基于数字辅助技术的SoC功率集成研究
摘要
当今SoC（System on Chip，系统级芯片）在个人移动信息终端中扮演着重要的角色。随着集成度的提高，外围的功率集成电路逐渐向片内集成。功率集成电路中传统的模拟控制方式，在先进工艺下集成于SoC时面临着诸多挑战。相比之下，数字电路有着更好的工艺兼容性和更强的信号处理能力。因此，本文从多个方面对数字辅助功率集成（Digital Assistant Power Integration，DAPI）技术进行了研究，包括数字辅助DC-DC变换器、数字控制DC-DC变换器、PMU（PowerManagement Unit，电源管理单元）以及PMU在SoC中的集成几个方面，实现了SoC中的高精度、高变换效率和高集成度的功率集成。本文的主要研究工作和创新包括：
（1）提出DC-DC变换器的数字误差校准方法：针对相位超前补偿方式环路增益较低、调整率较差的情况，在误差放大器的输出叠加补偿电流。通过复用误差放大器的差分电流输出，构建比较器用以检测输出电压是否在容差范围内，并通过有限状态机动态调整叠加的补偿电流，从而大幅度提高了变换器的调整率和输出电压精度。基于此方法研制的具有数字误差校准器的DC-DC变换器，很好地结合了数字控制方式和模拟控制方式的优点，具有高调整率、低误差、良好的瞬态响应等特性，非常适用于DVS（Dynamic Voltage Scaling）系统。在负载范围和以25mV为步进的DVS范围内，电压误差在±10mV以内。在负载电流为250mA时，输出电压在1.20V和0.85V之间变化，实现了上调压时间30μs，下调压时间32μs。由于相位超前补偿方式具有较小的无源器件，变换器实现了单片集成，并可在PMU中实现较高的集成度。
（2）提出了一种数字脉宽调制器（Digital Pulse Width Modulator，DPWM）的自校准方法：通过分析使得DPWM线性度降低的因素，在限制各个延迟单元控制码之间偏差的基础上，通过组合不同延迟时间的延迟单元，实现了线性度的提高。基于此方法研制的可综合2MHz10bit数字脉宽调制器实现了较高的线性度。其中，INL由校准前的-5.1，在完成自校准后降低到1.3；DNL由校准前的5.1，在完成自校准后降低到0.4。全数字方式实现的DPWM有良好的工艺兼容性和实现便捷性，为数字控制DC-DC变换器技术实现更高精度的输出提供了更好的选择。
（3）设计实现了多种方式的变换效率提升方法：为提升变换器变换效率，采用多种数字手段对变换器的工作进行增强，包括双模式工作、功率管自适应尺寸控制和数字式自适应死区时间控制。通过综合应用多种方法，降低了轻负载时的电流消耗，提升了变换器宽负载范围内的变换效率。本文提出的死区时间检测电路，通过检测功率管体二极管的开通情况，通过翻转边沿触发逻辑，从而及时打开N型功率管，达到了最短的死区时间。同其他形式的死区时间优化控制方法相比，具有更快的响应速度和更好的鲁棒性。在开关频率为2MHz的DC-DC变换器中综合应用以上效率提升方法，实现了最高91%，轻负载下维持80%以上的变换效率。
（4）设计并实现了一款数字控制双模式DC-DC变换器：通过在频率域处理ADC的差分输入电压，实现了小面积、高精度和具有良好工艺和温度稳定性的差分环形振荡器ADC；在z域构建IIR（Infinite Impulse Response，无限冲激响应）滤波器，补偿整个变换器环路；变换器在较重负载情况下工作于PWM（Pulse WidthModulation，脉宽调制模式）模式，在较轻负载下工作于PSM（Pulse SkippingModulation，脉冲跳跃模式）模式，可在较宽负载范围内保持较高的变换效率。
（5）设计并实现了带有双DVS功能的电源管理单元：采用时钟分相控制和地噪声隔离技术，提升了PMU中集成多个开关变换器的稳定性和兼容性。针对DVS速度的需求，发展了最大充电电流和PSM工作模式相结合的DVS策略，实现了高效、快速的DVS响应。
（6）将本文所研究的PMU在一款低功耗SoC芯片中进行集成。针对DVFS系统的不足，提出一种全新的AVS（Adaptive Voltage Scaling，自适应电压调节）实现架构，可以在不同的工艺偏差、温度变化和电压情况下，实现最优化的供电电压，使SoC达到最低的功率消耗。
In nowadays, SoC (System on Chip) is playing an important role in personalinformation devices. For higher level integration, extral power management integratedcircuits are becoming on-chip integration. Traditional power management ICs are basedon analog control, facing lots of challenges in advance technologies. In contrast, digitalcircuits perform better process compatibility and signal processing capability. Thedissertation focuses on Digital Assistant Power Integration (DAPI) technique, mainlyabout digital assistant DC-DC converter, digital controlled DC-DC converter, PMU(Power Management Unit) and PMU integration in SoC. Solutions are proposed torealize highly precise, high level integration and high efficiency power integration. Theresearches and innovations consist of:
(1) Digital error correction scheme in DC-DC converters is proposed. Given lowloop gain and bad regulation in phase lead compensation, compensation current is addedat output of error amplifier. Two comparators are designed by reusing output current oferror amplifier to detect whether output in tolerance range. Finite stage machine is usedto adjust compensation current. Regulation and output precision are greatly improved.DC-DC converter based on digital error correction is good combination of analog anddigital control schemes, performing good regulation, low error and fast response,suitable for DVS (Dynamic Voltage Scaling) systems. The output error is within10mVin load and25mV per step DVS range. The DVS speed are30μs and32μs for up anddown reference tracking, respectively. Because of small passive devices of phase leadcompensation, the converter is monolithically integrated and can be integrated in PMUwith small area.
(2) A self calibration scheme for DPWM (Digital Pulse Width Modulator) isproposed. The reasons of degeneration of linearity in DPWM are analyzed. Based onlimiting different of delay cell control words, linearity is improved by combination ofdelay cells with different delay. Full digital2MHz10bit implementation realizes highlinearity. After calibration, the INL and DNL are reduced from-5.1to1.3and from5.1to0.4, respectilvely. Full digital DPWM is compatible and convenient with different process. It provides good choice for digital controlled DC-DC converters with muchhigher precision outputs.
(3) Design and realization of conversion efficiency improvement techniques. Inorder to improve conversion efficiency, multi digital methods are used to enhanceoperation of power converter, including dual mode operation, adaptive power transistorsizing and adaptive dead time control. By using variable techniques, light load currentconsumption is reduced and efficiency in wide load range is improved. The dead timedetector proposed in the dissertation detects body diode conduction of power device.Logic is triggered by flip edge of detector output. N type power device is then opened,achieving minimum dead time. Comparing to other implementations, the proposedadaptive dead time control circuit performs faster response and better robustness. Thetechniques are used in a2MHz DC-DC converter and the peak efficiency is91%andabove80%at light load.
(4) Design and realization of digital controlled dual mode DC-DC converter:differential oscillator based ADC with small area, high conversion precision, goodprocess and temperature stability is realized by dealing with differential input of ADC infrequency domain. Digital compensator is built to compensate the converter by buildingIIR (Infinite Impulse Response) filter. The converter operates in PWM mode with heavyload and PSM mode with light load. High conversion efficiency is realized in wide loadrange.
(5) Design of PMU with dual DVS ability: Multi phase clock and substrate noiseisolation are used to improve stability and compatibility in PMU with several switchingDC-DC converters. In order to achieve fast and efficient DVS response, maximumcharging control and PSM control work together.
(6) Integration of PMU in a low power SoC: The chip functions well. A novel AVSarchitecture is given to further overcome the shortages of DVFS system. The novel AVSarchitecture can realize optimum supply voltage under different process, temperatureand voltage variations, enabling minimum power consumption of SoC.
（1）提出DC-DC变换器的数字误差校准方法：针对相位超前补偿方式环路增益较低、调整率较差的情况，在误差放大器的输出叠加补偿电流。通过复用误差放大器的差分电流输出，构建比较器用以检测输出电压是否在容差范围内，并通过有限状态机动态调整叠加的补偿电流，从而大幅度提高了变换器的调整率和输出电压精度。基于此方法研制的具有数字误差校准器的DC-DC变换器，很好地结合了数字控制方式和模拟控制方式的优点，具有高调整率、低误差、良好的瞬态响应等特性，非常适用于DVS（Dynamic Voltage Scaling）系统。在负载范围和以25mV为步进的DVS范围内，电压误差在±10mV以内。在负载电流为250mA时，输出电压在1.20V和0.85V之间变化，实现了上调压时间30μs，下调压时间32μs。由于相位超前补偿方式具有较小的无源器件，变换器实现了单片集成，并可在PMU中实现较高的集成度。
（2）提出了一种数字脉宽调制器（Digital Pulse Width Modulator，DPWM）的自校准方法：通过分析使得DPWM线性度降低的因素，在限制各个延迟单元控制码之间偏差的基础上，通过组合不同延迟时间的延迟单元，实现了线性度的提高。基于此方法研制的可综合2MHz10bit数字脉宽调制器实现了较高的线性度。其中，INL由校准前的-5.1，在完成自校准后降低到1.3；DNL由校准前的5.1，在完成自校准后降低到0.4。全数字方式实现的DPWM有良好的工艺兼容性和实现便捷性，为数字控制DC-DC变换器技术实现更高精度的输出提供了更好的选择。
（3）设计实现了多种方式的变换效率提升方法：为提升变换器变换效率，采用多种数字手段对变换器的工作进行增强，包括双模式工作、功率管自适应尺寸控制和数字式自适应死区时间控制。通过综合应用多种方法，降低了轻负载时的电流消耗，提升了变换器宽负载范围内的变换效率。本文提出的死区时间检测电路，通过检测功率管体二极管的开通情况，通过翻转边沿触发逻辑，从而及时打开N型功率管，达到了最短的死区时间。同其他形式的死区时间优化控制方法相比，具有更快的响应速度和更好的鲁棒性。在开关频率为2MHz的DC-DC变换器中综合应用以上效率提升方法，实现了最高91%，轻负载下维持80%以上的变换效率。
（4）设计并实现了一款数字控制双模式DC-DC变换器：通过在频率域处理ADC的差分输入电压，实现了小面积、高精度和具有良好工艺和温度稳定性的差分环形振荡器ADC；在z域构建IIR（Infinite Impulse Response，无限冲激响应）滤波器，补偿整个变换器环路；变换器在较重负载情况下工作于PWM（Pulse WidthModulation，脉宽调制模式）模式，在较轻负载下工作于PSM（Pulse SkippingModulation，脉冲跳跃模式）模式，可在较宽负载范围内保持较高的变换效率。
（5）设计并实现了带有双DVS功能的电源管理单元：采用时钟分相控制和地噪声隔离技术，提升了PMU中集成多个开关变换器的稳定性和兼容性。针对DVS速度的需求，发展了最大充电电流和PSM工作模式相结合的DVS策略，实现了高效、快速的DVS响应。
（6）将本文所研究的PMU在一款低功耗SoC芯片中进行集成。针对DVFS系统的不足，提出一种全新的AVS（Adaptive Voltage Scaling，自适应电压调节）实现架构，可以在不同的工艺偏差、温度变化和电压情况下，实现最优化的供电电压，使SoC达到最低的功率消耗。
In nowadays, SoC (System on Chip) is playing an important role in personalinformation devices. For higher level integration, extral power management integratedcircuits are becoming on-chip integration. Traditional power management ICs are basedon analog control, facing lots of challenges in advance technologies. In contrast, digitalcircuits perform better process compatibility and signal processing capability. Thedissertation focuses on Digital Assistant Power Integration (DAPI) technique, mainlyabout digital assistant DC-DC converter, digital controlled DC-DC converter, PMU(Power Management Unit) and PMU integration in SoC. Solutions are proposed torealize highly precise, high level integration and high efficiency power integration. Theresearches and innovations consist of:
(1) Digital error correction scheme in DC-DC converters is proposed. Given lowloop gain and bad regulation in phase lead compensation, compensation current is addedat output of error amplifier. Two comparators are designed by reusing output current oferror amplifier to detect whether output in tolerance range. Finite stage machine is usedto adjust compensation current. Regulation and output precision are greatly improved.DC-DC converter based on digital error correction is good combination of analog anddigital control schemes, performing good regulation, low error and fast response,suitable for DVS (Dynamic Voltage Scaling) systems. The output error is within10mVin load and25mV per step DVS range. The DVS speed are30μs and32μs for up anddown reference tracking, respectively. Because of small passive devices of phase leadcompensation, the converter is monolithically integrated and can be integrated in PMUwith small area.
(2) A self calibration scheme for DPWM (Digital Pulse Width Modulator) isproposed. The reasons of degeneration of linearity in DPWM are analyzed. Based onlimiting different of delay cell control words, linearity is improved by combination ofdelay cells with different delay. Full digital2MHz10bit implementation realizes highlinearity. After calibration, the INL and DNL are reduced from-5.1to1.3and from5.1to0.4, respectilvely. Full digital DPWM is compatible and convenient with different process. It provides good choice for digital controlled DC-DC converters with muchhigher precision outputs.
(3) Design and realization of conversion efficiency improvement techniques. Inorder to improve conversion efficiency, multi digital methods are used to enhanceoperation of power converter, including dual mode operation, adaptive power transistorsizing and adaptive dead time control. By using variable techniques, light load currentconsumption is reduced and efficiency in wide load range is improved. The dead timedetector proposed in the dissertation detects body diode conduction of power device.Logic is triggered by flip edge of detector output. N type power device is then opened,achieving minimum dead time. Comparing to other implementations, the proposedadaptive dead time control circuit performs faster response and better robustness. Thetechniques are used in a2MHz DC-DC converter and the peak efficiency is91%andabove80%at light load.
(4) Design and realization of digital controlled dual mode DC-DC converter:differential oscillator based ADC with small area, high conversion precision, goodprocess and temperature stability is realized by dealing with differential input of ADC infrequency domain. Digital compensator is built to compensate the converter by buildingIIR (Infinite Impulse Response) filter. The converter operates in PWM mode with heavyload and PSM mode with light load. High conversion efficiency is realized in wide loadrange.
(5) Design of PMU with dual DVS ability: Multi phase clock and substrate noiseisolation are used to improve stability and compatibility in PMU with several switchingDC-DC converters. In order to achieve fast and efficient DVS response, maximumcharging control and PSM control work together.
(6) Integration of PMU in a low power SoC: The chip functions well. A novel AVSarchitecture is given to further overcome the shortages of DVFS system. The novel AVSarchitecture can realize optimum supply voltage under different process, temperatureand voltage variations, enabling minimum power consumption of SoC.
引文
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