基于新型FPGA的自可重构系统设计研究
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摘要
最近几年,可重构计算和软硬件协同设计是当前计算机科研领域的两大核心,其任务建模平台大多是基于FPGA的动态可重构系统,而可重构系统也是最近几年学术领域研究的热点问题。本论文的核心工作就是围绕着新型FPGA架构设计以及基于新型FPGA的动态可重构系统设计展开的。
可重构系统设计中有两个关键问题:任务重构时间和系统功耗。本论文一共包含三个方面的内容。第一,我们从平台工具FPGA器件入手,提出了一种新型的FPGA架构,在提高了器件逻辑密度和系统的资源利用率的同时,大大减少了FPGA的动态重构时间和功耗,这种新型的FPGA器件也是下面两部分工作的基础;第二,我们设计一套新的可重构系统的设计方法,重构数据传输采用处理器本地高速总线,并提出了任务状态直接控制的概念,进一步提高的可重构系统的性能;第三,在可重构系统的软件设计方面,基于首次自适应算法,我们提出了一种基于可重构系统的硬件调度算法,从任务调度的角度减少系统的重构功耗。以上三个方面的工作为可重构计算以及软硬件混合任务系统的设计提供了重要前提,而可重构计算也将是下一阶段我们工作的重点。
Recently reconfigurable computing and software-hardware system co-design are two current issues, and their models are both based on reconfigurable system, meanwhile FPGA-based reconfigurable system is the pivotal concerning in the passing years. The key work in the thesis is related to novel FPGA-based dynamic reconfigurable system.
In this thesis, our work includes three aspects. Firstly, we sponsor a novel FPGA architecture, which not only improves the logic intensity and resource usage in the device, but greatly reduce reconfigurable time and power dissipation. At the same time, communication issue is also handled. Secondly, we design a new set of development chain for reconfiguration, and address the concept about task status access (TSA) to order to solve many tough problems, such as preemptive hardware task scheduling, hardware resource defragment, and so on. It's beneficial for solving real time task immigration in software-hardware system in the future. Finally, with respect to software design on the reconfigurable system, we make a novel and high-efficient hardware scheduling algorithm based on first-fit self-adaptive algorithm. With this algorithm, the power consumption will decrease.
To sum up, all three problems we target are relative to reconfigurable computing and software-hardware mixed system, which will be our emphasis in the next term.
可重构系统设计中有两个关键问题:任务重构时间和系统功耗。本论文一共包含三个方面的内容。第一,我们从平台工具FPGA器件入手,提出了一种新型的FPGA架构,在提高了器件逻辑密度和系统的资源利用率的同时,大大减少了FPGA的动态重构时间和功耗,这种新型的FPGA器件也是下面两部分工作的基础;第二,我们设计一套新的可重构系统的设计方法,重构数据传输采用处理器本地高速总线,并提出了任务状态直接控制的概念,进一步提高的可重构系统的性能;第三,在可重构系统的软件设计方面,基于首次自适应算法,我们提出了一种基于可重构系统的硬件调度算法,从任务调度的角度减少系统的重构功耗。以上三个方面的工作为可重构计算以及软硬件混合任务系统的设计提供了重要前提,而可重构计算也将是下一阶段我们工作的重点。
Recently reconfigurable computing and software-hardware system co-design are two current issues, and their models are both based on reconfigurable system, meanwhile FPGA-based reconfigurable system is the pivotal concerning in the passing years. The key work in the thesis is related to novel FPGA-based dynamic reconfigurable system.
In this thesis, our work includes three aspects. Firstly, we sponsor a novel FPGA architecture, which not only improves the logic intensity and resource usage in the device, but greatly reduce reconfigurable time and power dissipation. At the same time, communication issue is also handled. Secondly, we design a new set of development chain for reconfiguration, and address the concept about task status access (TSA) to order to solve many tough problems, such as preemptive hardware task scheduling, hardware resource defragment, and so on. It's beneficial for solving real time task immigration in software-hardware system in the future. Finally, with respect to software design on the reconfigurable system, we make a novel and high-efficient hardware scheduling algorithm based on first-fit self-adaptive algorithm. With this algorithm, the power consumption will decrease.
To sum up, all three problems we target are relative to reconfigurable computing and software-hardware mixed system, which will be our emphasis in the next term.
引文
[1] Brebner G. A Virtual Hardware Operating System for the Xilinx XC6200[A], The 6th International Workshop on Field-Programmable Logic and Applications (FPL)[C],Darmstadt,Germany, 1996,327-336
[2] Wigley G B., Kearney D. A.. Research Issues in Operating Systems for Reconfigurable Computing[A], The International Conference on Engineering Reconfigurable Systems and Architecture[C], LasVegas, USA, 2002,232-240
[3] Steiger C, Walder H., Platzner M..Operating Systems for Reconfigurable Embedded Platforms Online Scheduling of Real-Time Tasks[J], IEEE Transaction on Computers, 2004,53(11):1393-1407
[4] Walder H., Platzner M.. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations[J], Engineering of Reconfigurable Systems and Algorithms, 2003,24(5):84-287
[5] Baskaran K., SrikanthanA T. Hardware Operating System based Approach for Run-time Reconfigurable Platform of Embeded Devices[A], The 6th Real-time Linux(RTL) Workshop[C],Singapore, 2004,92-96
[6] Rissa T, Niittylahti J.. A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs[A], The 10th International Conference on Field-Programmable Logic and its Applications(FPL)[C], Villach, Austria, 2000,371-378
[7] Wiangtong T., Cheung P. Y.K., Luk W.. A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer[A], The 13th International Conference on Field-Programmable Logic and its Applications(FPL)[C], Lisbon, Portugal, 2003,396-405
[8] Ericson M., Johansson M.. A General Purpose Embedded System Utilizing Runtime Reconfiguration[A], The International Conference on Reconfigurable Computing and FPGAs ReConFig[C], Colima, Mexico, Sep 2004,483-490
[9] Kwok-Hay S. H., Tkachenko A., Brodersen R.. A Unified Hardware Software Runtime Environment for FPGA Based Reconfigurable Computers using BORPH[A], The IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis(CODES+ISSS)[C], Seoul, Korea, Oct., 2006, 259-264
[10] Agron J., Peck W., Anderson E., Andrews D.. Run-Time Services for Hybrid CPU/FPGA Systems on Chip[A], The 27th IEEE International Real-Time Systems Symposium (RTSS)[C],Rio de Janeiro,Brazil, 2006, 312-318
[11] Horta E.L., Lockwood J.W., Kofuji S.. Using PARBIT to Implement Partial Run-time Reconfigurable Systems[A], The 12th Field-Programmable Logic and Applications(FPL)[C], La Grande Motte, France,Sep 2002, 182-191
[12] Xilinx Inc.. Virtex-4 configuration guide[M], UserGuide 071, vl.1, 2004
[13] Sedcole P., Blodget B., Becker T, Anderson J., Lysaght P.. Modular dynamic reconfiguration in Virtex FPGAs[J], IEEE Proc Computer Digital Tech, May 2006, 153(3):457-463
[14] Zhou B., Qiu W., Peng C. An Operating System Framework for Reconfigurable Systems[A],The 5th International Conference on Computer and Information Technology(CIT)[C],Shanghai,China, 2005, 23-27
[15] Bazargan K., Kastner R., Sarrafzadeh M.. Fast Template Placement for Re-configurable Computing Systems[J], IEEE Design and Test of Computers, 2000,17(3):68-83
[16] Handa M., Vemuri R.. Area Fragmentation in Reconfigurable Operating Systems[A], The 14th International Conference on Field Programmable Logic and Applications (FPL)[C], Leuven,Belgium, 2004, 173-179
[17] Walder H., Platzner M.. Fast On-line Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing[A], The 17th International Parallel & Distributed Processing Symposium (IPDPS)[C], Nice, France, Apr 2003,220-226
[18] Handa M., Vemuri R.. An Efficient Algorithm For Finding Empty Space For Online FPGA Placement[A], The 41th Desgin Automation Conference(DAC)[C], San Diego,CA,USA, 2004,960-965
[19] Tabero J., Septien J., Mecha H., Mozos D.. A Vertex-List Approach to 2D HW Multitasking Management in RTR FPGAs[A], The 18th International Conference on Design of Circuits and Integrated Systems(DCIS)[C], 2003,312-320
[20] Yoo S. M., Youn H. Y., Shirazi B.. An Efficient Task Allocation Scheme for 2D Mesh Architectures[J], IEEE Transaction of Parallel Distributing System, 1997,8(9):934-942
[21] O.Diessel, H.EIGindy, M.Middendorf, H.Schmeck and B.Schmidt, "Dynamic scheduling of tasks on partially reconfigurable FPGAS". In IEE Proc-Comput.Digit.Tech.Vol. 147, No.3, May 2000.
[22] Edson L. Horta, John W.Lockwood, David Parlour, "Dynamic Hardware Plugins in an FPGA with Partial Run-time Reconfiguration", In DAC 2002, June 10-14,2002.
[23] Steve Guccione, Delon Levi and Prasanna Sundararajan:JBits, "Java based interface for reconfigurable computing", Xilinx Inc, 1999.
[24] Michael Rencher and Brad L. Hutchings. "Automated target recognition on SPLASH-2",Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p192-200, Apr 1997.
[25] Jack Jean, Xuejun Liang, Brian Drozd, and Karen Tomko, "Accelerating an IR 3automatic target recognition application with FPGAs", Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p290-291, Apr 1999.
[26] Alexandre F.Tenca and Milos D.Ercegovac, "A variable long-precision arithmetic unit design for reconfigurable coprocessor architectures", Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p216-225, Apr 1998.
[27] Paul Graham and Brent Nelson, "Frequency-domain sonar processing in FPGAs and DSPs",Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pages 304-305,April 1998.
[28] Emeka Mosanya and Eduardo Sanchez, "A FPGA-based hardware implementation of generalized profile search using online arithmetic", Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, p101-111, Feb 1999.
[29] Andy G. Ye and David M. Lewis, "Procedural Texture Mapping on FPGAs", Proceedings of the ACM/SIGDA International Sympisium on FPGA, p112-120, Feb 1999.
[30] P.Zhong, M.Martonosi and P.Ashar, "FPGA-based SAT solver architecture with near-zero systhesis and layout overhead', IEE Proc.-Comput, Digit. Tech, Vol.147, No.3, p135-141, May2000.
[31] A.Stocia, D. Keymeulen, V. Duong, and C. Salazar-Lazaro, "Automatic synthesis and fault-tolerant experiments on an evolvable hardware platform", IEEE Aerospace Conference Porceedings, Vol. 5, Pags 465-471,2000.
[32] J.D.Lohn, G.L. Haith, S.P.Colombano, and D.Stassinopoulos, "Towards evolving circuits for autonomous space applications", IEEE Aerospace Conference Proceedings, Vol. 5,2000.
[33] C. Chen M. Sarrafzadeh, "Provably Good Algorithm for Low Power Consumption with Dual Supply Voltages", Proceedings of the 1999 international Conference on Cpmputer Aided Design,1999.
[34] F. LI Y. Lin L. He et al, "low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics", ACM International Symposium on FPGA, February 2004.
[35] E. Ahmed, J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density", ACM International Symposium on FPGA, 2000
[36] F. LI, D. Chen, L He and J. Cong, "Architecture Evaluation for Power-Efficient FPGAs", ACM International Symposium on FPGA, February 2003.
[37] J. Rose and S. Brown, "Flexibility of Interconnection Structures for Field -Programmable Gate Arrays",JSSC,March 1991.
[38] Zhu Mingcheng, Huang Qiang, "The Initial Study on Dynamically Re-configurable Logic System Based on FPGA", Cortege of imformation Engineering, Shenzhen University.
[39] Satnam Singh, Jonathan Hogg and Derek McAuley, "Expressing Dynamic Reconfiguration by Partial Evaluation", FCCM'96. IEEE Computer Society, 1996.
[40] A. Thompson, "An evolved circuit, intrinsic in silicon, entwined with physics", EvolvableSystems:From Biology to Hardware, vol. 1259, pp. 390-405,1997.
[41] A. Thompson and P. Layzell, "Evolution of robustness in an electronics design", Proc.of Evolvable Systems: From Biology to Hardware,, vol. 1801, pp. 218-228,2000.
[42] D.-W. Lee, C.-B. Ban, K.-B. Sim, H.-S. Seok, Lee Kwang-Ju, and B.-T. Zhang,"Behaviorevolution of autonomous mobile robot using genetic programming based on evolvablehardware", Proceeding of 2000 IEEE International Conference on Systems,Man, and Cybernetics, vol. 5, pp. 3835-3840,2000.
[43] G. Hollingworth, S. Smith, and A. Tyrrell, "The intrinsic evolution of Virtex devicesthrough Internet reconfigurable logic", Evolvable Systems: From Biology to Hardware,Proceedings, vol.1801, pp. 72-79,2000.
[24] A. M. Tyrrell, R. A. Krohling, and Y. Zhou, "Evolutionary algorithm for the promotion of evolvable hardware", IEE Proceedings-Computers and Digital Techniques, vol. 151, pp. 267-275,2004.
[45] XilinxCorp., "XAPP 290: Two Flows for Partial Reconfiguration: Module Based or Difference Based", www.xilinx.com, Sept, 2004.
[46] A.Upegui, C. A. Pela-Reyes, and E. Sanchez, "An FPGA platform for on-line topology exploration of spiking neural networks", Microprocessors and Microsystems, in press, 2005.
[47] A. Upegui, C. A. Pela-Reyes, and E. Sanchez, "A methodology for evolving spiking neural-network topologies on line using partial dynamic reconfiguration", presented at ICCI -International Conference on Computational Intelligence, Medellin, Colombia, 2003.
[48] G. Mermoud, A.Upegui, C.A. Pela-Reyes, and E. Sanchez, "A Dynamically-Reconfigurable FPGA Platform for Evolving Fuzzy Systems", in The 8th International Work-Conference on Artificial Neural Networks (IWANN'2005), 2005.
[49] B. Blodget, P. James-Roxby, E. Keller, S. McMillan, and P. Sundararajan, "A selfreconfiguring platform", Proceedings of Field-Programmable Logic and Applications, vol. 2778, pp. 565-574,2003.
[50] Xilinx_Corp., "XAPP 151: Virtex Series Configuration Architecture User Guide",www.xilinx.com, Oct 2004.
[51] Andres Upegui, Eduardo Sanchez, "Evolving Hardware by Dynamically Reconfiguring", Ecole Poly technique Federate de Lausanne - EPFL, 1015 Lausanne, Switzerland.
[52] B.Ouni, A.Mtibaa, M. Abid, "Time Partitioning Framework for fully Reconfigurable Systems", The 16th International Conference on Microelectronics, ICM'04, December 6 - 8,2004.
[53] By Bouraoui Ouni and Abdellatif Mtibaa, "Approach of Heuristic Algorithm for Time Partitioning problem", Dedicated Systems Magazine, 2005.
[54] Eric Keller and Scott McMillan, "An FPGAWire Database for Run-Time Routers", Xilinx Inc,2003.
[55] Sundararajan, Prasanna; Guccione, Steven A.; Levi, Delon, "XHWIF: a portable hardware interface for reconfigurable computing", Proc. SPIE Vol. 4525, p. 155-160, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry; Eds, July 2001.
[56] The Hoplite Guide to Run-Time Reconfiguration Computing, Hoplite Systems LLC, Dec 2004.
[57] Delon Levi and Steven A. Guccione, John Schewel, "BoardScope: A Debug Tool for Reconfigurable Systems", Configurable Computing: Technology and Applications, Proc. SPIE 3526, Bellingham WA, November 1998.
[58] Steven A. Guccione, "Portable Native Methods in Java", Xilinx,2100 Logic Drive,San Jose, CA95124-3450.
[59] Virtex-II Platform FPGA User Guide, Xilinx, 2005.
[60] Vaughn Betz, Jonathan Rose, "Architecture and CAD for Deep-Submicron FPGAs", Kluwer Academic Publishers, 2000.
[2] Wigley G B., Kearney D. A.. Research Issues in Operating Systems for Reconfigurable Computing[A], The International Conference on Engineering Reconfigurable Systems and Architecture[C], LasVegas, USA, 2002,232-240
[3] Steiger C, Walder H., Platzner M..Operating Systems for Reconfigurable Embedded Platforms Online Scheduling of Real-Time Tasks[J], IEEE Transaction on Computers, 2004,53(11):1393-1407
[4] Walder H., Platzner M.. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations[J], Engineering of Reconfigurable Systems and Algorithms, 2003,24(5):84-287
[5] Baskaran K., SrikanthanA T. Hardware Operating System based Approach for Run-time Reconfigurable Platform of Embeded Devices[A], The 6th Real-time Linux(RTL) Workshop[C],Singapore, 2004,92-96
[6] Rissa T, Niittylahti J.. A Hybrid Prototyping Platform for Dynamically Reconfigurable Designs[A], The 10th International Conference on Field-Programmable Logic and its Applications(FPL)[C], Villach, Austria, 2000,371-378
[7] Wiangtong T., Cheung P. Y.K., Luk W.. A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer[A], The 13th International Conference on Field-Programmable Logic and its Applications(FPL)[C], Lisbon, Portugal, 2003,396-405
[8] Ericson M., Johansson M.. A General Purpose Embedded System Utilizing Runtime Reconfiguration[A], The International Conference on Reconfigurable Computing and FPGAs ReConFig[C], Colima, Mexico, Sep 2004,483-490
[9] Kwok-Hay S. H., Tkachenko A., Brodersen R.. A Unified Hardware Software Runtime Environment for FPGA Based Reconfigurable Computers using BORPH[A], The IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis(CODES+ISSS)[C], Seoul, Korea, Oct., 2006, 259-264
[10] Agron J., Peck W., Anderson E., Andrews D.. Run-Time Services for Hybrid CPU/FPGA Systems on Chip[A], The 27th IEEE International Real-Time Systems Symposium (RTSS)[C],Rio de Janeiro,Brazil, 2006, 312-318
[11] Horta E.L., Lockwood J.W., Kofuji S.. Using PARBIT to Implement Partial Run-time Reconfigurable Systems[A], The 12th Field-Programmable Logic and Applications(FPL)[C], La Grande Motte, France,Sep 2002, 182-191
[12] Xilinx Inc.. Virtex-4 configuration guide[M], UserGuide 071, vl.1, 2004
[13] Sedcole P., Blodget B., Becker T, Anderson J., Lysaght P.. Modular dynamic reconfiguration in Virtex FPGAs[J], IEEE Proc Computer Digital Tech, May 2006, 153(3):457-463
[14] Zhou B., Qiu W., Peng C. An Operating System Framework for Reconfigurable Systems[A],The 5th International Conference on Computer and Information Technology(CIT)[C],Shanghai,China, 2005, 23-27
[15] Bazargan K., Kastner R., Sarrafzadeh M.. Fast Template Placement for Re-configurable Computing Systems[J], IEEE Design and Test of Computers, 2000,17(3):68-83
[16] Handa M., Vemuri R.. Area Fragmentation in Reconfigurable Operating Systems[A], The 14th International Conference on Field Programmable Logic and Applications (FPL)[C], Leuven,Belgium, 2004, 173-179
[17] Walder H., Platzner M.. Fast On-line Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing[A], The 17th International Parallel & Distributed Processing Symposium (IPDPS)[C], Nice, France, Apr 2003,220-226
[18] Handa M., Vemuri R.. An Efficient Algorithm For Finding Empty Space For Online FPGA Placement[A], The 41th Desgin Automation Conference(DAC)[C], San Diego,CA,USA, 2004,960-965
[19] Tabero J., Septien J., Mecha H., Mozos D.. A Vertex-List Approach to 2D HW Multitasking Management in RTR FPGAs[A], The 18th International Conference on Design of Circuits and Integrated Systems(DCIS)[C], 2003,312-320
[20] Yoo S. M., Youn H. Y., Shirazi B.. An Efficient Task Allocation Scheme for 2D Mesh Architectures[J], IEEE Transaction of Parallel Distributing System, 1997,8(9):934-942
[21] O.Diessel, H.EIGindy, M.Middendorf, H.Schmeck and B.Schmidt, "Dynamic scheduling of tasks on partially reconfigurable FPGAS". In IEE Proc-Comput.Digit.Tech.Vol. 147, No.3, May 2000.
[22] Edson L. Horta, John W.Lockwood, David Parlour, "Dynamic Hardware Plugins in an FPGA with Partial Run-time Reconfiguration", In DAC 2002, June 10-14,2002.
[23] Steve Guccione, Delon Levi and Prasanna Sundararajan:JBits, "Java based interface for reconfigurable computing", Xilinx Inc, 1999.
[24] Michael Rencher and Brad L. Hutchings. "Automated target recognition on SPLASH-2",Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p192-200, Apr 1997.
[25] Jack Jean, Xuejun Liang, Brian Drozd, and Karen Tomko, "Accelerating an IR 3automatic target recognition application with FPGAs", Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p290-291, Apr 1999.
[26] Alexandre F.Tenca and Milos D.Ercegovac, "A variable long-precision arithmetic unit design for reconfigurable coprocessor architectures", Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p216-225, Apr 1998.
[27] Paul Graham and Brent Nelson, "Frequency-domain sonar processing in FPGAs and DSPs",Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pages 304-305,April 1998.
[28] Emeka Mosanya and Eduardo Sanchez, "A FPGA-based hardware implementation of generalized profile search using online arithmetic", Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, p101-111, Feb 1999.
[29] Andy G. Ye and David M. Lewis, "Procedural Texture Mapping on FPGAs", Proceedings of the ACM/SIGDA International Sympisium on FPGA, p112-120, Feb 1999.
[30] P.Zhong, M.Martonosi and P.Ashar, "FPGA-based SAT solver architecture with near-zero systhesis and layout overhead', IEE Proc.-Comput, Digit. Tech, Vol.147, No.3, p135-141, May2000.
[31] A.Stocia, D. Keymeulen, V. Duong, and C. Salazar-Lazaro, "Automatic synthesis and fault-tolerant experiments on an evolvable hardware platform", IEEE Aerospace Conference Porceedings, Vol. 5, Pags 465-471,2000.
[32] J.D.Lohn, G.L. Haith, S.P.Colombano, and D.Stassinopoulos, "Towards evolving circuits for autonomous space applications", IEEE Aerospace Conference Proceedings, Vol. 5,2000.
[33] C. Chen M. Sarrafzadeh, "Provably Good Algorithm for Low Power Consumption with Dual Supply Voltages", Proceedings of the 1999 international Conference on Cpmputer Aided Design,1999.
[34] F. LI Y. Lin L. He et al, "low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics", ACM International Symposium on FPGA, February 2004.
[35] E. Ahmed, J. Rose, "The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density", ACM International Symposium on FPGA, 2000
[36] F. LI, D. Chen, L He and J. Cong, "Architecture Evaluation for Power-Efficient FPGAs", ACM International Symposium on FPGA, February 2003.
[37] J. Rose and S. Brown, "Flexibility of Interconnection Structures for Field -Programmable Gate Arrays",JSSC,March 1991.
[38] Zhu Mingcheng, Huang Qiang, "The Initial Study on Dynamically Re-configurable Logic System Based on FPGA", Cortege of imformation Engineering, Shenzhen University.
[39] Satnam Singh, Jonathan Hogg and Derek McAuley, "Expressing Dynamic Reconfiguration by Partial Evaluation", FCCM'96. IEEE Computer Society, 1996.
[40] A. Thompson, "An evolved circuit, intrinsic in silicon, entwined with physics", EvolvableSystems:From Biology to Hardware, vol. 1259, pp. 390-405,1997.
[41] A. Thompson and P. Layzell, "Evolution of robustness in an electronics design", Proc.of Evolvable Systems: From Biology to Hardware,, vol. 1801, pp. 218-228,2000.
[42] D.-W. Lee, C.-B. Ban, K.-B. Sim, H.-S. Seok, Lee Kwang-Ju, and B.-T. Zhang,"Behaviorevolution of autonomous mobile robot using genetic programming based on evolvablehardware", Proceeding of 2000 IEEE International Conference on Systems,Man, and Cybernetics, vol. 5, pp. 3835-3840,2000.
[43] G. Hollingworth, S. Smith, and A. Tyrrell, "The intrinsic evolution of Virtex devicesthrough Internet reconfigurable logic", Evolvable Systems: From Biology to Hardware,Proceedings, vol.1801, pp. 72-79,2000.
[24] A. M. Tyrrell, R. A. Krohling, and Y. Zhou, "Evolutionary algorithm for the promotion of evolvable hardware", IEE Proceedings-Computers and Digital Techniques, vol. 151, pp. 267-275,2004.
[45] XilinxCorp., "XAPP 290: Two Flows for Partial Reconfiguration: Module Based or Difference Based", www.xilinx.com, Sept, 2004.
[46] A.Upegui, C. A. Pela-Reyes, and E. Sanchez, "An FPGA platform for on-line topology exploration of spiking neural networks", Microprocessors and Microsystems, in press, 2005.
[47] A. Upegui, C. A. Pela-Reyes, and E. Sanchez, "A methodology for evolving spiking neural-network topologies on line using partial dynamic reconfiguration", presented at ICCI -International Conference on Computational Intelligence, Medellin, Colombia, 2003.
[48] G. Mermoud, A.Upegui, C.A. Pela-Reyes, and E. Sanchez, "A Dynamically-Reconfigurable FPGA Platform for Evolving Fuzzy Systems", in The 8th International Work-Conference on Artificial Neural Networks (IWANN'2005), 2005.
[49] B. Blodget, P. James-Roxby, E. Keller, S. McMillan, and P. Sundararajan, "A selfreconfiguring platform", Proceedings of Field-Programmable Logic and Applications, vol. 2778, pp. 565-574,2003.
[50] Xilinx_Corp., "XAPP 151: Virtex Series Configuration Architecture User Guide",www.xilinx.com, Oct 2004.
[51] Andres Upegui, Eduardo Sanchez, "Evolving Hardware by Dynamically Reconfiguring", Ecole Poly technique Federate de Lausanne - EPFL, 1015 Lausanne, Switzerland.
[52] B.Ouni, A.Mtibaa, M. Abid, "Time Partitioning Framework for fully Reconfigurable Systems", The 16th International Conference on Microelectronics, ICM'04, December 6 - 8,2004.
[53] By Bouraoui Ouni and Abdellatif Mtibaa, "Approach of Heuristic Algorithm for Time Partitioning problem", Dedicated Systems Magazine, 2005.
[54] Eric Keller and Scott McMillan, "An FPGAWire Database for Run-Time Routers", Xilinx Inc,2003.
[55] Sundararajan, Prasanna; Guccione, Steven A.; Levi, Delon, "XHWIF: a portable hardware interface for reconfigurable computing", Proc. SPIE Vol. 4525, p. 155-160, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III, John Schewel; Peter M. Athanas; Philip B. James-Roxby; John T. McHenry; Eds, July 2001.
[56] The Hoplite Guide to Run-Time Reconfiguration Computing, Hoplite Systems LLC, Dec 2004.
[57] Delon Levi and Steven A. Guccione, John Schewel, "BoardScope: A Debug Tool for Reconfigurable Systems", Configurable Computing: Technology and Applications, Proc. SPIE 3526, Bellingham WA, November 1998.
[58] Steven A. Guccione, "Portable Native Methods in Java", Xilinx,2100 Logic Drive,San Jose, CA95124-3450.
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