FPGA远程动态重构系统的设计与实现
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摘要
进入21世纪,FPGA (Field Programmable Gate Array,现场可编程门阵列)技术发展迅猛,已经在自动机器人、卫星和智能家电等应用领域发挥了关键作用。将FPGA动态重构技术和互联网技术相结合,可以使电子设备具有硬件自主修复和远程实时更新升级的能力,从而大幅提高系统的可靠性和安全性,因此基于FPGA的远程动态重构系统已成为近年来FPGA领域的一个研究热点。本文应用Mentor公司和Xilinx公司的多种软件工具,研究了基于FPGA的远程动态重构技术并完成了相关系统的设计与实现。
首先根据IRL (Internet Reconfigurable Logic,互联网可重配置逻辑)设计理念设计了一种FPGA远程动态重构系统,使系统具有远程实时更新升级的能力。采用网络通信技术,远程主机端中的更新文件可以通过以太网传送到本系统中,并应用全局动态重构技术对FPGA终端系统进行重新配置。
其次,为了验证上述系统方案的可行性,结合可重构技术的两个主要用途——功能转换和硬件容错,应用HDL语言设计了FPGA远程动态重构系统的密码算法和存储器内建自测试两大功能模块。将密钥固化在FPGA芯片内部的块RAM中,并应用局部动态重构技术进行DES密码算法的加解密功能转换；插入内建自测试电路检测FPGA芯片内部存储器的故障,若有故障,则应用局部动态重构技术将故障模块替换为无故障模块。
最终在XUP Virtex-ⅡPro硬件平台上实现了本系统并进行了远程动态重构试验,证明了系统的可行性和优越性,整个远程动态重构过程中FPGA系统可以不断电正常工作,达到了远程实时更新升级的目的。
In the 21st century, FPGA(Field Programmable Gate Array) technology is developing quickly, and has played a key role in some application fields, such as automatic robots, satellite, intelligent home appliance and so on. FPGA dynamic reconfigurable technology combined with Internet can make electronic equipment have the abilities of self-repair and remote real time updating, so that the reliability and safety of the systems can be greatly improved. For this reason, remote dynamic reconfigurable system based on FPGA has been a research hotspot of FPGA field in recent years. With a variety of Mentor's and Xilinx's software tools, this paper researched remote dynamic reconfigurable technology based on FPGA, and accomplished the design and implementation of relative system.
Firstly, according to IRL (Internet Reconfigurable Logic) design concept, a remote dynamic reconfigurable system based on FPGA was designed, which has the ability of remote real time updating. Depending on network communication technology, the update files in remote host can be transmitted to this system via ethernet, and reconfigure the system with overall dynamic reconfigurable technology.
Secondly, according to two applications of reconfigurable technology, which are function transformation and fault-tolerance, two function modules were designed with HDL language, Cipher and MBIST, to virefy the feasibility of the above-mentioned system scheme. The key of cipher resides in internal bram of FPGA chip, and functions of DES cipher, encryption and decryption, are transformed with partial dynamic reconfigurable technology. BIST circuits are inserted into internal memory of FPGA chip to detect faults. If there is any fault, also with partial dynamic reconfigurable technology, faulty module can be replaced with trouble-free module.
Finally, to prove its feasibility and advantages, the system was implemented on XUP Virtex-II Pro hardware platform and tested remote dynamic reconfigurable technology. During the entire process, FPGA system always keeps electrifying, and has achieved the goal of remote real time updating.
首先根据IRL (Internet Reconfigurable Logic,互联网可重配置逻辑)设计理念设计了一种FPGA远程动态重构系统,使系统具有远程实时更新升级的能力。采用网络通信技术,远程主机端中的更新文件可以通过以太网传送到本系统中,并应用全局动态重构技术对FPGA终端系统进行重新配置。
其次,为了验证上述系统方案的可行性,结合可重构技术的两个主要用途——功能转换和硬件容错,应用HDL语言设计了FPGA远程动态重构系统的密码算法和存储器内建自测试两大功能模块。将密钥固化在FPGA芯片内部的块RAM中,并应用局部动态重构技术进行DES密码算法的加解密功能转换；插入内建自测试电路检测FPGA芯片内部存储器的故障,若有故障,则应用局部动态重构技术将故障模块替换为无故障模块。
最终在XUP Virtex-ⅡPro硬件平台上实现了本系统并进行了远程动态重构试验,证明了系统的可行性和优越性,整个远程动态重构过程中FPGA系统可以不断电正常工作,达到了远程实时更新升级的目的。
In the 21st century, FPGA(Field Programmable Gate Array) technology is developing quickly, and has played a key role in some application fields, such as automatic robots, satellite, intelligent home appliance and so on. FPGA dynamic reconfigurable technology combined with Internet can make electronic equipment have the abilities of self-repair and remote real time updating, so that the reliability and safety of the systems can be greatly improved. For this reason, remote dynamic reconfigurable system based on FPGA has been a research hotspot of FPGA field in recent years. With a variety of Mentor's and Xilinx's software tools, this paper researched remote dynamic reconfigurable technology based on FPGA, and accomplished the design and implementation of relative system.
Firstly, according to IRL (Internet Reconfigurable Logic) design concept, a remote dynamic reconfigurable system based on FPGA was designed, which has the ability of remote real time updating. Depending on network communication technology, the update files in remote host can be transmitted to this system via ethernet, and reconfigure the system with overall dynamic reconfigurable technology.
Secondly, according to two applications of reconfigurable technology, which are function transformation and fault-tolerance, two function modules were designed with HDL language, Cipher and MBIST, to virefy the feasibility of the above-mentioned system scheme. The key of cipher resides in internal bram of FPGA chip, and functions of DES cipher, encryption and decryption, are transformed with partial dynamic reconfigurable technology. BIST circuits are inserted into internal memory of FPGA chip to detect faults. If there is any fault, also with partial dynamic reconfigurable technology, faulty module can be replaced with trouble-free module.
Finally, to prove its feasibility and advantages, the system was implemented on XUP Virtex-II Pro hardware platform and tested remote dynamic reconfigurable technology. During the entire process, FPGA system always keeps electrifying, and has achieved the goal of remote real time updating.
引文
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[27]XILINX INC. XUP Virtex-Ⅱ Pro Development System[EB/OL]. UGO69(v1.0), March 8, 2005. http://www.xilinx.com/univ/XUPV2P/Documentation/XUPV2P_User_Guide.pdf
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[30]XILINX INC. Overview of Flash Memory Programming in XPS[EB/OL].2008. http://www.xilinx.com/itp/xilinx10/help/platform_studio/ps_c_dld_flash_ovrvw_f lash_mem_prog.htm
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[35]XILINX INC. OS and Libraries Document Collection[EB/OL]. Embedded Development Kit, EDK 10.1, January 14,2008. http://www.xilinx.com/support/documentation/application_notes.
[36]郑东,李祥学,黄征,等.密码学：密码算法与协议[M].北京：电子工业出版社,2009.
[37]DA CANNIERE C, BIRYUKOV A, PRENEEL B. An introduction to Block Cipher Cryptanalysis [J].Proceedings of the IEEE,2006,94(2):346-356.
[38]ELBIRT A J, PARR C. An instruction-level distributed processor for symmetric-key cryptography [J]. IEEE Transactions on Parallel and Distributed Systems,2005,16(5): 468-480.
[39]MCLOONE M, MCCANNY J V. High-performance FPGA implementation of DES using a novel method for implementing the key schedule [J]. IEE Proceedings Circuits, Devices & Systems,2003,150(5):373-378.
[40]郭炜,郭筝,谢憬.SoC设计方法与实现[M].北京：电子工业出版社,2008.
[2]KARTASHEV S I, KARTASHEV S P. A Multicomputer System with Software Reconfiguration of the Architecture,8th International Conference on Computer Performance, SIGMETRICS CMG VIII,1977[C]. USA:Washington D. C.,1977.
[3]KEAN T, BUCHANAN I. The Use of FPGAs in a Novel Computing Subsystem,1st International ACM Workshop on Field Programmable Gate Arrays,1992[C]. USA: Berkeley CA,1992.
[4]MCDONALD E J. Runtime FPGA partial reconfiguration [J]. IEEE Aerospace and Electronic Systems Magazine,2008,23(7):10-15.
[5]BONDALAPATI K, PRASANNA V K. Reconfigurable computing systems [J]. Proceedings of the IEEE,2002,90 (7):1201-1217.
[6]BARR, MICHAEL. A Reconfigurable Computing Primer[J]. Multimedia Systems Design, 1998,2(9):44-47.
[7]GOKHALE M. RAW keynote 1:the outer limits:reconfigurable computing in space and in orbit,20th International Conference on Parallel and Distributed Processing Symposium,2006[C]. Greece:Computer Technology Institute,2006.
[8]WILLIAMS J A, DAWOOD A S, VISSER S J. FPGA-based cloud detection for real-time onboard remote sensing, IEEE International Conference on Field-Programmable Technology,2002[C]. China:the Chinese University of Hong Kong,2002.
[9]DAWOOD A S, VISSER S J, WILLIAMS J A. Reconfigurable FPGAS for real time image processing in space,14th International Conference on Digital Signal Processing, 2002[C]. Greece:University of Patras,2002.
[10]DAWOOD A S, WILLIAMS J A, VISSER S J. On-board satellite image compression using reconfigurable FPGAs, IEEE International Conference on Field-Programmable Technology,2002[C]. China:the Chinese University of Hong Kong,2002.
[11]SALEMI B, MOLL M, WEI-MIN SHEN. SUPERBOT:A Deployable, Multi-Functional, and Modular Self-Reconfigurable Robotic System, IEEE/RSJ International Conference on Intelligent Robots and Systems,2006[C]. China:the International Convention Center of Beijing,2006.
[12]INGEBRETSEN M, DOLLARHIDE M. In the News [J]. IEEE Intelligent Systems,2007,22 (4): 8-11.
[13]WEI-MIN SHEN, SALEMI B, MOLL M, et al. Multifunctional behaviors of reconfigurable superbot robots, IEEE/RSJ International Conference on Intelligent Robots and Systems,2007[C]. USA:University of Southern California,2007.
[14]LGOR A K, LLYA I L, EVGENIY A S可重配置系统使用大型FPGA计算域[J].赛灵思中国通讯,2011,40：14-18.
[15]JOACHIM M, JUANJO N, RODNEY S, et al. Xilinx FPGA的快速启动[J].赛灵思中国通讯,2011，40：9-13.
[16]邢克飞,杨俊,王跃科,等Xilinx SRAM型FPGA抗辐射设计技术研究[J].宇航学报,2007,28(1)：123-129.
[17]XILINX INC. Architecting Systems for Upgradability with IRL (Internet Reconfigurable Logic)[EB/OL], XAPP412(vl.0), June 29,2001. http://www.xilinx.com/support/documentation/application_notes/xapp412.pdf.
[18]RAJSUMAN R. Design and test of large embedded memories:An overview [J]. IEEE Design & Test of Computers,2001,18(3):16-27.
[19]田耕,徐文波,胡彬,等Xilinx ISE Design Suite 10. x FPGA开发指南——逻辑设计篇[M].北京：人民邮电出版社,2008.
[20]何宾.可编程逻辑器件设计技术详解[M].北京：清华大学出版社,2010.
[21]田耘,徐文波Xilinx FPGA开发实用教程[M].北京：清华大学出版社,2008.
[22]谷銮,徐贵力,王友仁FPGA动态可重构理论及其研究进展[J].计算机测量与控制,2007,15(11)：1415-1418.
[23]覃祥菊,朱明程,张太鎰,等FPGA动态可重构技术原理及实现方法分析[J].电子器件,2004,27(2)：277-282.
[24]周信坚.基于可重构技术的密码分析系统模型研究[D].上海：上海交通大学,2008.
[25]PATEL P, MOALLEM M. Reconfigurable system for real-time embedded control applications [J]. IET Control Theory & Applications,2010,4(11):2506-2515.
[26]PELLIZZONI R, CACCAMO M. Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems [J].IEEE Transactions on Computers,2007,56(12): 1666-1680.
[27]XILINX INC. XUP Virtex-Ⅱ Pro Development System[EB/OL]. UGO69(v1.0), March 8, 2005. http://www.xilinx.com/univ/XUPV2P/Documentation/XUPV2P_User_Guide.pdf
[28]DALLAS SEMICONDUCTOR INC. DS2401 Silicon Serial Number[EB/OL]. DS2401 (v1.5), April 12,2011. http://datasheets.maxim-ic.com/en/ds/DS2401.pdf.
[29]XILINX INC. System ACE CompactFlash Solution[EB/OL]. DS080(v2.0), October 1,2008. http://www.xilinx.com/support/documentation/data_sheets/ds080.pdf.
[30]XILINX INC. Overview of Flash Memory Programming in XPS[EB/OL].2008. http://www.xilinx.com/itp/xilinx10/help/platform_studio/ps_c_dld_flash_ovrvw_f lash_mem_prog.htm
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[32]MOTOROLA INC. SREC(file format)[EB/OL].2011. http://en.wikipedia.org/wiki/SREC_(file_format).
[33]任泰明TCP/IP协议与网络编程[M].西安：西安电子科技大学出版社,2004.
[34]贾素玲,王强,罗昌,等.HTML网页设计[M].北京：清华大学出版社,2007.
[35]XILINX INC. OS and Libraries Document Collection[EB/OL]. Embedded Development Kit, EDK 10.1, January 14,2008. http://www.xilinx.com/support/documentation/application_notes.
[36]郑东,李祥学,黄征,等.密码学：密码算法与协议[M].北京：电子工业出版社,2009.
[37]DA CANNIERE C, BIRYUKOV A, PRENEEL B. An introduction to Block Cipher Cryptanalysis [J].Proceedings of the IEEE,2006,94(2):346-356.
[38]ELBIRT A J, PARR C. An instruction-level distributed processor for symmetric-key cryptography [J]. IEEE Transactions on Parallel and Distributed Systems,2005,16(5): 468-480.
[39]MCLOONE M, MCCANNY J V. High-performance FPGA implementation of DES using a novel method for implementing the key schedule [J]. IEE Proceedings Circuits, Devices & Systems,2003,150(5):373-378.
[40]郭炜,郭筝,谢憬.SoC设计方法与实现[M].北京：电子工业出版社,2008.