可重构计算中支持硬件透明编程的自重构技术研究
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摘要
可重构计算系统利用可编程逻辑器件可重配置的特点,在通用微处理器和专用集成电路之间提供一个结合功能灵活性和高运算速度的平台,被认为是能满足未来嵌入式应用市场需求的一种极具竞争力的技术解决方案,国内外学者对此研究十分活跃。随着可编程逻辑设计技术的发展,目前的可编程器件还支持动态部分重配置,这使得可重构计算系统在运行时可以改变自身部分功能,形成一种自重构系统。这样的系统中通常包括微处理器作为主要控制器,以及若干可重构的硬件模块作为硬件加速器,因此是一个软硬件混成系统。现有设计方法在其上进行设计时,需要设计人员了解硬件接口细节,管理硬件加速器的配置,以及软硬件之间通信,这对设计人员而言比较繁琐,也容易出错,不利于提高系统设计的效率。本文提出一个硬件透明的编程模型,屏蔽了硬件接口细节,而提供一个类似软件函数的硬件函数给设计人员,使其能简单方便地使用硬件加速器。在此基础上,本文着重研究了自重构系统的实现技术及对上述硬件透明编程模型的支持。
首先我们设计了在自重构系统中实现硬件透明模型的层次结构:最下层是自重构系统的硬件,硬件之上是对可重构的硬件加速器进行封装的硬件函数,最上层是支持硬件函数调用的嵌入式操作系统。然后设计了自重构系统的体系结构:把微处理器(固定部分)和所有硬件加速器(可变部分)看作一种共享存储器的异构多核并行处理结构,并讨论了它们之间的关系与实现方法。为了实现重构我们研究了自重构系统中连接固定部分和可变部分的总线结构以及实现方法。然后讨论了自重构系统设计流程,利用Xilinx提供的工具,给出了一个基于模块的自重构系统设计流程;并按照这个设计流程完成了一个包含硬件加速器及其硬件函数的自重构系统,通过实验验证了我们提出的基于硬件透明编程模型的自重构系统设计方法的可行性。
实验结果表明,按照本文所给出的自重构系统设计流程,可以在单片可编程器件上实现自重构系统,在运行时根据需要把不同硬件加速器配置到可编程器件上。在硬件透明编程模型上进行设计时设计人员不用了解硬件加速器的配置和接口细节,只需要在程序中调用相应硬件函数,系统将自动完成硬件加速器配置,并控制加速器完成计算任务,极大地方便了设计工作。
Reconfigurable computing using programmable hardware promises an intermediate tradeoff between flexibility and performance and becomes an impressive platform that can satisfy the requirements of embedded system applications. More recently, there has been an increasing study in the reconfigurable computing. With the development of programmable logical design technique, the programmable devices begin to support partial and dynamic reconfiguration. This provides a platform on which users can create a self-reconfigurable system that can change parts of itself at run-time. Such self-reconfigurable system generally contains microprocessor as the primary controller of the system and several reconfigurable hardware blocks as accelerators, forming a mixed software-hardware system. In the traditional method to program for such self-reconfigurable system,the programmers have to know the details of hardware accelerators, and control the configurations of hardware accelerators as well as communications between software and hardware parts. This state-of-art programming style is not efficient for system development. In this thesis, a transparent hardware-software co-design programming model is proposed. It hides the details of hardware and provides an easy-to-use interface to the programmers. How to support this transparent hardware-software co-design programming model in the self-reconfigurable system is studied.
A transparent hardware-software co-design programming model for self-reconfigurable computing system is proposed. It contains three layers: a self-reconfigurable hardware system which supports the transparent programming model, the hardware functions which encapsulate the reconfigurable hardware accelerators, as well as an embedded operating system which supports the calling of hardware functions. A self-reconfigurable architecture is proposed. The microprocessor (fixed part) and hardware accelerators (reconfigurable parts) are regarded as a shared-memory heterogeneous multi-core parallel processing structure. The relation between the different parts and the implementation of the architecture are discussed in detail. The design and implementation of the bus connecting the fixed part and reconfigurable parts of the system are studied. A self-reconfigurable system design flow using Xilinx development tools is proposed. A self-reconfigurable system that contains several hardware accelerators and the corresponding hardware functions is created based on the above design flow to validate the feasibility of the proposed transparent programming model.
The experiment shows that it is possible to implement a complex self-reconfigurable system in single FPGA chip based on the self-reconfigurable system deign flow discussed in this thesis. By adopting the transparent programming model, what programmers need to do is to call a hardware function while the system automatically reconfigures the corresponding accelerator and controls it to finish the computing task. This is helpful to increase the design efficiency of whole system.
首先我们设计了在自重构系统中实现硬件透明模型的层次结构:最下层是自重构系统的硬件,硬件之上是对可重构的硬件加速器进行封装的硬件函数,最上层是支持硬件函数调用的嵌入式操作系统。然后设计了自重构系统的体系结构:把微处理器(固定部分)和所有硬件加速器(可变部分)看作一种共享存储器的异构多核并行处理结构,并讨论了它们之间的关系与实现方法。为了实现重构我们研究了自重构系统中连接固定部分和可变部分的总线结构以及实现方法。然后讨论了自重构系统设计流程,利用Xilinx提供的工具,给出了一个基于模块的自重构系统设计流程;并按照这个设计流程完成了一个包含硬件加速器及其硬件函数的自重构系统,通过实验验证了我们提出的基于硬件透明编程模型的自重构系统设计方法的可行性。
实验结果表明,按照本文所给出的自重构系统设计流程,可以在单片可编程器件上实现自重构系统,在运行时根据需要把不同硬件加速器配置到可编程器件上。在硬件透明编程模型上进行设计时设计人员不用了解硬件加速器的配置和接口细节,只需要在程序中调用相应硬件函数,系统将自动完成硬件加速器配置,并控制加速器完成计算任务,极大地方便了设计工作。
Reconfigurable computing using programmable hardware promises an intermediate tradeoff between flexibility and performance and becomes an impressive platform that can satisfy the requirements of embedded system applications. More recently, there has been an increasing study in the reconfigurable computing. With the development of programmable logical design technique, the programmable devices begin to support partial and dynamic reconfiguration. This provides a platform on which users can create a self-reconfigurable system that can change parts of itself at run-time. Such self-reconfigurable system generally contains microprocessor as the primary controller of the system and several reconfigurable hardware blocks as accelerators, forming a mixed software-hardware system. In the traditional method to program for such self-reconfigurable system,the programmers have to know the details of hardware accelerators, and control the configurations of hardware accelerators as well as communications between software and hardware parts. This state-of-art programming style is not efficient for system development. In this thesis, a transparent hardware-software co-design programming model is proposed. It hides the details of hardware and provides an easy-to-use interface to the programmers. How to support this transparent hardware-software co-design programming model in the self-reconfigurable system is studied.
A transparent hardware-software co-design programming model for self-reconfigurable computing system is proposed. It contains three layers: a self-reconfigurable hardware system which supports the transparent programming model, the hardware functions which encapsulate the reconfigurable hardware accelerators, as well as an embedded operating system which supports the calling of hardware functions. A self-reconfigurable architecture is proposed. The microprocessor (fixed part) and hardware accelerators (reconfigurable parts) are regarded as a shared-memory heterogeneous multi-core parallel processing structure. The relation between the different parts and the implementation of the architecture are discussed in detail. The design and implementation of the bus connecting the fixed part and reconfigurable parts of the system are studied. A self-reconfigurable system design flow using Xilinx development tools is proposed. A self-reconfigurable system that contains several hardware accelerators and the corresponding hardware functions is created based on the above design flow to validate the feasibility of the proposed transparent programming model.
The experiment shows that it is possible to implement a complex self-reconfigurable system in single FPGA chip based on the self-reconfigurable system deign flow discussed in this thesis. By adopting the transparent programming model, what programmers need to do is to call a hardware function while the system automatically reconfigures the corresponding accelerator and controls it to finish the computing task. This is helpful to increase the design efficiency of whole system.
引文
[1] Todman T J, Constantinides G A, Wilton S J E, et al. Reconfigurable Computing: Architectures and Design Methods. Journal of IEE Proceedings - Computers and Digital Techniques, 2005, 152(2): 193-207
[2] Bondalapati K, Viktor K. Reconfigurable Computing Systems. Journal of IEEE Proceedings, 2002, 90(7):1201-1217
[3]. Estrin G. Reconfigurable Computer Origins: The UCLA Fixed-Plus-Variable (F+V) Structure Computer. Journal of IEEE Annals History of Computing, 2002, 24(4): 3-9
[4] 覃祥菊, 朱明程, 张太镒等. FPGA 动态可重构技术原理及实现方法分析. 电子器件, 2004, 27(2): 277-282
[5] 朱凯科. FPGA 动态可重构设计方法研究: [浙江大学硕士学位论文]. 杭州: 浙江大学信息科学与工程学院, 2006, 17-18
[6] Rafael M. A Framework for Reconfigurable Computing: Task Scheduling and Context Management. Journal of IEEE Trans on VLSI Systems, 2001, 9(6): 858-873.
[7] Moreno J M, Jordi M, Joan C, et al. Realization of Self-Repairing and Evolvable Hardware Structures by Implicit Self-Configuration. In: Proceedings of the First NASA/DoD Workshop on Evolvable Hardware. Pasadena, 1999, 182-187
[8] Andre D. DPGA-Coupled Microprocessors: Commodity Ics for the Early 21st Century. In: Proceeding of IEEE Workshop on FPGAs for Custom Computing Machine'94. Canada, 1994: 31-39
[9] 朱明程. XILINX 数字系统现场集成技术. 南京:东南大学出版社, 2001, 1-230
[10] Javier C, Pablo H, Victor L, et al. A Secure Self-Reconfiguring Architecture based on Open-Source Hardware. In: Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2005). Budapest, 2005, 10-16
[11] Andres U, Eduardo S. On-chip and On-line Self-reconfigurable Adaptable Platform: the Non-Uniform Cellular Automata Case. In: Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS06). Rhodes - Greece, IEEE Computer Society, 2006. 206-210
[12] Andreas W, Darran N. A Self-Reconfigurable Computing Platform Hardware Architecture. www.arxiv.org/PS_cache/cs, 2004-11-20.
[13] Oliver F, Bernhard S, Darran N, et al. A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio In: Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS’03). Nice, 2003,191-199
[14] Blodget B, James-Roxby P, Keller E, et al. A Self- reconfiguring Platform. In: Proceedings of 2003 International Conference on Field-Programmable Logic and Applications. Lisbon, 2003, 565-574
[15] Blodget B, Bobda C, Huebner M, et al. Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs. In: Proceeding of International conference on field-programmable logic and applications No14. Antwerp, 2004, 801-810
[16] Sedcole P, Blodget B, Becher T, et al. Modular Dynamic Reconfiguration in Virtex FPGAs. Journal of IEE Proceedings - Computers and Digital Techniques, May 2006, 153(3): 157-164.
[17] Andrews D, Niehaus D, Programming Models for Hybrid FPGA-CPU Computational Components: A missing Link. Journal of IEEE Transaction on Micro, 2004, 24(4): 42-53
[18] Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Architectures (ERSA’03). Las Vegas, 2003, 284-287
[19] Marescaux T, Nollet V, Mignolet Y, et al. Run-time Support for Heterogeneous Multitasking on Reconfigurable SOCs. Journal of Integration VLSI J, 2004, 38(1): 107-130
[20] 周博, 王石记, 邱卫东等. SHUM-UCOS 基于统一多任务模型可重构系统的实时操作系统. 计算机学报, 2006,29(2): 208-218
[21] Qingxu D, Shuisheng W, Hai X, et al. A Reconfigurable RTOS with HW/SW Co-scheduling for SOPC.In: Proceedings of the Second International Conference on Embedded Software and Systems (ICESS’05). Xi’an, 2005, 116 - 121
[22] Martyn E, Peter G. Run-time support for dynamically reconfigurable computing systems. Journal of Systems Architecture, 2003, 49(1): 267-281
[23] Miljan V, Laura P, Paolo I. Seamless Hardware-Software Integration in Reconfigurable Computing Systems. Journal of IEEE Design & Test of Computers, 2005, 22(2): 102-113.
[24] Miljan V, Laura P, and Paolo I. Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. In: Proceedings of the 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP’04). Galveston, 2004, 339-351
[25] Miljan V, Laura P, and Paolo I, et al. Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. In: Proceedings of the 12th IEEESymposium on Field-Programmable Custom Computing Machines. Napa Valley, 2004, 24-33
[26] Miljan V, Laura P, Paolo I. Virtual Memory Window for Application-Specific Reconfigurable Coprocessors. In: Proceedings of Design Automation Conference. San Diego, 2004, 948-954
[27] Miljan V, Ludovic R, Laura P, et al. Operating System Support for Interface Virtualization of Reconfigurable Coprocessors. In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition. Paris, 2004, 748-749
[28] Miljan V, Laura P, and Paolo I. Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. In: Proceedings of the 14th int’l conf. Field-Programmable Logic and Applications, LNCS3203. Springer-Verlag, 2004, 596-605.
[29] Cesario W, Baghdadi A, Gauthier L, et al. Component-Based Design Approach for Multicore SOCs. In: Proceedings of the 39th Design Automation Conference. New Orleans, 2002, 789-794
[30] Xilinx Inc. Embedded System Tools Reference Manual- Embedded Development Kit EDK 8.1i. www.xilinx.com/support, 2005-10-24
[31] Wayne W. 孙玉芳等译. 嵌入式计算系统设计原理. 北京:机械工业出版社, 2002, 255-277
[32] Xilinx Inc. Two Flows for Partial Reconfiguration: Module Based or Difference Based. www.xilinx.com/support , 2004-09-09
[33] Gregory M. A Module-Based Dynamic Partial Reconfiguration Tutorial. ic2.epfl.ch/~gmermoud, 2004-11-1
[34] 黄俊. 动态重构SOPC系统总线上IP模块的应用研究: [深圳大学硕士学位论文]. 深圳: 深圳大学信息工程学院, 2006, 26-53
[35] Jens Thorvinger. Dynamic Partial Reconfiguration of FPGA for Computational Hardware Support: [dissertation]. Copenhagen: Univ. of Lund, 2004, 40-61
[36] Nicholas Peter Sedcole. Reconfigurable Platform-Based Design in FPGAs for Video Image Processing: [dissertation], London: Univ. of London, 2006, 149-154
[37] Huebner M, Becker T, Becker J. Real-time LUT-based Network Topologies for Dynamic and Partial FPGA Self-reconfiguration. In: Proceedings of Symposium on Integrated Circuits and Systems Design. Pernambuco, 2004, 28-32
[38] Xilinx Inc. FPGA Editor Guide. www.xilinx.com/support, 2006-10
[39] Xilinx Inc. Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet. www.xilinx.com/support, 2005-10-10
[40] Xilinx Inc. Virtex-II Pro and Virtex-II Pro X FPGA User Guide. www.xilinx.com/support, 2005-03-23
[41] Xilinx Inc. Product Specification: OPB HWICAP. www.xilinx.com, 2005-04-04
[42] Xilinx Inc. PowerPC 405 Processor Block Reference Guide. www.xilinx.com/support, 2005-06-20
[43] Xilinx Inc. PowerPC Processor Reference Guide. www.xilinx.com/support, 2003-09-02, 13-23
[44] Xilinx Inc. Xilinx University Program Virtex-II Pro Development System. www.xilinx.com/support, 2005-03-08, 13-18
[45] Xilinx Inc. Development System Reference Guide. www.xilinx.com/support, 2005-03, 75-140
[46] IBM Inc. The CoreConnectTM Bus Architecture. www.chips.ibm.com/products, 2006-07
[47] Xilinx Inc. OPB IPIF Architecture. www.xilinx.com/support, 2004-08, 2-12
[2] Bondalapati K, Viktor K. Reconfigurable Computing Systems. Journal of IEEE Proceedings, 2002, 90(7):1201-1217
[3]. Estrin G. Reconfigurable Computer Origins: The UCLA Fixed-Plus-Variable (F+V) Structure Computer. Journal of IEEE Annals History of Computing, 2002, 24(4): 3-9
[4] 覃祥菊, 朱明程, 张太镒等. FPGA 动态可重构技术原理及实现方法分析. 电子器件, 2004, 27(2): 277-282
[5] 朱凯科. FPGA 动态可重构设计方法研究: [浙江大学硕士学位论文]. 杭州: 浙江大学信息科学与工程学院, 2006, 17-18
[6] Rafael M. A Framework for Reconfigurable Computing: Task Scheduling and Context Management. Journal of IEEE Trans on VLSI Systems, 2001, 9(6): 858-873.
[7] Moreno J M, Jordi M, Joan C, et al. Realization of Self-Repairing and Evolvable Hardware Structures by Implicit Self-Configuration. In: Proceedings of the First NASA/DoD Workshop on Evolvable Hardware. Pasadena, 1999, 182-187
[8] Andre D. DPGA-Coupled Microprocessors: Commodity Ics for the Early 21st Century. In: Proceeding of IEEE Workshop on FPGAs for Custom Computing Machine'94. Canada, 1994: 31-39
[9] 朱明程. XILINX 数字系统现场集成技术. 南京:东南大学出版社, 2001, 1-230
[10] Javier C, Pablo H, Victor L, et al. A Secure Self-Reconfiguring Architecture based on Open-Source Hardware. In: Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2005). Budapest, 2005, 10-16
[11] Andres U, Eduardo S. On-chip and On-line Self-reconfigurable Adaptable Platform: the Non-Uniform Cellular Automata Case. In: Proceedings of the 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS06). Rhodes - Greece, IEEE Computer Society, 2006. 206-210
[12] Andreas W, Darran N. A Self-Reconfigurable Computing Platform Hardware Architecture. www.arxiv.org/PS_cache/cs, 2004-11-20.
[13] Oliver F, Bernhard S, Darran N, et al. A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio In: Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS’03). Nice, 2003,191-199
[14] Blodget B, James-Roxby P, Keller E, et al. A Self- reconfiguring Platform. In: Proceedings of 2003 International Conference on Field-Programmable Logic and Applications. Lisbon, 2003, 565-574
[15] Blodget B, Bobda C, Huebner M, et al. Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs. In: Proceeding of International conference on field-programmable logic and applications No14. Antwerp, 2004, 801-810
[16] Sedcole P, Blodget B, Becher T, et al. Modular Dynamic Reconfiguration in Virtex FPGAs. Journal of IEE Proceedings - Computers and Digital Techniques, May 2006, 153(3): 157-164.
[17] Andrews D, Niehaus D, Programming Models for Hybrid FPGA-CPU Computational Components: A missing Link. Journal of IEEE Transaction on Micro, 2004, 24(4): 42-53
[18] Walder H, Platzner M. Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations. In: Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Architectures (ERSA’03). Las Vegas, 2003, 284-287
[19] Marescaux T, Nollet V, Mignolet Y, et al. Run-time Support for Heterogeneous Multitasking on Reconfigurable SOCs. Journal of Integration VLSI J, 2004, 38(1): 107-130
[20] 周博, 王石记, 邱卫东等. SHUM-UCOS 基于统一多任务模型可重构系统的实时操作系统. 计算机学报, 2006,29(2): 208-218
[21] Qingxu D, Shuisheng W, Hai X, et al. A Reconfigurable RTOS with HW/SW Co-scheduling for SOPC.In: Proceedings of the Second International Conference on Embedded Software and Systems (ICESS’05). Xi’an, 2005, 116 - 121
[22] Martyn E, Peter G. Run-time support for dynamically reconfigurable computing systems. Journal of Systems Architecture, 2003, 49(1): 267-281
[23] Miljan V, Laura P, Paolo I. Seamless Hardware-Software Integration in Reconfigurable Computing Systems. Journal of IEEE Design & Test of Computers, 2005, 22(2): 102-113.
[24] Miljan V, Laura P, and Paolo I. Programming Transparency and Portable Hardware Interfacing: Towards General-Purpose Reconfigurable Computing. In: Proceedings of the 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP’04). Galveston, 2004, 339-351
[25] Miljan V, Laura P, and Paolo I, et al. Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor. In: Proceedings of the 12th IEEESymposium on Field-Programmable Custom Computing Machines. Napa Valley, 2004, 24-33
[26] Miljan V, Laura P, Paolo I. Virtual Memory Window for Application-Specific Reconfigurable Coprocessors. In: Proceedings of Design Automation Conference. San Diego, 2004, 948-954
[27] Miljan V, Ludovic R, Laura P, et al. Operating System Support for Interface Virtualization of Reconfigurable Coprocessors. In: Proceedings of Design, Automation and Test in Europe Conference and Exhibition. Paris, 2004, 748-749
[28] Miljan V, Laura P, and Paolo I. Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. In: Proceedings of the 14th int’l conf. Field-Programmable Logic and Applications, LNCS3203. Springer-Verlag, 2004, 596-605.
[29] Cesario W, Baghdadi A, Gauthier L, et al. Component-Based Design Approach for Multicore SOCs. In: Proceedings of the 39th Design Automation Conference. New Orleans, 2002, 789-794
[30] Xilinx Inc. Embedded System Tools Reference Manual- Embedded Development Kit EDK 8.1i. www.xilinx.com/support, 2005-10-24
[31] Wayne W. 孙玉芳等译. 嵌入式计算系统设计原理. 北京:机械工业出版社, 2002, 255-277
[32] Xilinx Inc. Two Flows for Partial Reconfiguration: Module Based or Difference Based. www.xilinx.com/support , 2004-09-09
[33] Gregory M. A Module-Based Dynamic Partial Reconfiguration Tutorial. ic2.epfl.ch/~gmermoud, 2004-11-1
[34] 黄俊. 动态重构SOPC系统总线上IP模块的应用研究: [深圳大学硕士学位论文]. 深圳: 深圳大学信息工程学院, 2006, 26-53
[35] Jens Thorvinger. Dynamic Partial Reconfiguration of FPGA for Computational Hardware Support: [dissertation]. Copenhagen: Univ. of Lund, 2004, 40-61
[36] Nicholas Peter Sedcole. Reconfigurable Platform-Based Design in FPGAs for Video Image Processing: [dissertation], London: Univ. of London, 2006, 149-154
[37] Huebner M, Becker T, Becker J. Real-time LUT-based Network Topologies for Dynamic and Partial FPGA Self-reconfiguration. In: Proceedings of Symposium on Integrated Circuits and Systems Design. Pernambuco, 2004, 28-32
[38] Xilinx Inc. FPGA Editor Guide. www.xilinx.com/support, 2006-10
[39] Xilinx Inc. Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Complete Data Sheet. www.xilinx.com/support, 2005-10-10
[40] Xilinx Inc. Virtex-II Pro and Virtex-II Pro X FPGA User Guide. www.xilinx.com/support, 2005-03-23
[41] Xilinx Inc. Product Specification: OPB HWICAP. www.xilinx.com, 2005-04-04
[42] Xilinx Inc. PowerPC 405 Processor Block Reference Guide. www.xilinx.com/support, 2005-06-20
[43] Xilinx Inc. PowerPC Processor Reference Guide. www.xilinx.com/support, 2003-09-02, 13-23
[44] Xilinx Inc. Xilinx University Program Virtex-II Pro Development System. www.xilinx.com/support, 2005-03-08, 13-18
[45] Xilinx Inc. Development System Reference Guide. www.xilinx.com/support, 2005-03, 75-140
[46] IBM Inc. The CoreConnectTM Bus Architecture. www.chips.ibm.com/products, 2006-07
[47] Xilinx Inc. OPB IPIF Architecture. www.xilinx.com/support, 2004-08, 2-12