应用于生物芯片中的CMOS荧光检测系统的设计和研究
详细信息    本馆镜像全文|  推荐本文 |  |   获取CNKI官网全文
摘要
基于荧光的检测方法是诸多生物实验中最重要的检测技术之一。而基于Si工艺的荧光检测芯片以其低成本,低功耗,高灵敏度等优点在很多荧光检测实验中获得了广泛的关注。本文着重研究一种基于CMOS工艺的荧光检测系统芯片的设计和荧光检测实验方案的改进,论文主要包括以下几方面内容:
     在荧光检测系统设计方面,本文首先根据现有的工艺参数,建立了CMOS工艺光电二极管的光电转换模型,推导出光电转换效率的数学表达式,并且通过仿真和实际流片验证了该模型。除此,还分析比较了三种CMOS工艺兼容的光电二极管在灵敏度,峰值响应和暗电流等方面的差异,为荧光检测实验中选择适当的光电二极管提供了有利的理论基础。其次,本文提出一种新型的电容跨阻放大器(CTIA)结构读出电路来实现微弱荧光产生的光电流到电压的转换。这种结构拥有更高的光电流-电压转换增益,同时能够帮助光电二极管获得更好的暗电流特性。所提出的T型复位开关有效避免了积分期间复位开关漏电流的影响。最后,本文设计了一个12-bit,10-MS/s的流水线模数转换器(ADC)来实现检测芯片的数字化输出,为了获得较低的功耗和较小芯片面积,本文中的ADC采用了如下一些技术:通过对ADC模拟通路噪声和功耗模型的建立,确定2.5位的级分辨率;消除传统结构中的采样/保持电路;采用交换反馈电容开关(CFCS)技术来减轻级电路中采样电容的匹配要求;带有采样电容和预放大器的动态比较器;增益自举共源共栅放大器等等。本文通过SMIC 0.18-μm混合信号CMOS工艺对所设计的荧光检测芯片进行流片验证。芯片面积3 mm~2(包括PAD部分面积),消耗功耗37 mW。实验结果表明,所提出的光电转换模型与测试结果基本相符合,用于荧光检测实验的Nwell/Psub光电二极管在580 nm波长处拥有最大的光电转换灵敏度0.176 A/W。所采用的改进CTIA结构读出电路功能正确,电荷-电压转换增益为1.6μV/e~-,这种结构令Nwell/Psub光电二极管在300 mV反向偏压条件下,暗电流仅为300fA(3 nA/cm~2)。所设计的ADC的最大微分非线性(DNL)和最大积分非线性(INL)分别为+0.8 LSB和-3LSB。并且,当采样时钟为10 MHz,输入频率为1 MHz时,ADC与杂散无关的动态范围(SFDR)为61.7 dB,信号与噪声及谐波失真比(SNDR)为56.2 dB。
     在荧光实验方面,本文采用了一种“接触式”检测方法,即将荧光产生池直接放到芯片表面,从而有效避免了额外的光学仪器和光学通路带来的荧光损失。实验证明,利用所设计的CMOS荧光检测芯片配合“接触式”检测方法能够在室温下成功检测到由荧光素溶液产生的荧光。当荧光素溶液体积为2 ml时,芯片在50 ms积分时间条件下,能够检测到的最小荧光强度为3.5 nW/cm~2,最小光电流7 fA,此时荧光素溶液浓度为20 ng/ml。当荧光素溶液体积为0.5μl时,芯片在10 ms积分时间内,能够检测到浓度为625 ng/ml的荧光素溶液产生的荧光,并在光电二极管内产生约为36 fA的光电流,此时照在芯片表面的荧光强度约为18 nW/cm~2。
Fluorescence-based method is one of the most important detecting techniques in various biological experiments.The fluorescent detecting chips based on Si technology attract widely concern in lots of detecting experiments because of their low cost,low power and high sensitivity.This thesis focuses on the study and design of a CMOS fluorescent detector chip,and the improvement of the fluorescent experiment scheme.The main contributions of this thesis are concluded as following:
     On the design of the fluorescent detecting system,this thesis firstly establishes a photon-electron conversion model of the standard CMOS photodiodes based on some available technology parameters.The mathematic formulation of the conversion efficiency is also deduced and validated by simulation and testing.Furthermore,the comparisons of the three CMOS compatible photodiodes(N+/Psub photodiode,Nwell/Psub photodiode and P+/Nwell photodiode) on the sensitivity,peak response wavelength and dark current performance are given,which provide the theoretical basis for choosing proper photodectors in the detecting experiment.Secondly,a new capacitive trans-impedance amplifier(CTIA) is proposed to convert the photocurrent generated by weak fluorescence to voltage.This architecture has a higher photocurrent-voltage conversion gain and helps the photodiode have a better dark current performance.The proposed T-type reset switch avoids the leakage current influence effectively during the integrating period.Finally,a 12-bit, 10-MS/s pipelined analog-to-digital converter(ADC) is employed to realize the digitization outputs of the detecting chip.In order to achieve low power and small chip area,some special techniques have been adopted in this ADC.These techniques include the elimination of the conventional S/H circuit;the adoption of 2.5-bit/stage according to the noise model and power model in analog chain;the commutated feedback-capacitor switching(CFCS) technique to release the sampling capacitor mismatch requirement in the stage circuit; dynamic comparators with sampling capacitors and pre-amplifiers;gain boosting cascode amplifiers and so on.The proposed fluorescent detecting system is implemented in SMIC 0.18-μm standard CMOS process.This chip occupies an area of 3 mm~2(including PAD area) and consumes 37 roW.Experiments show that,the proposed photon-electron conversion model of the CMOS compatible photodiodes identifies the testing results.The Nwell/Psub photodiode used in the fluorescence detecting experiment has the maximum sensitivity of 0.176 A/W at wavelength of 580 nm.The CTIA has a charge-voltage conversion gain of 1.6μV/e~- and helps the Nwell/Psub photodiode to achieve a dark current of 300 fA(3 nA/cm~2) with 300 mV reverse biased voltage.The maximum DNL and INL of the designed ADC are +0.8 LSB and -3 LSB,respectively.A signal to noise and distortion ratio(SNDR) of 56.2 dB and a spurious free dynamic range(SFDR) of 61.7 dB are achieved at 1 MHz input frequency and 10 MHz sampling rate.
     On the testing method of the fluorescence detecting experiment,a "contact imaging" detecting method,which puts the reaction vessel onto the surface of the detecting chip directly,is adopted to avoid the fluorescence loss due to the additional optical instruments and paths.Testing results indicate that,the detector system cooperating with the "contact imaging" detecting method can detect the fluorescence generated by fluorescein solution successfully at room temperature.With a solution volume of 2 ml and an integrating time of 50 ms,the detecting chip is sensitive to the fluorescence(3.5 nW/cm~2) excited from the fluorescein solution with a concentration of 20 ng/ml,and can generate a photocurrent of 7 fA within the photodetector.While with a solution volume of 0.5μl and an integrating time of 10 ms,the detecting chip is also sensitive to the fluorescence(18 nW/cm~2) excited from the fluorescein solution with a concentration of 625 ng/ml,and generates a photocurrent of 36fA.
引文
[1]朱婷,朱大中.“用与细胞外电信号检测的CMOS集成生物传感芯片的研究”,传感器技术学报,vol.19,no.4,Aug.2006,pp.941-946.
    [2]朱婷,朱大中,施朝霞.“阵列式CMOS细胞电信号传感芯片”,固体电子学研究与进展.vol.25,no.4,Nov.2005,pp.507-512.
    [3]Lei Zhang,Xiangqing He and Zhiping Yu."Design and implementation of ultra low current sensing with pico-ampere sensitivity aiming at bio-sensor applications",Chinese Journal of Electronics,vol.16,no.2,2007,pp.247-251.
    [4]Lei Zhang,Zhiping Yu and Xiangqing He."An ultra-low current mode amplifier aiming at biosensor applications",in IEEE Proc.ASICON,Oct.2007,pp.477-480.
    [5]Lei Zhang,Zhiping Yu and Xiangqing He."Circuit design and verification of on-chip femto-ampere current mode circuit using 0.18/splmu/m CMOS technology",in IEEE Proc.ICSICT,2006,pp.1624-1626.
    [6]许金钩,王尊本.荧光分析法.北京科学出版社,2006.
    [7]林金明.化学发光基础理论与应用.北京化学工业出版社,2004
    [8]周爱玉,罗金平,岳伟伟等.“手持式ATP生物荧光检测仪研制”,传感器技术学报,vol.21,no.4,Apr.2008,pp.543-546.
    [9]余勇,胡松.“基于PMT的激光共聚焦生物芯片微弱荧光检测”,微纳电子技术,第一期,Jan.2006,pp.50-54.
    [10]沈斌,屠大维,曾爱华.“DNA芯片的CCD荧光检测”,光学仪器,vol.27,no.5,Oct.2005,pp.16-20.
    [11]David Sander,Marc Dandin,Honghao Ji et al."Low-noise CMOS fluorescence sensor",in IEEE Proc.ISCAS,2007.pp.2007.
    [12]P.Pitter,J.M.Galvan,G.N.Lu et al."CMOS LIF detection system for capillary analysis",Sensors and Actuators B,vol.97,2004,pp.355-361.
    [13]David C.Ng,Takashi Tokuda,Akio Yamamoto et al."On-chip biofluorescence imaging inside a brain tissue phantom using a CMOS image sensor for in vivo brain imaging verification",Sensors and Actuators B,vol.119,2006,pp.262-274.
    [14]Marianna Beiderman,Terence Tam,Alexander Fish et al."A low noise CMOS image sensor with an emission filter for fluorescence applications",in IEEE Proc.ISCAS,May,2008,pp.1100-1103.
    [15]Takashi Tokuda,Kunihiro Tanaka,Masamichi Matsuo et al."Optical and electrochemical dual-image CMOS sensor for on-chip biomolecular sensing applications",Sensor and Actuators A,vol.135,2007,pp.315-322.
    [16]Takashi Tokuda,Akio Yamamoto,Keiichiro Kagawa et al."A CMOS image sensor with optical and potential dual imaging function for on-chip bioscientific applications",Sensors and Actuators A,vol.125,2006,pp.273-280.
    [17]Ude Lu,Ben C.-P.Hu,Yu-Chuan Shih et al."The design of a novel complementary metal oxide semiconductor detection system for biochemical luminescence",Biosensors and Bioelectronics,vol.19,2004,pp.1185-1191.
    [18]George Patounakis,Kenneth L.Shepard and Rastislav Levicky."Active CMOS array sensor for time-resolved fluorescence detection",IEEE Journal of Solid-State Circuits,vol.41,no.11,Nov.2006,pp.2521-2530.
    [19]Takashi Tokuda,Akio Yamamoto,Keiichiro Kagawa et al."An optical and potential dual-image CMOS sensor for bioscientific applications",in IEEE Proc.Of SPIE-IS&T Electronic Imaging,vol.606802,2006,pp.1-6.
    [20]Yuki Maruyama,Kazuaki Sawada,Hidekuni Takao et al."A novel filterless fluorescence detection sensor for DNA analysis",IEEE Transactions on Electron Devices,vol.53,no.3,Mar.2006,pp.553-558.
    [21]Ventzeslav P.Iordanov,Blagoi P.Lliev,Andre Bossche et al."Integrated sensor arrays for bioluminescence and fluorescence bio-chemical analysis",in IEEE Proc.Sensors,vol.2,Oct.2004,pp.810-813.
    [22]Honghao Ji,David Sander,Alfred Haas et al."Contact imaging:simulation and experiment",IEEE Transactions on Circuits and Systems-Ⅰ:Regular papers,vol.54,no.8,Aug.2007,pp.1698-1710.
    [23]Khaled Salama,Helmy Eltoukhy,Arjang Hassibi et al."Modeling and simulation of luminescence detection platforms",Biosensors and Bioelectronics,vol.19,2004,pp.1377-1386.
    [24]Rachel A.Yotter and Denise Michelle Wilson."A review of photodetectors,for sensing light-emitting reporters in biological systems",IEEE Sensors Journal,vol.3,no.3,June,2003,pp.288-303.
    [25]Ying Huang and Richard I.Hornsey."Current-mode CMOS image sensor using lateral bipolar phototransistors",IEEE Transactions on Electron Devices,vol.50,no.12,Dec.2003,pp.2570-2573.
    [26]王为,用于生物芯片的光电传感器研究,上海:复旦大学微电子学系硕士学位论文,2007.
    [27]Ji Soo Lee,Richard I.Hornsey and David Renshaw."Analysis of CMOS photodiodes-part Ⅰ:quantum efficiency",IEEE Transactions on Electron Devices,vol.50,no.5,May,2003,pp.1233-1238.
    [28]J.Del Alamo,S.Swirhun and R.M.Swanson."Simultaneous measurement of hole lifetime,hole mobility and bandgap narrowing in heavily doped n-type silicon",IEEE International Electron Device Meeting,vol.31,1985,pp.290-293.
    [29]S.E.Swirhun,Y.-H.Kwark and R.M.Swanson."Measurement of electron lifetime,electron mobility and bandgap narrowing in heavily doped p-type silicon",IEEE International Electron Device Meeting,vol.32,1986,pp.24-27.
    [30]Muahel Tabet."Double sampling techniques for CMOS image sensors",PhD thesis,Waterloo University,2002.
    [31]Neamen D.A.半导体物理与器件.北京电子工业出版社,
    [32]Chung-Yu Wu,Yu-Chuan Shih et al."Design,optimization and performance analysis of new photodiode structures for CMOS active-pixel-sensor(APS) imager applications",IEEE Sensors Journal,vol.4,no.1,Feb.2004,pp.135-144.
    [33]M.A.Abdallah,E.Dubaric,H.E.Nilsson et al."A scintillator-coated phototransistor pixel sensor with dark current cancellation",in IEEE Proc.ICECS,Sep.2001,pp.663-667.
    [34]Hsiu-Yu Cheng and Ya-Chin King."An ultra-low dark current CMOS image sensor cell using n~+ ring reset",IEEE Electron Device Letters,vol.23,no.9,Sep.2002,pp.538-540..
    [35]Igor Shcherback,Alexander Belenky and Orly Yadid-Pecht."Empirical dark current modeling for complementary metal oxide semiconductor active pixel sensor",Society of Photo-Optical Instrumentation Engineers,vol.41,no.6,June,2002,pp.1216-1219.
    [36]Natalia V.Loukianova,Hein Otto Folkerts,Joris P.V.Maas et al."Leakage current modeling of test structures for characterization of dark current in CMOS image sensors",IEEE Transactions on Electron Devices,vol.50,no.1,Jan.2003,pp.77-83.
    [37]Michael L.Simpson,Gary S.Sayler,Greg Patterson et al."An integrated CMOS microluminometer for low-level luminescence sensing in the bioluminescent bioreporter integrated circuit",Sensors and Actuators B,vol.72,2001,pp.134-140.
    [38]Hui Tian,Boyd Fowler and Abbas El Gamal."Analysis of temporal noise in CMOS photodiode active pixel sensor",IEEE Journal of Solid-State Circuits,vol. 36,no.1,Jan.2001,pp.92-101.
    [39]Paul R.Gray,Paul J.Hurst.模拟集成电路的分析与设计.高等教育出版社,2003.
    [40]Rahul Sarpeshkar,Tobias Delbr(u|¨)ck and Carver A.Mead."White noise in MOS transistors and resistors",IEEE Circuits and Device Magazine,Nov.1993,pp.23-29.
    [41]Eric K.Bolton,Gary S.Sayler,David E.Nivens et al."Integrated CMOS photodetectors and signal processing for very low-level chemical sensing with the bioluminescent bioreporter integrated circuit",Sensors and Actuators B,vol.85,2002,pp.179-185.
    [42]Helmy Eltoukhy,Khaled Salama and Abbas El Gamal."A 0.18-μm CMOS bioluminescence detection Lab-on-Chip",IEEE Journal of Solid-State Circuits,vol.41,no.3,Mar.2006,pp.651-662.
    [43]Behzad Razavi.模拟CMOS集成电路设计.西安交通大学出版社,2003.
    [44]Abbas El Gamal,Boyd Fowler,Hao Min et al."Modeling and estimation of FPN components in CMOS image sensors",Society of Photo-Optical Instrumentation Engineers,vol.3301,1998,pp.168-177.
    [45]K.Matou,Yang Ni."Precise FPN compensation circuit for CMOS APS",Electronics Letters,vol.38,no.19,Sep.2002,pp.1078-1079.
    [46]Dileepan Joseph,Steve Collins."Modeling calibration,and correction of nonlinear illumination-dependent fixed pattern noise in logarithmic CMOS image sensors",IEEE Transactions on Instrumentation and Measurement,vol.51,no.5,Oct.2002,pp.996-1001.
    [47]Satoshi Yoshihara,Yoshikazu Nitta,Masaru Kikuchi et al."A 1/1.8-inch 6.4Mpixel 60 frames/s CMOS image sensor with seamless mode change",IEEE Journal of Solid-State Circuits,vol.41,no.12,Dec.2006,pp.2998-3006.
    [48]Yang Ni,Jianhong Guan."A 256×256 pixel smart CMOS image sensor for line-based stereo vision applications",IEEE Journal of Solid-State Circuits,vol.35,no.7,July,2000,pp.1055-1061.
    [49]Kwang-Bo Cho,Alexander I.Krymski and Eric R.Fossum."A 1.5-V 550-μW 176×144 autonomous CMOS active pixel image sensor",IEEE Transactions on Electron Devices,vol.50,no.1,Jan.2003,pp.96-105.
    [50]Naser Faramarzpour,M.Jamal Deen and Shahram Shirani."An approach to improve the signal-to-noise ratio of active pixel sensor for low-light-level applications",IEEE Transactions on Electron Devices,vol.53,no.9,Sep.2006,pp.2384-2391.
    [51]Stephen H.Lewis and Paul R.Gray."A pipelined 5-Msample/s 9-bit analog-to-digital converter',IEEE Journal of Solid-State Circuits,vol.22,no.6,Dec.1987,pp.954-961
    [52]Mitsuru Shinagawa,Yukio Akazawa and Tsutomu Wakimoto."Jitter analysis of high-speed sampling systems",IEEE Journal of Solid-State Circuits,vol.25,no.1,Feb.1990,pp.220-224.
    [53]Alan Hastings,模拟电路版图的艺术,北京清华大学出版社,2006
    [54]Stephen H.Lewis."Optimizing the stage resolution in pipelined,multistage,analog-to-digital converters for video-rate applications",IEEE Transactions on Circuits and Systems-Ⅱ:Analog and Digital Signal Process,vol.39,no.8,Aug.1992,pp.516-523.
    [55]Jo(?)o Goes,Jo(?)o C.Vital and José E.Franca,"Systematic design for optimization of high-speed self-calibrated pipelined A/D converters",IEEE Transactions on Circuits and Systems-Ⅱ:Analog and Digital Signal Processing,vol.45,no.12,Dec.1998,pp.1513-1526.
    [56]David W.Cline,Paul R.Gray."A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS",IEEE Journal of Solid-State Circuits,vol.31,no.3,Mar.1990,pp.294-303.
    [57]Jorge Guilherme,P.Figueiredo,P.Azevedo et al."Design considerations for high resolution pipeline ADCs in digital CMOS technology",in IEEE Proc.ICECS,vol.1,Sep.2001,pp.497-500.
    [58]Olujide A.Adeniran and Andreas Demosthenous."Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs",in IEEE Proc.CETAD,vol.2,Aug.2005,pp.Ⅱ/55-Ⅱ/58.
    [59]Reza Lotfi,Mohammad Taherzadeh-Sani and Omid Shoaei."Power consumption issues in high-speed high-resolution pipelined A/D converters",in IEEE Proc.ISCAS,May,2005,pp.4618-4621.
    [60]Yun Chiu,Paul R.Gray and Borivoje Nikolic."A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR",IEEE Journal of Solid-State Circuits,vol.39,no.12,Dec.2004,pp.2139-2150.
    [61]Wenhua Yang,Dan Kelly,Iuri Mehr et al."A 3-V 340-roW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at nyquist input".IEEE Journal of Solid-State Circuits,vol.36,no.12,Dec.2001,pp.1931-1936.
    [62]Paul C.Yu and Hae-Seung Lee."A 2.5-V,12-b,5-MSample/s pipelined CMOS ADC",IEEE Journal of Solid-State Circuits,vol.31,no.12,Dec.1996,pp.1854-1861.
    [63]Sang-Min Yoo,Jong-Bum Park,Seung-Hoon et al."A 2.5-V 10-b 120-MSamples/s CMOS pipelined ADC based on merged-capacitor switching",IEEE Transactions on circuits and systems-Ⅱ:Express briefs,vol.51,no.5,May,2004,pp.269-275.
    [64]Stephen H.Lewis,H.Scott Fetterman,George F.Gross et al."A 10-b 20-Msample/s Analog-to-Digital converter",IEEE Journal of Solid-State Circuits,vol.27,no.3,Mar.1992,pp.351-358.
    [65]Thomas Byunghak Cho and Paul R.Gray."A 10 b,20 Msample/s,35 mW pipeline A/D converter",IEEE Journal of Solid-State Circuits,vol.30,no.3,Mar.1995,pp.166-172.
    [66]Iuri Mehr and Larry Singer."A 55-roW,10-bit,40-Msample/s Nyquist-rate CMOS ADC",IEEE Journal of Solid-State Circuits,vol.35,no.3,Mar.2000,pp.318-325.
    [67]Dong-Young Chang."Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier",IEEE Transactions on Circuits and Systems-Ⅰ:Regular papers,vol.51,no.11,Nov.2004,pp.2123-2132.
    [68]Kush Gulati,Mark Shane Peng,Anurag Pulincherry et al."A highly integrated CMOS analog baseband transceiver with 180MSPS 13-bit pipelined CMOS ADC and dual 12-bit DACs",IEEE Journal of Solid-State Circuits,vol.41,no.8,Aug.2006,pp.1856-1865.
    [69]Jian Li,Xiaoyang Zeng,Lei Xie et al."A 1.8-V 22-mW 10-bit 30-MS/s pipelined CMOS ADC for low-power subsampling applications",IEEE Journal of Solid-State Circuits,vol.43,no.2,Feb.2008,pp.321-326.
    [70]Olujide A.Adeniran and Andreas Demosthenous."A 92 dB 560MHz 1.5V 0.35um CMOS operational transconductance amplifier",in IEEE Proc.ECCTD,vol.3,Aug.2005,pp.Ⅲ/325-Ⅲ/328.
    [71]Li Jian,Yan Jiefeng,Chen Jun et al."A 59 mW 10b 40Msample/s pipelined ADC",Chinese Journal of Semiconductors,vol.26,no.7,July,2005,pp.1301-1308.
    [72]谢磊,李建,邓焕等.“一个高性能低功耗10位30MS/s流水线A/D转换器”, 半导体学报,vol.28,no.3,Mar.2007,pp.453-459.
    [73]Yao Zhijian,Ma Chengyan,Ye Tianchun et al."Design and analysis of a gain-enhanced,fully differential telescopic operational transconductance amplifier",Chinese Journal of Semiconductors,vol.29,no.2,Feb.2008,pp.269-274.
    [74]Johns D and Martin K.Analog integrated circuit design.Toronto:John Wiley &Sons,1996.
    [75]Klaas Bult and Govert J.G.M.Geelen."A fast-settling CMOS op amp for SC circuits with 90-dB DC gain",IEEE Journal of Solid-State Circuits,vol.25,no.6,Dec.1990,pp.1379-1384.
    [76]Mrinal Das."Improved design criteria of gain-boosted CMOS OTA with high-speed optimizations",IEEE Transactions on circuits and systems-Ⅱ:analog and digital signal processing,vol.49,no.3,Mar.2002,pp.204-207.
    [77]Patheera Uthaichana and Ekachai Leelarasmec."Low power CMOS dynamic latch comparators",in IEEE Proc.TENCON,2003,pp.605-608.
    [78]Lauri Sumanen,Mikko Waltari,V(a|¨)in(o|¨) Hakkarainen et al."CMOS dynamic comparators for pipeline A/D converters",in IEEE Proc.ISCAS,May,2002,pp.157-160.
    [79]Pedro M,Figueiredo and Joao C.Vital,"Kickback noise reduction techniques for CMOS latched comparators",IEEE Transactions on Circuits and Systems-Ⅱ:Express Briefs,vol.53,no.7,July,2006,pp.541-545.
    [80]Phillip E.Alien,Douglas R.Holberg.CMOS模拟集成电路设计(第二版).电子工业出版社,2005.
    [81]Andrew M.Abo and Paul R.Gray."A 1.5-V,10-bit,14.3-MS/s CMOS pipeline Analog-to-Digital converter",IEEE Journal of Solid-State Circuits,vol.34,no.5,May,1999,pp.599-606.
    [82]Lauri Sumanen,Mikko Waltari and Kari A.I.Halonen."A 10-bit 200-MS/s CMOS parallel pipeline A/D converter",IEEE Journal of Solid-State Circuits,vol.36,no.7,July,2001,pp.1048-1055.
    [83]Ming-Huang Liu,Kuo-Chan Huang,Wei-Yang Ou et al."A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC",IEEE Journal of Solid-State Circuits,vol.39,no.5,May,2004,pp.834-837.
    [84]David William Cline."Noise,speed and power trade-offs in pipelined analog to digital converters",PhD thesis,University of California at Berkeley,1995.
    [85]Josh Carnes and Un-Ku Moon,"The effect of switch resistance on pipelined ADC MDAC settling time",in IEEE Proc.ISCAS,May,2006,pp.5251-5254.
    [86]郝允祥,陈遐举,张保洲.光度学.北京师范大学出版社,1987.

© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号

地址:北京市海淀区学院路29号 邮编:100083

电话:办公室:(+86 10)66554848;文献借阅、咨询服务、科技查新:66554700