高速精密时间间隔测量及应用研究
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摘要
时间间隔测量是信号周期、频率和相位等物理量测量的基础,连续时间间隔测量是调制域测量必需的技术手段。随着科技的飞速发展,在调制域测量中,被测信号频率不断提高,为了适应目前高频信号的测试需求,必须深入研究时间间隔测量技术,进一步提高时间间隔测量分辨率和测量速度。另外,时间间隔的高速精密测量在原子物理、天文实验、航空航天和遥测遥控等高科技领域也得到了广泛应用。时间间隔测量分辨率和速度的提高会促进许多高科技和先进工艺水平进一步提高,从而促进国民经济的发展。
本文系统综述了时间间隔测量技术的发展概况,阐述了时间间隔测量理论。针对调制域测量技术中高速、高分辨、无间隔计数等特性,以提高连续测时分辨率为目的,对连续高速同步计数问题和时间内插问题进行了深入研究。在高速同步计数器方面,分析了三种不同逻辑运算深度的计数器结构;改进了无间隔计数器的设计;提出了Systolic型非二进制同步计数器输出编码修正算法。在时间内插方面,为了减小内插保障时间提出了多斜时间内插方法,并提出了双游标、流水线式及游标时钟数字移相三种游标内插方法;针对事件信号在无源延迟单元组成的延迟链中衰减特性,提出了反馈型延迟内插方法。在高速连续测时技术应用方面,研制了VXI总线时间间隔分析模块;提出了动态相位补偿技术以提高同步串行通讯性能。本文主要的创新性研究成果如下:
1.针对级联的二进制同步计数器最大计数频率随着计数器级联位数增多而降低的问题,本文从同余理论出发,提出了模数互质的并联计数器组模型,根据中国剩余定理,推导了并联计数器组的有效计数值公式。在并联计数器组中各因子计数器独立计数,最大计数频率与位数无关。通过有效计数值公式,可将因子计数器的计数值转换为计数器组的有效计数值。为了验证模型的有效性,分别以环形计数器和中规模集成电路二进制计数器作为因子计数器,进行了仿真与实际电路实验。
2.针对高分辨延迟内插技术中延迟单元的数目多、延时短的问题,本文提出了事件与时基双延迟内插方法。该方法对事件信号和时基信号分别采用不同的延迟单元进行延迟,在满足给定的约束条件时,内插测时分辨率为两种不同延迟单元的延时差,在不增加延迟单元的情况下,提高了测时分辨率。利用Modelsim仿真软件对该方法进行了仿真验证。
3.针对目前超声波测距技术测距精度低的问题,本文以FSK调制的超声波作为发射波,采用调制域测量技术对回波瞬时频率进行测量,可对回波前沿进行精确定位,提高测距精度,并对该方法进行了实验验证。
Time interval measurement is the measurement basis of many physicalvariables such as period, frequency and phase. And continuous time intervalmeasurement is also the essentialtechnique for modulation domain measurement.With the development of science and technology, the frequency of the signalunder measurement in themodulation domain measurement raises rapidly, whichmakes the further research on the time interval measurement necessary. Theresearch aims at improving the resolution and speed of time intervalmeasurement. Moreover high-speed precise time interval measurement is widelyapplied to atomic physics, astronomy experiments, aviation and spaceflight, andremote sensing and control, so the improvement of time interval measurementcan accelerate the development in these fields and promote the development ofeconomy.
Thisdissertation systematicallysummarizes the current achievement and thefundamental theory of time interval measurement. To improve the resolution oftime interval measurement, it researches on the continuous high-speedsynchronous counter and the time interpolation technologyfor the characteristicsin modulation domain measurement, such as the high-speed and high resolution,and zero-dead-time. In the high-speed synchronous counter aspect, thedissertation analyzes the logic operation depth of three types of counters, andthen proposes the improved zero-dead-time counter design and proposes anamendment coding scheme for the non-binary Systolic counter. In the timeinterpolation aspect, a multi-slope time interpolation method to eliminate theblind measurementspot is presented, and threetypes of vernier time interpolationare also proposed, including dual-vernier interpolation, pipeline interpolation anddigital clock phase shifting interpolation. In addition, a feedback delayinterpolation is proposed according to the attenuation of the event signal in thedelay chain that is composed of passive delay units. In the application of highspeed continuous time measurement, a VXIbus time interval analyzer isdevelopped and the dynamic phase compensation is proposed to improve theperformance of the synchronous serial communication. The major innovative contributions of this dissertation are as follows:
1. The binary counters’maximum working frequency reduces as the bitsincrease. To solve the problem, a parallel synchronous counter group modelwiththe relatively prime divisors is proposed according to the reminder theory. Thereminder theory is adopted to derive the formula calculating the parallel countergroup’s counting value. The counters in the group work independently and themaximum working frequencies have no relationship with the bits. With thederived formula, the real counting value can be obtained according to thecounters’value. The formula’s validity is examined by experiments of the ringcounters and the medium-scaleintegration counters.
2. In the delay time interpolation with high resolution, the number of thedelay units is big and the delay time is short. To solve the two problems, thedissertation presents the event and time-base delay method that delay the eventsignal and the time-base through different delay units. When the restrictioncondition is fulfilled, the time interpolation resolution is the difference betweenthe two delay units’delay time and the time measurement resolution improveswithout adding additional delay units. The method is tested by Modelsimsimulation.
3. To improve the precision in the ultrasonic distance measurement, thedissertation presents a method of embedding the frequency characteristic into theecho leading edge that takes the FSK ultrasonic as transmitting wave and adoptsthe modulation domain measurement to get the real frequency of the echo. Themethod can precisely position the echo edge and improve the precision of thedistance measurement.The method is tested with experiments.
本文系统综述了时间间隔测量技术的发展概况,阐述了时间间隔测量理论。针对调制域测量技术中高速、高分辨、无间隔计数等特性,以提高连续测时分辨率为目的,对连续高速同步计数问题和时间内插问题进行了深入研究。在高速同步计数器方面,分析了三种不同逻辑运算深度的计数器结构;改进了无间隔计数器的设计;提出了Systolic型非二进制同步计数器输出编码修正算法。在时间内插方面,为了减小内插保障时间提出了多斜时间内插方法,并提出了双游标、流水线式及游标时钟数字移相三种游标内插方法;针对事件信号在无源延迟单元组成的延迟链中衰减特性,提出了反馈型延迟内插方法。在高速连续测时技术应用方面,研制了VXI总线时间间隔分析模块;提出了动态相位补偿技术以提高同步串行通讯性能。本文主要的创新性研究成果如下:
1.针对级联的二进制同步计数器最大计数频率随着计数器级联位数增多而降低的问题,本文从同余理论出发,提出了模数互质的并联计数器组模型,根据中国剩余定理,推导了并联计数器组的有效计数值公式。在并联计数器组中各因子计数器独立计数,最大计数频率与位数无关。通过有效计数值公式,可将因子计数器的计数值转换为计数器组的有效计数值。为了验证模型的有效性,分别以环形计数器和中规模集成电路二进制计数器作为因子计数器,进行了仿真与实际电路实验。
2.针对高分辨延迟内插技术中延迟单元的数目多、延时短的问题,本文提出了事件与时基双延迟内插方法。该方法对事件信号和时基信号分别采用不同的延迟单元进行延迟,在满足给定的约束条件时,内插测时分辨率为两种不同延迟单元的延时差,在不增加延迟单元的情况下,提高了测时分辨率。利用Modelsim仿真软件对该方法进行了仿真验证。
3.针对目前超声波测距技术测距精度低的问题,本文以FSK调制的超声波作为发射波,采用调制域测量技术对回波瞬时频率进行测量,可对回波前沿进行精确定位,提高测距精度,并对该方法进行了实验验证。
Time interval measurement is the measurement basis of many physicalvariables such as period, frequency and phase. And continuous time intervalmeasurement is also the essentialtechnique for modulation domain measurement.With the development of science and technology, the frequency of the signalunder measurement in themodulation domain measurement raises rapidly, whichmakes the further research on the time interval measurement necessary. Theresearch aims at improving the resolution and speed of time intervalmeasurement. Moreover high-speed precise time interval measurement is widelyapplied to atomic physics, astronomy experiments, aviation and spaceflight, andremote sensing and control, so the improvement of time interval measurementcan accelerate the development in these fields and promote the development ofeconomy.
Thisdissertation systematicallysummarizes the current achievement and thefundamental theory of time interval measurement. To improve the resolution oftime interval measurement, it researches on the continuous high-speedsynchronous counter and the time interpolation technologyfor the characteristicsin modulation domain measurement, such as the high-speed and high resolution,and zero-dead-time. In the high-speed synchronous counter aspect, thedissertation analyzes the logic operation depth of three types of counters, andthen proposes the improved zero-dead-time counter design and proposes anamendment coding scheme for the non-binary Systolic counter. In the timeinterpolation aspect, a multi-slope time interpolation method to eliminate theblind measurementspot is presented, and threetypes of vernier time interpolationare also proposed, including dual-vernier interpolation, pipeline interpolation anddigital clock phase shifting interpolation. In addition, a feedback delayinterpolation is proposed according to the attenuation of the event signal in thedelay chain that is composed of passive delay units. In the application of highspeed continuous time measurement, a VXIbus time interval analyzer isdevelopped and the dynamic phase compensation is proposed to improve theperformance of the synchronous serial communication. The major innovative contributions of this dissertation are as follows:
1. The binary counters’maximum working frequency reduces as the bitsincrease. To solve the problem, a parallel synchronous counter group modelwiththe relatively prime divisors is proposed according to the reminder theory. Thereminder theory is adopted to derive the formula calculating the parallel countergroup’s counting value. The counters in the group work independently and themaximum working frequencies have no relationship with the bits. With thederived formula, the real counting value can be obtained according to thecounters’value. The formula’s validity is examined by experiments of the ringcounters and the medium-scaleintegration counters.
2. In the delay time interpolation with high resolution, the number of thedelay units is big and the delay time is short. To solve the two problems, thedissertation presents the event and time-base delay method that delay the eventsignal and the time-base through different delay units. When the restrictioncondition is fulfilled, the time interpolation resolution is the difference betweenthe two delay units’delay time and the time measurement resolution improveswithout adding additional delay units. The method is tested by Modelsimsimulation.
3. To improve the precision in the ultrasonic distance measurement, thedissertation presents a method of embedding the frequency characteristic into theecho leading edge that takes the FSK ultrasonic as transmitting wave and adoptsthe modulation domain measurement to get the real frequency of the echo. Themethod can precisely position the echo edge and improve the precision of thedistance measurement.The method is tested with experiments.
引文
[1] 冯杰,郑树文.国际单位制(SI)基本物理量——时间及其测量方法.中山大学学报论丛. 2001,(21)1:31-34
[2] 李宗扬. 时间频率计量. 原子能出版社. 2002,9:3-16
[3] Peake, Alex. Moudulation Domain: A New Dimension in Signal Analysis.Electronic Products.1988,(30)16:35-38
[4] 黄秉英等. 时间频率的精确测量. 中国计量出版社. 1986,11:12-19
[5] 韩吉辰. 光速是怎样测量出来的.知识就是力量. 2003,9:19-20
[6] Manel Gasulla, Xiujun Li,Gerard C.M. Meijer. A High-Speed Capacitive-Sensor Interface Using a Relaxation Oscillstor and a FastCounter.Instumentation and Measurement Technology Conference.2003:811-816
[7] S. B. Kaplan. A Prescaler Circuit for a Superconductive Time- to-DigitalConverter. IEEE Transactions on Applied Super-conductivity.2001,11(1):513-516
[8] 陈千颂,杨成伟. 激光飞行时间测距关键技术进展. 激光与红外.2002,32(1):7-10
[9] K. M??tt?. A High-Precision Time-to-Digital Converter for Pulsed Time-of-Flight Laser Radar Applications. IEEE Transactions on Instrumentation andMeasurement.1998,47(2):521-536
[10] 冯萍等.集群通信网络中的高速率位同步技术.西北工业大学学报.2003,21(5):590-594
[11] 李 澄 等 . 多 气 隙 电 阻 板 室 的 时 间 特 性 研 究 . 高 能 物 理 与 核 物理.2002,26(5):455-461
[12] 梁勇飞,白立新,张一云,吴丽萍,周厚全. 基于FPGA的时间序列采集器. 核电子学与探测技术. 2006, 26(3):355-357
[13] K. Karadamoglou, N. P. Paschalidis. An 11-Bit High-Resolution andAdjustable-Range CMOS Time-To-Digital Converter for Space ScienceInstruments. IEEE Journal of Solid-State Circuits. 2004,39(1):214-222
[14] B. K. Swann. A 100-ps Time-Resolution CMOS Time-to-Digital Converterfor Positron Emission Tomography Imaging Applications. IEEE Journal ofSolid-State Circuits.2004,39(11):1839-1852
[15] 雷加,颜学龙,陈尚松.在调频通讯对抗中应用调制域分析技术.桂林电子工业学院学报.1998, (18)2:18-21
[16] 颜国军,顾宏斌.一种调制域分析仪的工程实现.仪器仪表用户.2004,(11)5:73-75
[17] 葛军.频率捷变时间间隔测量的技术研究.宇航计测技术.2000, (20)3:21-25,64
[18] 葛军.利用调制域分析仪实现频率稳定性的测量.宇航计测技术.2003,(23)5:10-14
[19] 杨文举,杨成.基于延迟内插的调制域分析.现代科学仪器.2005, 6:46-47
[20] 唐智,李景文,周荫清,王宝发.基于调制域分析的自动测试系统设计.计算机工程与设计.2007, (28)3:695-696
[21] 李国全.调制域——雷达信号分析的新方法.雷达与对抗.1993,1:61-65
[22] 李玉涛,杨成.调制域分析技术中的高精度频率测量.电子质量.2004, 11:26-27
[23] 孙圣和,刘明亮,施正豪.现代时域测量.哈尔滨工业大学出版社.1989:1-180
[24] 汤海,周渭,关鹏,王海. 特殊时间间隔测量.电子科技. 2006,2:40-43
[25] 秦云,赵德安,刘星桥. 一种短时间间隔的高精度测量方法.电测与仪表.2005,10:14-16
[26] 杨文举,杨成. 基于延迟内插的调制域分析. Modern Scientific Instruments.2005,6:46-47
[27] 安琪. 粒子物理实验中的精密时间间隔测量. 核技术. 2006,35(2):204-207
[28] 宋健,安琪,刘树彬. 基于PCI总线的高精密时间间隔测量仪的研制. 电子测量与仪器学报. 2006, 20(3):37-42
[29] 张延,黄佩诚. 高精度时间间隔测量技术与方法. 天文学进展. 2006,24(1):1-15
[30] 卜英勇, 何永强, 赵海鸣, 任凤跃. 一种高精度超声波测距仪测量精度的研究.郑州大学学报.2006,27(1):86-90
[31] Jussi-Pekka Jansson , Antti M?ntyniemi, Juha Kostamovaara. A CMOSTime-to-Digital Converter With Better Than 10 ps Single-Shot Precision .IEEE Journalof Solid-State Circuits.2006,41(6):1286-1296
[32] T. H. Kuo, H. C. Lin. Multiple-valued counter. IEEE Transactions onComputers. 1993,42(1):106-109
[33] J. R. Yuan, C. Svensson. Fast CMOS Nonbinary Divider and Counter.Electronics Letters. 1993,29(13):1222-1223
[34] O. A. Mukhanov, S. V. Rylov. Time-to-Digital Converters Based on RSFQDigital Counters. IEEE Transactions on Applied Superconductivity.1997,7(2):2669-2672
[35] J. R. Yuan. Efficient CMOS Counter Circuits. ElectronicsLetters.1988,24(21):1311-1313
[36] M. Ercegovac, T.Lang. Binary Counter with Counting Period of One HalfAdder Independent of Counter Size. IEEE Transactions on circuits andsystems. 1989,36(6):924-926
[37] J. E. Vuillemin. Constant Time Arbitrary Length Synchronous BinaryCounter. 10th IEEE Symposium on Computer Arithmetic. 1991,6: 180-183
[38] P. Larsson, J. Yuan. Novel Carry Progagation in High-Speed SynchronousCounters and Dividers.Electronics Letters.1993,29(13):1457-1458
[39] D. C. Hendry. Sequential Look-ahead Method for Digital Counters.Electronics Letters.1996,32(3):160-161
[40] Jiin-chuan Wu, Hun-Hsien Chang. A 550 MHz 9.3 mW CMOS FrequencyDivider. IEEE International Symposium on Circuits and Systems.1995,1:199-202
[41] Hun-Hsien Chang, Jiin-chuan Wu. A 723-MHz 17.2-Mw CMOSProgrammable Counter. IEEE Journal of Solid-state Circuits.1998,33(10):1572-1575
[42] B. Chang, J. Park, W. Kim. A 1.2GHz CMOS Dual-Modulus Prescaler UsingNew Dynamic D-Type Flip-Flops. IEEE Journal of Solid-stateCircuits.1996,31(5):749-752
[43] J. Craninckx. A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescalerin 0.7-um COMS.IEEE Journal of Solid-state Circuits.1996,31(7):890-897
[44] M. R. Stan, M. D. Ercegovac. Long and Fast Up/Down Counters. IEEETransactions on Computers. 1998,47(7):722-735
[45] Sang-Hoon Lee, Hong-June Park. A CMOS High-Speed Wide-RangeProgrammable Counter. IEEE Transactions on circuits and systems.2002,49(9): 638-642
[46] A. P Kakarountas. A Novel High-Speed Counter with Counting RateIndependent of the Counter’s Length. Proceedings of the 2003 10th IEEEInternational Conference on Electronics, Circuits and Systems.2003,3:1164-1167
[47] R. Ahmed, D. Perreault. High Speed Low Connectivity (HDLC) Counters.Proceedings of the 35th Midwest Symposium on Circuits and Systems.1992,8(1):433- 436
[48] K. Z. Pekmestzi, N. Thanasouras. Systolic Frequency Dividers/Counters.IEEE Transactions on circuits and systems. 1994,41(11): 775-776
[49] 王礼平,王观凤. 超前进位加法器的延迟时间公式与优化设计. 武汉理工大学学报. 2004,4:585-588
[50] 王礼平,王观凤. 超前进位加法器混合模块延迟公式及优化序列. 微电子学与计算机. 2005,1:152-155
[51] 杭国强,吴训威. 一种单锁存器CMOS三值D型边沿触发器设计. 电子学报.2002,5:760-762
[52] 陈学雄.同步计数器快速进位链的设计方法.台州学院学报.2003, (25)6:40-42
[53] C. W. Sobczynski, B. W. Haynes. 25 ps resolution, 12-bit, 64 channelFASTBUS time-to-digital converter. IEEE Transactions on NuclearScience.Volume.1989,36(1):426- 430
[54] E. J. Gerds, J. V. Spiegel. A CMOS Time to Digital Converter IC with 2Level Analog CAM. IEEE Journal of Solid-State Circuits. 1994,29(9):1068-1076
[55] R. R. Elvi, T. Rahkonen. A Bi-CMOS Time-To-Digital Converter with 30 psResolution. Proceedings of the 1999 IEEE International Symposium onCircuits and Systems.1999,1:278–281
[56] J. Kostamovaara, K. MZW, T. Rahkonen, R. Rankinen. ECL and CMOSASICS for Time-to-Digital Conversion. IEEE ASIC Seminar and Exhibit.1989,9:5-2-1- 5-2-4
[57] M. Koskinen, J. Kostamovaara. An Averaging Mode Time-to-AmplitudeConverter with Picosecond Resolution. IEEE Transactions onInstrumentation and Measurement. 1993, 42(4): 866-870
[58] 刘波,王文双. 基于AD644的内插电路的设计. 电子质量. 2005,10:4-5,15
[59] Ming-Jun Hsiao, Jing-Reng Huang. A Low-Cost CMOS Time IntervalMeasurement Core. The 2001 IEEE International Symposium on Circuits andSystems. 2001,4:190 –193
[60] I. Cosimo. A Fast, Programmable, Multichannel Pulse Delay Generator.Measurement.1999, 26(1):55-67
[61] M. A. Thompson, Mark W. Werner. Free Running Time to Digital Converterwith 1 Nanosecond Resolution. IEEE Transactions on Nuclear Science.1988,35(1):184-186
[62] T. Rahkonen. J. Kostarnovaara. A CMOS ASIC Time-to-Digital Converterfor Short Time Interval Measurements. IEEE International Symposium onCircuits and Systems.1989, 3(5): 2092-2095
[63] S. Kleinfelder, T. J. Majors. MTD 132 - A New Sub-Nanosecond Multi-hitCMOS Time-to-Digital Converter. IEEE Transactions on Nuclear Science.1991,38(2): 97-105
[64] K. Sakamoto, J. McDonald, M. Swapp, B. Weir. A Digitally ProgrammableDelay Chip with Picosecond Resolution. Bipolar Circuits and TechnologyMeeting. 1989,9:295 –297
[65] Y. Arai, T. Qhsugi. TMC-A CMOS Time to Digital Converter VLSI. IEEETransactions on Nuclear Science. 1989,36(1):528-531
[66] A. Black, E. Ozbay. Colliding Pulse Phase Detector for PicosecondResolution Timing Measurement. Electronics Letters. 1991,27(18): 1620-1622
[67] J. G. Maneatis, M. A. Horowitz. Precise Delay Generation Using CoupledOscillators IEEE Journal of Solid-State Circuits. 1993,28(12): 1273-1282
[68] C. Ljuslin, J. Christiansen. An Integrated 16-channel CMOS Time to DigitalConverter. IEEE Transactionson Nuclear Science.1994,41(4):1104-1108
[69] R.Szplet, J. Kalisz,R. Szymanowski.Interpolating Time Counter with 100 psResolution on a Single FPGADevice. IEEE Transactions on Instrumentationand Measurement.2000,49(4):879-883
[70] R. Pelka, J. Kalisz, R. Szplet. Nonlinearity Correction of the IntegratedTime-to-Digital Converter with Direct Coding. IEEE Transactions onInstrumentation and Measurement.1997,46(2):449-453
[71] D. M. Santos, J. M. Flasck. A CMOS Delay Locked Loop and Sub-Nanosecond Time-To-Digital Converter Chip. IEEE Transactions on NuclearScience. 1996,43(3):1717-1719
[72] M. Mota, J. Christiansen.AFour Channel, Self-Calibrating, High Resolution,Time to Digital Converter. Electronics. IEEE International Conference onCircuits and Systems.1998,1(9):409-412
[73] A. Mantyniemi, T.Rahkonen, J. Kostamovaara. A High Resolution DigitalCMOS Time-To-Digital Converter Based On Nested Delay Locked Loops.Proceedings of the 1999 IEEE International Symposium on Circuits andSystems. 1999,2:537-540
[74] F. Baronti, L. Fanucci. On the Differential Nonlinearity of Time-to-DigitalConverters Based on Delay-Locked-Loop Delay Lines.IEEE Transactions onNuclear Science.2001,48(6):2424-2432
[75] R. Pelka, J. Kalisz, R. Szplet. Nonlinearity Correction of the IntegratedTime-to-Digital Converter with Direct Coding. IEEE Transactions onInstrumentation and Measurement.1997,46(2):P449-453
[76] A. Boujrada, D. Bloyet, M. Tripon. A Digital TDC with a Reduced Numberof Delay Line Cells. Nuclear Instruments and Methods in Physics Research.2002:803–812
[77] J. Kalisz, R. Szplet. Field-Programmable-Gate-Array-Based Time-to-DigitalConverter with 200-ps Resolution. IEEE Transactions on Instrumentationand Measurement.1997,46(1):51-55
[78] P. Andreani, F. Bigongiari. Multihit multichannel time-to-digital converterwith ±1% differential nonlinearity and near optimal time resolution. IEEEJournal Of Solid-State Circuits. 1998,33(4):650-656
[79] M. Mota, J. Christiansen. A Flexible Multi-Channel High-Resolution Time-to-Digital Converter ASIC. IEEE Nuclear Science Symposium ConferenceRecord.2000,2:9/155-9/159
[80] C. S. Hwang, P. Chen, H. W. Tsao. A High-Resolution and Fast-ConversionTime-To-Digital Converter. Proceedings of the 2003 InternationalSymposium onCircuits and Systems.2003,1:I-37-I-40
[81] 朱恒宝. 游标法时间间隔测定器. 华东船舶工业学院学报. 1997,11(2):90-97
[82] 陈堂敏. 游标式测时法的探讨. 化工自动化及仪表. 1998,25(3):56-57
[83] 陈堂敏,丁广壁. 一种游标式测频的新方法. 仪表技术. 1999,3:32-34
[84] M.S. Andaloussi, M. Boukadoum1.ANovel Time-To-Digital Converter with150 ps Time Resolution and 2.5 ns Pulse-Pair Resolution. The 14thInternational Conference on Microelectronics.2002:123 –126
[85] 刘莉,李署坚,邵定蓉. 一种基于FPGA用游标法实现的时间间隔测定器.遥测遥控. 2005,5:63-67
[86] G. C.Moyer, M.Clements, W. Liu. Precise Delay Generation Using theVernierTechnique.Electronics Letters.1996, 32(18): 1658-1659
[87] P. Dudek, J. V. Hatfield. A High-Resolution CMOS Time-to-DigitalConverter Utilizing a Vernier Delay Line. IEEE Transactions on Solid-StateCircuits.2000,35(2):240-247
[88] A.H. Chan,G.W. Roberts.A deep sub-micron timing measurement circuitusing a single-stage Vernier delay line. IEEE Custom Integrated CircuitsConference.2002:77–80
[89] G. C. Moyer, M. Clements, W. Liu. The Delay Vernier Pattern GenerationTechnique.IEEE Journal of Solid-State Circuits.1997,32(4):551-562
[90] A. H. Chan, G. W. Roberts. A Synthesizable, Fast and High-ResolutionTiming Measurement Device Using a Component-Invariant Vernier DelayLine.International Proceedings of Test Conference. 2001:858–867
[91] T. E. Rahkonen, J. T. Kostamovaara. The Use of Stabilized CMOS DelayLines for the Digitization of Short Time Intervals. IEEE Journal of Solid-State Circuits. 1993,28(8):887-894
[92] R. R. Elvi, T. Rahkonen, J.Kostamovaara. A Low-Power CMOS Time-to-Digital Converter. IEEE Journal of Solid-State Circuits. 1995,30(9):984-990
[93] P. Chen, S. I. Liu. A Low Power High Accuracy CMOS Time-To-DigitalConverter. 1997 IEEE International Symposium on Circuits and Systems.1997:281-284
[94] Poki Chen, Shen-Iuan Liu, Jingshown Wu. Highly Accurate Cyclic CMOSTime-to-Digital Converter with Extremely Low Power Consumption.Electronics Letters. 1997,33(10):858-860
[95] Chorng-Sii Hwang,Poki Chen,Hen-Wai Tsao.A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme. IEEETransactions on Nuclear Science. 2004,51(4):1349-1352
[96] Chun-Chi Chen, Poki Chen,Wei Chang.A Precise Cyclic CMOS Time-to-Digital Converter With Low Thermal Sensitivity. IEEE Transactions onNuclear Science.2005,52(4):834-838
[97] Poki Chen, Chun-Chi Chen,Chin-Chung Tsai,Wen-Fu LU.A Time-to-Digital-Converter-Based on Smart Temprature Sensor. IEEE Journal of Solid-StateCircuits. 2005,40(8):1642-1648
[98] 周渭,王海. 时频测控技术的发展. 时间频率学报. 2003,2:87-95
[99] 于建国,陈明,周渭,刘海霞. 精密时间间隔测量方法的改进. 宇航计测技术.2003,3:15-20
[100] 江玉洁,陈辰,周渭.新型频率测量方法的研究. 仪器仪表学报. 2004,1:30-33,60
[101] 辛明,冯清贤. 提高时间参量量化精度的方法. 电子信息对抗技术.2006,5:22-24
[102] Jian Song, Qi An,Shubin Liu.A High-Resolution Time-to-DigitalImplemented in Field-Programmable-Gate-Arrays. IEEE Transactions onNuclear Science.2006,53(1):236-241
[103] V. Lagareste, F. Badets, D. Belot, Y. Deval, J.B. Begueret, P. Melchior. ANew PLL Architecture: theComposite PLL.2005. 48th Midwest Symposiumon Circuits and Systems. 2005,1:511-514
[104] Adem Aktas, Mohammed Ismail. CMOS PLL Calibration Techniques. IEEECircuits and Devices Magazine.Sept.-Oct. 2004:6-11
[105] Thomas Olsson, Peter Nilsson. A Digitally Controlled PLL for SoCApplications. IEEE Journal of Solid-State Circuits. 2004, 39(5):751-760
[106] D. Chu. Phase Digitizing Sharpens Timing Measurements. IEEE SpectrumMagazine.1998,25(7):28-32
[107] 张顺燕.数学的源与流. 高等教育出版社. 2000:215-266
[108] 余莉,王润生,韩方剑.多分辨率形态学目标检测.计算机辅助设计与图形学学报.2006,18(6):849-853
[109] Seung-Jun Bae,Hyung-Joon Chi,Young-Soo Sohn,Park, H.-J.A VCDL-based60-760-MHz Dual-loop DLL with Infinite Phase-shift Capability andAdaptive-bandwidth Scheme. IEEE Journal of Solid-State Circuits. 2005,40(5):1119- 1129
[110] Ching-Che Chung,Chen-Yi Lee.A New DLL-based Approach for All-digitalMultiphase Clock Generation. IEEE Journal of Solid-State Circuits. 2004,39(3):469-475
[111] J.-H. Kim, Y.-H. Kwak, M. Kim, S.-W. Kim, C. Kim. A 120-MHz–1.8-GHzCMOS DLL-Based Clock Generator for Dynamic Frequency Scaling. IEEEJournal of Solid-State Circuits.2006,41(9):2077-2082
[112] Ramin Farjad-Rad,William Dally, Ng Hiok-Tiaq, Ramesh Senthinathan, M.-J Edward Lee, Rohit Rathi, John Poulton. A low-power Multiplying DLL forLow-jitter Multigigahertz Clock Generation in Highly Integrated DigitalChips. IEEE Journal of Solid-State Circuits. 2002,37(12):1804-1812
[113] Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang. A Low-power Small-area/spl plusmn/7.28-ps-jitter 1-GHz DLL-based Clock Generator. IEEE Journalof Solid-State Circuits. 2002,37(11):1414-1420
[114] H.-H. Chang,C.-H. Sun, and S.-I. Liu.A low-jitter and Precise MultiphaseDelay Locked Loop Using Shifted Averaging VCDL. ISSCC Digest ofTechnical Papers. 2003:434–504.
[115] Mouurad Oulmane,Gorddon W. Roberts. CMOS Digital Time Amplifiers forHigh Resolution Timing Measurement. Analog Integrated Circuits andSignal Processing. 2005,43: 269-280
[116] Hsiang-Hui Chang, Chih-Hao Sun, Shen-Iuan Liu. A Low-jitter and PreciseMultiphase Delay-locked Loop Using Shifted Averaging VCDL. Solid-StateCircuits Conference. 2003, 1:434-505
[117] M. Mota,J. Christiansen.A High-Resolution Time Interpolator Based on aDelay Locked Loop and an RC Delay Line. IEEE Journal of Solid-StateCircuits.1999, 34(10):1360-1366
[118] J. Kalisz.Determination of Short-Term Error Caused by the Reference Clockin Precision Time-Interval Measurement and Generation. IEEE Transactionson Instrumentation and Measurement. 1988,37(2):315-316
[119] S. Bregni. Measurement of Maximum Time Interval Error forTelecommunications Clock Stability Characterization. IEEE Transactions onInstrumentation and Measurement.1996,45(5):900-906
[120] Yuriy S. Shmaliy. An Unbiased FIR Filer for TIE Model of a Local Clock inApplications to GPS-Based Timekeeping. IEEE Transactions on Ultrasonics,Freroelectri,and FrequencyControl.2006,53(5):862-870
[121] Antonio H. Chan, Gordon W. Roberts.A Jitter Characterization SystemUsing a Component-Invariant Vernier Delay Line. IEEE Transactions onVeryLarge Scale Integration(VLSI)Systems.2004.12.(1):79-95
[122] H. Hartmann, E. Steiner. Synchronization Techniques for Digital Networks.IEEE Journal on Selected Areas in Communications.1986,4(4):506-513
[123] 马红梅,韩立中,王公森. 数字通信信号漂移测量方法研究. 宇航计测技术.2005,25(5):14-17
[124] K. Sasaki, M. Nishihira, K. Imano. Ultra-high Distance Resolution UsingPhase Information of 40 KHz Air-coupled Ultrasonic. Electronics Letters.2006,42(14):858-860
[125] M. McCarthy, P. Duff, H.L. Muller, Cliff Randell. Accessible UltrasonicPositioning. IEEE Pervasive Computing.2006,5(4):86-93
[126] 刘永富,朱昌平,林善明,朱佳,张红苹. 基于复杂可编程逻辑器件的气介超声测距系统的设计. 声学技术. 2006,25(4):317-320
[127] 李飞,陈峰. 基于BP神经网络的超声测距误差补偿. 传感器与微系统.2006,25(6):31- 33
[2] 李宗扬. 时间频率计量. 原子能出版社. 2002,9:3-16
[3] Peake, Alex. Moudulation Domain: A New Dimension in Signal Analysis.Electronic Products.1988,(30)16:35-38
[4] 黄秉英等. 时间频率的精确测量. 中国计量出版社. 1986,11:12-19
[5] 韩吉辰. 光速是怎样测量出来的.知识就是力量. 2003,9:19-20
[6] Manel Gasulla, Xiujun Li,Gerard C.M. Meijer. A High-Speed Capacitive-Sensor Interface Using a Relaxation Oscillstor and a FastCounter.Instumentation and Measurement Technology Conference.2003:811-816
[7] S. B. Kaplan. A Prescaler Circuit for a Superconductive Time- to-DigitalConverter. IEEE Transactions on Applied Super-conductivity.2001,11(1):513-516
[8] 陈千颂,杨成伟. 激光飞行时间测距关键技术进展. 激光与红外.2002,32(1):7-10
[9] K. M??tt?. A High-Precision Time-to-Digital Converter for Pulsed Time-of-Flight Laser Radar Applications. IEEE Transactions on Instrumentation andMeasurement.1998,47(2):521-536
[10] 冯萍等.集群通信网络中的高速率位同步技术.西北工业大学学报.2003,21(5):590-594
[11] 李 澄 等 . 多 气 隙 电 阻 板 室 的 时 间 特 性 研 究 . 高 能 物 理 与 核 物理.2002,26(5):455-461
[12] 梁勇飞,白立新,张一云,吴丽萍,周厚全. 基于FPGA的时间序列采集器. 核电子学与探测技术. 2006, 26(3):355-357
[13] K. Karadamoglou, N. P. Paschalidis. An 11-Bit High-Resolution andAdjustable-Range CMOS Time-To-Digital Converter for Space ScienceInstruments. IEEE Journal of Solid-State Circuits. 2004,39(1):214-222
[14] B. K. Swann. A 100-ps Time-Resolution CMOS Time-to-Digital Converterfor Positron Emission Tomography Imaging Applications. IEEE Journal ofSolid-State Circuits.2004,39(11):1839-1852
[15] 雷加,颜学龙,陈尚松.在调频通讯对抗中应用调制域分析技术.桂林电子工业学院学报.1998, (18)2:18-21
[16] 颜国军,顾宏斌.一种调制域分析仪的工程实现.仪器仪表用户.2004,(11)5:73-75
[17] 葛军.频率捷变时间间隔测量的技术研究.宇航计测技术.2000, (20)3:21-25,64
[18] 葛军.利用调制域分析仪实现频率稳定性的测量.宇航计测技术.2003,(23)5:10-14
[19] 杨文举,杨成.基于延迟内插的调制域分析.现代科学仪器.2005, 6:46-47
[20] 唐智,李景文,周荫清,王宝发.基于调制域分析的自动测试系统设计.计算机工程与设计.2007, (28)3:695-696
[21] 李国全.调制域——雷达信号分析的新方法.雷达与对抗.1993,1:61-65
[22] 李玉涛,杨成.调制域分析技术中的高精度频率测量.电子质量.2004, 11:26-27
[23] 孙圣和,刘明亮,施正豪.现代时域测量.哈尔滨工业大学出版社.1989:1-180
[24] 汤海,周渭,关鹏,王海. 特殊时间间隔测量.电子科技. 2006,2:40-43
[25] 秦云,赵德安,刘星桥. 一种短时间间隔的高精度测量方法.电测与仪表.2005,10:14-16
[26] 杨文举,杨成. 基于延迟内插的调制域分析. Modern Scientific Instruments.2005,6:46-47
[27] 安琪. 粒子物理实验中的精密时间间隔测量. 核技术. 2006,35(2):204-207
[28] 宋健,安琪,刘树彬. 基于PCI总线的高精密时间间隔测量仪的研制. 电子测量与仪器学报. 2006, 20(3):37-42
[29] 张延,黄佩诚. 高精度时间间隔测量技术与方法. 天文学进展. 2006,24(1):1-15
[30] 卜英勇, 何永强, 赵海鸣, 任凤跃. 一种高精度超声波测距仪测量精度的研究.郑州大学学报.2006,27(1):86-90
[31] Jussi-Pekka Jansson , Antti M?ntyniemi, Juha Kostamovaara. A CMOSTime-to-Digital Converter With Better Than 10 ps Single-Shot Precision .IEEE Journalof Solid-State Circuits.2006,41(6):1286-1296
[32] T. H. Kuo, H. C. Lin. Multiple-valued counter. IEEE Transactions onComputers. 1993,42(1):106-109
[33] J. R. Yuan, C. Svensson. Fast CMOS Nonbinary Divider and Counter.Electronics Letters. 1993,29(13):1222-1223
[34] O. A. Mukhanov, S. V. Rylov. Time-to-Digital Converters Based on RSFQDigital Counters. IEEE Transactions on Applied Superconductivity.1997,7(2):2669-2672
[35] J. R. Yuan. Efficient CMOS Counter Circuits. ElectronicsLetters.1988,24(21):1311-1313
[36] M. Ercegovac, T.Lang. Binary Counter with Counting Period of One HalfAdder Independent of Counter Size. IEEE Transactions on circuits andsystems. 1989,36(6):924-926
[37] J. E. Vuillemin. Constant Time Arbitrary Length Synchronous BinaryCounter. 10th IEEE Symposium on Computer Arithmetic. 1991,6: 180-183
[38] P. Larsson, J. Yuan. Novel Carry Progagation in High-Speed SynchronousCounters and Dividers.Electronics Letters.1993,29(13):1457-1458
[39] D. C. Hendry. Sequential Look-ahead Method for Digital Counters.Electronics Letters.1996,32(3):160-161
[40] Jiin-chuan Wu, Hun-Hsien Chang. A 550 MHz 9.3 mW CMOS FrequencyDivider. IEEE International Symposium on Circuits and Systems.1995,1:199-202
[41] Hun-Hsien Chang, Jiin-chuan Wu. A 723-MHz 17.2-Mw CMOSProgrammable Counter. IEEE Journal of Solid-state Circuits.1998,33(10):1572-1575
[42] B. Chang, J. Park, W. Kim. A 1.2GHz CMOS Dual-Modulus Prescaler UsingNew Dynamic D-Type Flip-Flops. IEEE Journal of Solid-stateCircuits.1996,31(5):749-752
[43] J. Craninckx. A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescalerin 0.7-um COMS.IEEE Journal of Solid-state Circuits.1996,31(7):890-897
[44] M. R. Stan, M. D. Ercegovac. Long and Fast Up/Down Counters. IEEETransactions on Computers. 1998,47(7):722-735
[45] Sang-Hoon Lee, Hong-June Park. A CMOS High-Speed Wide-RangeProgrammable Counter. IEEE Transactions on circuits and systems.2002,49(9): 638-642
[46] A. P Kakarountas. A Novel High-Speed Counter with Counting RateIndependent of the Counter’s Length. Proceedings of the 2003 10th IEEEInternational Conference on Electronics, Circuits and Systems.2003,3:1164-1167
[47] R. Ahmed, D. Perreault. High Speed Low Connectivity (HDLC) Counters.Proceedings of the 35th Midwest Symposium on Circuits and Systems.1992,8(1):433- 436
[48] K. Z. Pekmestzi, N. Thanasouras. Systolic Frequency Dividers/Counters.IEEE Transactions on circuits and systems. 1994,41(11): 775-776
[49] 王礼平,王观凤. 超前进位加法器的延迟时间公式与优化设计. 武汉理工大学学报. 2004,4:585-588
[50] 王礼平,王观凤. 超前进位加法器混合模块延迟公式及优化序列. 微电子学与计算机. 2005,1:152-155
[51] 杭国强,吴训威. 一种单锁存器CMOS三值D型边沿触发器设计. 电子学报.2002,5:760-762
[52] 陈学雄.同步计数器快速进位链的设计方法.台州学院学报.2003, (25)6:40-42
[53] C. W. Sobczynski, B. W. Haynes. 25 ps resolution, 12-bit, 64 channelFASTBUS time-to-digital converter. IEEE Transactions on NuclearScience.Volume.1989,36(1):426- 430
[54] E. J. Gerds, J. V. Spiegel. A CMOS Time to Digital Converter IC with 2Level Analog CAM. IEEE Journal of Solid-State Circuits. 1994,29(9):1068-1076
[55] R. R. Elvi, T. Rahkonen. A Bi-CMOS Time-To-Digital Converter with 30 psResolution. Proceedings of the 1999 IEEE International Symposium onCircuits and Systems.1999,1:278–281
[56] J. Kostamovaara, K. MZW, T. Rahkonen, R. Rankinen. ECL and CMOSASICS for Time-to-Digital Conversion. IEEE ASIC Seminar and Exhibit.1989,9:5-2-1- 5-2-4
[57] M. Koskinen, J. Kostamovaara. An Averaging Mode Time-to-AmplitudeConverter with Picosecond Resolution. IEEE Transactions onInstrumentation and Measurement. 1993, 42(4): 866-870
[58] 刘波,王文双. 基于AD644的内插电路的设计. 电子质量. 2005,10:4-5,15
[59] Ming-Jun Hsiao, Jing-Reng Huang. A Low-Cost CMOS Time IntervalMeasurement Core. The 2001 IEEE International Symposium on Circuits andSystems. 2001,4:190 –193
[60] I. Cosimo. A Fast, Programmable, Multichannel Pulse Delay Generator.Measurement.1999, 26(1):55-67
[61] M. A. Thompson, Mark W. Werner. Free Running Time to Digital Converterwith 1 Nanosecond Resolution. IEEE Transactions on Nuclear Science.1988,35(1):184-186
[62] T. Rahkonen. J. Kostarnovaara. A CMOS ASIC Time-to-Digital Converterfor Short Time Interval Measurements. IEEE International Symposium onCircuits and Systems.1989, 3(5): 2092-2095
[63] S. Kleinfelder, T. J. Majors. MTD 132 - A New Sub-Nanosecond Multi-hitCMOS Time-to-Digital Converter. IEEE Transactions on Nuclear Science.1991,38(2): 97-105
[64] K. Sakamoto, J. McDonald, M. Swapp, B. Weir. A Digitally ProgrammableDelay Chip with Picosecond Resolution. Bipolar Circuits and TechnologyMeeting. 1989,9:295 –297
[65] Y. Arai, T. Qhsugi. TMC-A CMOS Time to Digital Converter VLSI. IEEETransactions on Nuclear Science. 1989,36(1):528-531
[66] A. Black, E. Ozbay. Colliding Pulse Phase Detector for PicosecondResolution Timing Measurement. Electronics Letters. 1991,27(18): 1620-1622
[67] J. G. Maneatis, M. A. Horowitz. Precise Delay Generation Using CoupledOscillators IEEE Journal of Solid-State Circuits. 1993,28(12): 1273-1282
[68] C. Ljuslin, J. Christiansen. An Integrated 16-channel CMOS Time to DigitalConverter. IEEE Transactionson Nuclear Science.1994,41(4):1104-1108
[69] R.Szplet, J. Kalisz,R. Szymanowski.Interpolating Time Counter with 100 psResolution on a Single FPGADevice. IEEE Transactions on Instrumentationand Measurement.2000,49(4):879-883
[70] R. Pelka, J. Kalisz, R. Szplet. Nonlinearity Correction of the IntegratedTime-to-Digital Converter with Direct Coding. IEEE Transactions onInstrumentation and Measurement.1997,46(2):449-453
[71] D. M. Santos, J. M. Flasck. A CMOS Delay Locked Loop and Sub-Nanosecond Time-To-Digital Converter Chip. IEEE Transactions on NuclearScience. 1996,43(3):1717-1719
[72] M. Mota, J. Christiansen.AFour Channel, Self-Calibrating, High Resolution,Time to Digital Converter. Electronics. IEEE International Conference onCircuits and Systems.1998,1(9):409-412
[73] A. Mantyniemi, T.Rahkonen, J. Kostamovaara. A High Resolution DigitalCMOS Time-To-Digital Converter Based On Nested Delay Locked Loops.Proceedings of the 1999 IEEE International Symposium on Circuits andSystems. 1999,2:537-540
[74] F. Baronti, L. Fanucci. On the Differential Nonlinearity of Time-to-DigitalConverters Based on Delay-Locked-Loop Delay Lines.IEEE Transactions onNuclear Science.2001,48(6):2424-2432
[75] R. Pelka, J. Kalisz, R. Szplet. Nonlinearity Correction of the IntegratedTime-to-Digital Converter with Direct Coding. IEEE Transactions onInstrumentation and Measurement.1997,46(2):P449-453
[76] A. Boujrada, D. Bloyet, M. Tripon. A Digital TDC with a Reduced Numberof Delay Line Cells. Nuclear Instruments and Methods in Physics Research.2002:803–812
[77] J. Kalisz, R. Szplet. Field-Programmable-Gate-Array-Based Time-to-DigitalConverter with 200-ps Resolution. IEEE Transactions on Instrumentationand Measurement.1997,46(1):51-55
[78] P. Andreani, F. Bigongiari. Multihit multichannel time-to-digital converterwith ±1% differential nonlinearity and near optimal time resolution. IEEEJournal Of Solid-State Circuits. 1998,33(4):650-656
[79] M. Mota, J. Christiansen. A Flexible Multi-Channel High-Resolution Time-to-Digital Converter ASIC. IEEE Nuclear Science Symposium ConferenceRecord.2000,2:9/155-9/159
[80] C. S. Hwang, P. Chen, H. W. Tsao. A High-Resolution and Fast-ConversionTime-To-Digital Converter. Proceedings of the 2003 InternationalSymposium onCircuits and Systems.2003,1:I-37-I-40
[81] 朱恒宝. 游标法时间间隔测定器. 华东船舶工业学院学报. 1997,11(2):90-97
[82] 陈堂敏. 游标式测时法的探讨. 化工自动化及仪表. 1998,25(3):56-57
[83] 陈堂敏,丁广壁. 一种游标式测频的新方法. 仪表技术. 1999,3:32-34
[84] M.S. Andaloussi, M. Boukadoum1.ANovel Time-To-Digital Converter with150 ps Time Resolution and 2.5 ns Pulse-Pair Resolution. The 14thInternational Conference on Microelectronics.2002:123 –126
[85] 刘莉,李署坚,邵定蓉. 一种基于FPGA用游标法实现的时间间隔测定器.遥测遥控. 2005,5:63-67
[86] G. C.Moyer, M.Clements, W. Liu. Precise Delay Generation Using theVernierTechnique.Electronics Letters.1996, 32(18): 1658-1659
[87] P. Dudek, J. V. Hatfield. A High-Resolution CMOS Time-to-DigitalConverter Utilizing a Vernier Delay Line. IEEE Transactions on Solid-StateCircuits.2000,35(2):240-247
[88] A.H. Chan,G.W. Roberts.A deep sub-micron timing measurement circuitusing a single-stage Vernier delay line. IEEE Custom Integrated CircuitsConference.2002:77–80
[89] G. C. Moyer, M. Clements, W. Liu. The Delay Vernier Pattern GenerationTechnique.IEEE Journal of Solid-State Circuits.1997,32(4):551-562
[90] A. H. Chan, G. W. Roberts. A Synthesizable, Fast and High-ResolutionTiming Measurement Device Using a Component-Invariant Vernier DelayLine.International Proceedings of Test Conference. 2001:858–867
[91] T. E. Rahkonen, J. T. Kostamovaara. The Use of Stabilized CMOS DelayLines for the Digitization of Short Time Intervals. IEEE Journal of Solid-State Circuits. 1993,28(8):887-894
[92] R. R. Elvi, T. Rahkonen, J.Kostamovaara. A Low-Power CMOS Time-to-Digital Converter. IEEE Journal of Solid-State Circuits. 1995,30(9):984-990
[93] P. Chen, S. I. Liu. A Low Power High Accuracy CMOS Time-To-DigitalConverter. 1997 IEEE International Symposium on Circuits and Systems.1997:281-284
[94] Poki Chen, Shen-Iuan Liu, Jingshown Wu. Highly Accurate Cyclic CMOSTime-to-Digital Converter with Extremely Low Power Consumption.Electronics Letters. 1997,33(10):858-860
[95] Chorng-Sii Hwang,Poki Chen,Hen-Wai Tsao.A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme. IEEETransactions on Nuclear Science. 2004,51(4):1349-1352
[96] Chun-Chi Chen, Poki Chen,Wei Chang.A Precise Cyclic CMOS Time-to-Digital Converter With Low Thermal Sensitivity. IEEE Transactions onNuclear Science.2005,52(4):834-838
[97] Poki Chen, Chun-Chi Chen,Chin-Chung Tsai,Wen-Fu LU.A Time-to-Digital-Converter-Based on Smart Temprature Sensor. IEEE Journal of Solid-StateCircuits. 2005,40(8):1642-1648
[98] 周渭,王海. 时频测控技术的发展. 时间频率学报. 2003,2:87-95
[99] 于建国,陈明,周渭,刘海霞. 精密时间间隔测量方法的改进. 宇航计测技术.2003,3:15-20
[100] 江玉洁,陈辰,周渭.新型频率测量方法的研究. 仪器仪表学报. 2004,1:30-33,60
[101] 辛明,冯清贤. 提高时间参量量化精度的方法. 电子信息对抗技术.2006,5:22-24
[102] Jian Song, Qi An,Shubin Liu.A High-Resolution Time-to-DigitalImplemented in Field-Programmable-Gate-Arrays. IEEE Transactions onNuclear Science.2006,53(1):236-241
[103] V. Lagareste, F. Badets, D. Belot, Y. Deval, J.B. Begueret, P. Melchior. ANew PLL Architecture: theComposite PLL.2005. 48th Midwest Symposiumon Circuits and Systems. 2005,1:511-514
[104] Adem Aktas, Mohammed Ismail. CMOS PLL Calibration Techniques. IEEECircuits and Devices Magazine.Sept.-Oct. 2004:6-11
[105] Thomas Olsson, Peter Nilsson. A Digitally Controlled PLL for SoCApplications. IEEE Journal of Solid-State Circuits. 2004, 39(5):751-760
[106] D. Chu. Phase Digitizing Sharpens Timing Measurements. IEEE SpectrumMagazine.1998,25(7):28-32
[107] 张顺燕.数学的源与流. 高等教育出版社. 2000:215-266
[108] 余莉,王润生,韩方剑.多分辨率形态学目标检测.计算机辅助设计与图形学学报.2006,18(6):849-853
[109] Seung-Jun Bae,Hyung-Joon Chi,Young-Soo Sohn,Park, H.-J.A VCDL-based60-760-MHz Dual-loop DLL with Infinite Phase-shift Capability andAdaptive-bandwidth Scheme. IEEE Journal of Solid-State Circuits. 2005,40(5):1119- 1129
[110] Ching-Che Chung,Chen-Yi Lee.A New DLL-based Approach for All-digitalMultiphase Clock Generation. IEEE Journal of Solid-State Circuits. 2004,39(3):469-475
[111] J.-H. Kim, Y.-H. Kwak, M. Kim, S.-W. Kim, C. Kim. A 120-MHz–1.8-GHzCMOS DLL-Based Clock Generator for Dynamic Frequency Scaling. IEEEJournal of Solid-State Circuits.2006,41(9):2077-2082
[112] Ramin Farjad-Rad,William Dally, Ng Hiok-Tiaq, Ramesh Senthinathan, M.-J Edward Lee, Rohit Rathi, John Poulton. A low-power Multiplying DLL forLow-jitter Multigigahertz Clock Generation in Highly Integrated DigitalChips. IEEE Journal of Solid-State Circuits. 2002,37(12):1804-1812
[113] Chulwoo Kim, In-Chul Hwang, Sung-Mo Kang. A Low-power Small-area/spl plusmn/7.28-ps-jitter 1-GHz DLL-based Clock Generator. IEEE Journalof Solid-State Circuits. 2002,37(11):1414-1420
[114] H.-H. Chang,C.-H. Sun, and S.-I. Liu.A low-jitter and Precise MultiphaseDelay Locked Loop Using Shifted Averaging VCDL. ISSCC Digest ofTechnical Papers. 2003:434–504.
[115] Mouurad Oulmane,Gorddon W. Roberts. CMOS Digital Time Amplifiers forHigh Resolution Timing Measurement. Analog Integrated Circuits andSignal Processing. 2005,43: 269-280
[116] Hsiang-Hui Chang, Chih-Hao Sun, Shen-Iuan Liu. A Low-jitter and PreciseMultiphase Delay-locked Loop Using Shifted Averaging VCDL. Solid-StateCircuits Conference. 2003, 1:434-505
[117] M. Mota,J. Christiansen.A High-Resolution Time Interpolator Based on aDelay Locked Loop and an RC Delay Line. IEEE Journal of Solid-StateCircuits.1999, 34(10):1360-1366
[118] J. Kalisz.Determination of Short-Term Error Caused by the Reference Clockin Precision Time-Interval Measurement and Generation. IEEE Transactionson Instrumentation and Measurement. 1988,37(2):315-316
[119] S. Bregni. Measurement of Maximum Time Interval Error forTelecommunications Clock Stability Characterization. IEEE Transactions onInstrumentation and Measurement.1996,45(5):900-906
[120] Yuriy S. Shmaliy. An Unbiased FIR Filer for TIE Model of a Local Clock inApplications to GPS-Based Timekeeping. IEEE Transactions on Ultrasonics,Freroelectri,and FrequencyControl.2006,53(5):862-870
[121] Antonio H. Chan, Gordon W. Roberts.A Jitter Characterization SystemUsing a Component-Invariant Vernier Delay Line. IEEE Transactions onVeryLarge Scale Integration(VLSI)Systems.2004.12.(1):79-95
[122] H. Hartmann, E. Steiner. Synchronization Techniques for Digital Networks.IEEE Journal on Selected Areas in Communications.1986,4(4):506-513
[123] 马红梅,韩立中,王公森. 数字通信信号漂移测量方法研究. 宇航计测技术.2005,25(5):14-17
[124] K. Sasaki, M. Nishihira, K. Imano. Ultra-high Distance Resolution UsingPhase Information of 40 KHz Air-coupled Ultrasonic. Electronics Letters.2006,42(14):858-860
[125] M. McCarthy, P. Duff, H.L. Muller, Cliff Randell. Accessible UltrasonicPositioning. IEEE Pervasive Computing.2006,5(4):86-93
[126] 刘永富,朱昌平,林善明,朱佳,张红苹. 基于复杂可编程逻辑器件的气介超声测距系统的设计. 声学技术. 2006,25(4):317-320
[127] 李飞,陈峰. 基于BP神经网络的超声测距误差补偿. 传感器与微系统.2006,25(6):31- 33