静态随机存取存储器IP核全定制设计与实现
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摘要
随着基于IP核复用的SOC设计方法发展,对于可重用IP核的需求越来越大。静态随机存取存储器SRAM以其低功耗的特点已成为微处理器和众多电子产品最常用的存储类部件。而编译器实现的SRAM已经不能满足设计需求,需要采用全定制的方法设计高速低功耗的SRAM存储器。全定制设计开销大,要求所设计的全定制模块具有一定的可配置性和可重用性,从而节省设计代价。因此,研究和设计具有可配置性的SRAM IP核具有重要的应用价值和实践意义。
本文采用全定制设计方法,在0.18μm CMOS工艺下设计实现了一款16Kb的SRAM IP核,完成了从逻辑设计、版图设计、内建自测试设计到投片验证以及最终IP化的完整设计流程。该SRAM实现了本文所提出的一种可配置译码结构,不需要改变整个硬核设计,就能实现64位和128位两种位宽的数据读写。这种可配置输入输出数据位宽的设计思想对于编译器的设计具有很好的指导作用。此外,本文还研究了一种具有低功耗特点,基于H树结构的编译器容量扩展方法,并优化设计了一种电流模式的敏感放大器,它的功耗仅为普通Latch结构功耗的77%。
在典型条件下,本文所设计的SRAM写入延迟小于1.35ns,读出延迟小于1.54ns,在500MHz频率下,平均功耗为35.053mW,与同等工艺下编译器生成的SRAM相比,访问时间减小了10%,平均功耗减小了20%。
With the development of SOC design method based on IP core,the need of reconfigurable IP core increases.Because SRAM comes up low power characteristic, Static Random Access Memory is the most common and important memory component in CPU and other electronic products.At present,SRAM complier can generate different capacity SRAM conveniently and quickly,but its performance can't reach high-speed and low-power goal in high performance microprocessor.So,it is significant to design a low power and high speed SRAM by full custom design method.For reducing design cost,the designed circuit module with reconfigurable characteristic is necessary.
The proposed 16Kb SRAM IP core with reconfigurable input and output data bitwidth is implemented in 0.18μm CMOS process.The structure design,circuit design, layout design,BIST design and IP modeling of IP core are finished,at the same time, the SRAM after taping out is verified.This SRAM with proposed reconfigurable decoder structure can input and output 64 bits and 128 bits data width without changing the design.The design idea guide SRAM complier design.Besides,this paper researches on low power design method of SRAM complier which is based on H-tree structure and optimizes a kind of current mode amplifier,its power consumption is only 77%of Latch structure amplifier's.
In typical case that the work power supply is 1.8v,the delay of writing data in SRAM is less than 1.35ns and the delay of reading data is less than 1.54ns,Under the condition of 500MHZ clock frequency,the average power consumption is 35.053mw. Comparing to the SRAM generated by the memory compiler in the same process,the designed SRAM's average power consumption reduces by 20%,and the access time reduces by 10%.
本文采用全定制设计方法,在0.18μm CMOS工艺下设计实现了一款16Kb的SRAM IP核,完成了从逻辑设计、版图设计、内建自测试设计到投片验证以及最终IP化的完整设计流程。该SRAM实现了本文所提出的一种可配置译码结构,不需要改变整个硬核设计,就能实现64位和128位两种位宽的数据读写。这种可配置输入输出数据位宽的设计思想对于编译器的设计具有很好的指导作用。此外,本文还研究了一种具有低功耗特点,基于H树结构的编译器容量扩展方法,并优化设计了一种电流模式的敏感放大器,它的功耗仅为普通Latch结构功耗的77%。
在典型条件下,本文所设计的SRAM写入延迟小于1.35ns,读出延迟小于1.54ns,在500MHz频率下,平均功耗为35.053mW,与同等工艺下编译器生成的SRAM相比,访问时间减小了10%,平均功耗减小了20%。
With the development of SOC design method based on IP core,the need of reconfigurable IP core increases.Because SRAM comes up low power characteristic, Static Random Access Memory is the most common and important memory component in CPU and other electronic products.At present,SRAM complier can generate different capacity SRAM conveniently and quickly,but its performance can't reach high-speed and low-power goal in high performance microprocessor.So,it is significant to design a low power and high speed SRAM by full custom design method.For reducing design cost,the designed circuit module with reconfigurable characteristic is necessary.
The proposed 16Kb SRAM IP core with reconfigurable input and output data bitwidth is implemented in 0.18μm CMOS process.The structure design,circuit design, layout design,BIST design and IP modeling of IP core are finished,at the same time, the SRAM after taping out is verified.This SRAM with proposed reconfigurable decoder structure can input and output 64 bits and 128 bits data width without changing the design.The design idea guide SRAM complier design.Besides,this paper researches on low power design method of SRAM complier which is based on H-tree structure and optimizes a kind of current mode amplifier,its power consumption is only 77%of Latch structure amplifier's.
In typical case that the work power supply is 1.8v,the delay of writing data in SRAM is less than 1.35ns and the delay of reading data is less than 1.54ns,Under the condition of 500MHZ clock frequency,the average power consumption is 35.053mw. Comparing to the SRAM generated by the memory compiler in the same process,the designed SRAM's average power consumption reduces by 20%,and the access time reduces by 10%.
引文
[1]Michael Keating,Pierre Bricaud.Reuse Methodology Manual for System-on-a-Chip Designs.Third Edition,Publishing House of Electronics Industry,2004.5.
[2]孟庆.SOC设计中IP核的测试方法与应用.浙江大学硕士学位论文,2004.
[3]贾智.SRAM技术与市场.计算机元器件,2000.2.
[4]SRAM发展面临挑战.http://www.chinaecnet.com/index_hqzs.asp?cat=22.
[5]我国存储器市场发展九大趋势.http://www.chinaecnet.com/index_hqzs.asp?cat=21.
[6]Jason Stinson,Stefan Rusu.A 1.5GHz Third Generation Itanium(?)Processor.Intel Comoration,Santa Clara,CA.
[7]Kannan Srinivasagam.SRAM的应用和技术发展趋势.http://www.cypress.com
[8]任艳颖,王彬.IC设计基础.西安电子科技大学出版社,2003.
[9]Richard C Jaeger.Microelectrionic Circuit Design.The McGraw Hill Companies,Inc,1997.
[10]D.Frohman.FAMOS A New Semicoductor Charge Stroge Device.Solid State Communications,Vol 5,1967,pp 813-815
[11]E.Snow,Fowler Nordheim.Tunneling in SiO_2 Films.Solid State Communicatioms,Vol 6,1967,pp813-815
[12]R.Pashley and S Lai.Flash memories:The Best of Two Worlds.IEEE Spectrum,December 1989,pp 30-33
[13]Michael L.Bushnell and Vishwani D.Agrawal.Essenials of elecrtonic tesing for digital memory and mixed-signal VLSI circuits.KLUWER ACADEMIC PUBLISHERS,2000.
[14]T.P.Haraszti.CMOS MEMORY CIRCUIT.Kluwer academic publishers,1999
[15]徐福培,蔡士杰.计算机组成与结构.电子工业出版社,2002.
[16]Jan M.Rabaey,Anantha Chandrakasan,Borivoje Nikolic.Digital Integrated Circuits.PRENTICE HALL ELECTRONICS AND VLSI SERIES,2003.
[17]H.Kato,et al.Consideration of poly-si loaded cell Capacity Limits for Low Power and High-Speed SRAMs.IEEE Journal of Solid State Circuits,Apt 1992,pp683-685.
[18]曾树荣.半导体器件物理基础.北京大学出版社,2002.2
[19]B.Chappel et al.Stability and SER Analysis of Static RAM cells.IEEE Journal of Solid State Circuit,Feb 1985,pp383-399.
[20]J.H.Friedrich.A coincident-select MOS storage Array.IEEE Journal of Solid State Circuits,Sep 1968,pp280-285
[21]Y.Tarui.et al.A 40ns 144bit n-channel MOS LSI Memory.IEEE Journal of Solid-State Circuits,Oct 1969,pp271-279
[22]R.M.Jacmen.et al.HMOS Ⅱ Static RAMs overtake bipolar competition Ⅰ.Electronics,Vol 52,Sep 1979,pp124-128
[23]Travis N.Blalock,Richard C.Jaeger.A High-Speed Clamped Bit-Line Cun'ent Mode Sense Amplifier.IEEE Journal of Solid-State circuits,Vol 26,No 4,April 1991.
[24]Tim Dao,Frank J.Sevjda.A dual-port SRAM compiler for 0.8μm 100K BiCMOS gate arrays.IEEE 1991 CUSTOM INTEGRATED CIRCUITS CONFERENCE
[25]K.Itoh et al.Trends in Low Power RAM Circuit Technologies.Proceedings of the IEEE,pp524-543,April 1995.
[26]Martin Margala.Low-Power SRAM Circuit Design.IEEE int.Workshop on Memory Technology,design and Testing.1999.
[27]Stephen T.Flannagan,Perry H.Pelley et.al.8-ns CMOS 64k×4 and 256K×1 SRAM's.IEEE JOURNAL OF SOLID-STATE CIRCUITS,vol.25,NO.5,OCTOBER 1990
[28]S.Kawashima et.al.A Charge-Transfer Amplifier and an Encoded-Bus Architecture for Low-Power SRAM's.IEEE Journal of Solid-State Circuits,vol.33,no.5,pp.793-799,May 1998.
[29]I.Fukushi et,al.A Low-Power SRAM Using Improved Charge Transfer Sense Amplifiers and a Dual-Vth CMOS Circuit Scheme.in Digest of Technical Papers of Symposium on VLSI Circuits,pp.142-143,June 1998.
[30]K.Nii et.al.A Low Power SRAM using Auto-Backgate- Controlled MT-CMOS.in proceedings onf ISLPED,pp.293-298,August 1998.
[31]M.Margala and N.G.Durdle.Noncomplementary BiCMOS logic and CMOS logic styles for low-voltage operation - A Comprehensive Study.IEEE J.Solid-State Circuits,vol.33,no.10,pp.1580-1585,October 1998.
[32]Subhasis Bhattacharjee,Dhiraj K.Pradhan.LPRAM:A Novel Low Power RAM Design with Testability.IEEE Transaction on CAD 2004
[33]P.M.Carter and B.R.Wilkins.Influences on soft Error Rates in Static RAMs.IEEE J Solid State Circuits,vol SC-22(3),019430-436,June.1987.
[34]贺朝会,李国政,罗晋生,刘恩科.CMOS SRAM单粒子翻转效应的解析分析.半导体学报,pp174-178.2000.21(2).
[35]S.E.Kerns,and B.D.Shafer.The Design of Radiation-Hardened Ics for Space:A Compendium of Approaches Proceedings of the IEEE,Vo 1.76(11),pp.1470-1508,November,1988.
[36]Robert Wong,Tao Peng,Greg Landry.Design and modeling of tapered LWL architecture for high density SRAM.Cypress Semiconductors NEDC,NH,USA03063
[37]I.E.Sutherland,R.F.Sproull,D.Harris.Logical Effort:Designing Fast CMOS Circuits.Morgan Kaufmann Publisher,San Francisco,1999.
[38]H.Q.Dao,V.G.Oklobdzija.Application of Logical Effort Techniques for Speed Optimization and Analysis of Representative Adders.35th Annual Asilomar Conference on Signals,Systems and Computers,2001.
[39]D.Harris,I.Sutherland.Logical effort of carry propagate adders.Proc.37th Asilomar Conf.Signals,Systems,and Computers,pp.673-678,2003.
[40]Frank Kagan Gurkaynak.ARIES:An LSI Macro-Block for DSP Applications.http://dewww.epfl.ch/～kgf/msc
[41]方粮等.一种高速SRAM单元的设计.第九届计算机工程与工艺全国学术年会论文集
[42]Toumazou.C.,Lidgey,FJ.J.and Haigh D.G.Analogue IC design:The current-mode approach.Peter Peregrinus Ltd.,London,UK,April 1990.
[43]L.C.Sood,J.S.Golab,J.Salter,J.E.Leiss and J.J.Bames.A Fast 8K×8 CMOS SRAM with Internal Power Down Design Techniques.IEEE.J.Solid-State Circuits,vol.SC-20(5),pp941-950,October.1985.
[44]Evert Seevinck,Petrus J.van Beers,and Hans Ontrop.Current-Mode Techniques for High-speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's.IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.26,NO.4,APRIL 1991.
[45]P.E.艾伦、D.R.霍尔伯格著,王正华、叶小琳译.CMOS模拟电路设计.科学出版社,1995.
[46]蔡懿慈、周强编著.超大规模集成电路设计导论.清华大学出版社,2005.1.
[47]Jan M.Rabaey.Digital Integrated Circuits.清华大学出版社,Prentice-Hall International,Inc,Dec,1998
[48]李振涛,陈书明.预防闩锁效应的CMOS版图设计技术.国防科技大学首届研究生学术活动周论文集.长沙:国防科技大学出版社,2001年10月.
[49]Michael L.Bushnell,Vishwani D.Agrawal著,蒋安平,冯建华,王新安译.超大规模集成电路测试-数字、存储器和混合信号系统.北京:电子工业出版社2005.8
[50]A.J.van de Goor.Testing Semiconductor Memories:Theory and Practice.Chichester,UK:John Wiley&Sons,Inc.,1991.
[51]A.J van de Goor,Yervant Zorian.Effective March Algorithms for Testing Single-Order Addressed Memories.Vol 5,no.4 Nov.1994 pp337-345.
[52]R.Dekker,F.Beenker,A.Thijssen.Fault Modeling and Test Algorithm Development for Static Random Access Memories.IEEE International Test Conference,Sep 1988.
[53]A.J.Van De Goor and I.B.S.Tlili.March Tests for Word-Oriented Memories.Proc.Design.Automation and Test in Europe Conference and Exhibition,1998,pp501-508.
[54]Wei-Lun Wang,Kuen-Jong Lee.A Programmable Data Background Generator for March Based Memory Testing.Asic,2002,IEEE,Asia-Pacific Conference
[55]W.W.Peterson and E.J.Weldon,Jr..Error-Correcting Codes.New York:John Wiley & Sons,Inc.,1972
[56]张建民.面向SoC的USB控制器及通用IO控制器的IP核设计与实现.国防科大硕士学位论文,2003
[57]李婉萍.Design and Implementation of a High-Performance Memory Generator国立中山大学资讯工程学系硕士学位论文,2004.7
[2]孟庆.SOC设计中IP核的测试方法与应用.浙江大学硕士学位论文,2004.
[3]贾智.SRAM技术与市场.计算机元器件,2000.2.
[4]SRAM发展面临挑战.http://www.chinaecnet.com/index_hqzs.asp?cat=22.
[5]我国存储器市场发展九大趋势.http://www.chinaecnet.com/index_hqzs.asp?cat=21.
[6]Jason Stinson,Stefan Rusu.A 1.5GHz Third Generation Itanium(?)Processor.Intel Comoration,Santa Clara,CA.
[7]Kannan Srinivasagam.SRAM的应用和技术发展趋势.http://www.cypress.com
[8]任艳颖,王彬.IC设计基础.西安电子科技大学出版社,2003.
[9]Richard C Jaeger.Microelectrionic Circuit Design.The McGraw Hill Companies,Inc,1997.
[10]D.Frohman.FAMOS A New Semicoductor Charge Stroge Device.Solid State Communications,Vol 5,1967,pp 813-815
[11]E.Snow,Fowler Nordheim.Tunneling in SiO_2 Films.Solid State Communicatioms,Vol 6,1967,pp813-815
[12]R.Pashley and S Lai.Flash memories:The Best of Two Worlds.IEEE Spectrum,December 1989,pp 30-33
[13]Michael L.Bushnell and Vishwani D.Agrawal.Essenials of elecrtonic tesing for digital memory and mixed-signal VLSI circuits.KLUWER ACADEMIC PUBLISHERS,2000.
[14]T.P.Haraszti.CMOS MEMORY CIRCUIT.Kluwer academic publishers,1999
[15]徐福培,蔡士杰.计算机组成与结构.电子工业出版社,2002.
[16]Jan M.Rabaey,Anantha Chandrakasan,Borivoje Nikolic.Digital Integrated Circuits.PRENTICE HALL ELECTRONICS AND VLSI SERIES,2003.
[17]H.Kato,et al.Consideration of poly-si loaded cell Capacity Limits for Low Power and High-Speed SRAMs.IEEE Journal of Solid State Circuits,Apt 1992,pp683-685.
[18]曾树荣.半导体器件物理基础.北京大学出版社,2002.2
[19]B.Chappel et al.Stability and SER Analysis of Static RAM cells.IEEE Journal of Solid State Circuit,Feb 1985,pp383-399.
[20]J.H.Friedrich.A coincident-select MOS storage Array.IEEE Journal of Solid State Circuits,Sep 1968,pp280-285
[21]Y.Tarui.et al.A 40ns 144bit n-channel MOS LSI Memory.IEEE Journal of Solid-State Circuits,Oct 1969,pp271-279
[22]R.M.Jacmen.et al.HMOS Ⅱ Static RAMs overtake bipolar competition Ⅰ.Electronics,Vol 52,Sep 1979,pp124-128
[23]Travis N.Blalock,Richard C.Jaeger.A High-Speed Clamped Bit-Line Cun'ent Mode Sense Amplifier.IEEE Journal of Solid-State circuits,Vol 26,No 4,April 1991.
[24]Tim Dao,Frank J.Sevjda.A dual-port SRAM compiler for 0.8μm 100K BiCMOS gate arrays.IEEE 1991 CUSTOM INTEGRATED CIRCUITS CONFERENCE
[25]K.Itoh et al.Trends in Low Power RAM Circuit Technologies.Proceedings of the IEEE,pp524-543,April 1995.
[26]Martin Margala.Low-Power SRAM Circuit Design.IEEE int.Workshop on Memory Technology,design and Testing.1999.
[27]Stephen T.Flannagan,Perry H.Pelley et.al.8-ns CMOS 64k×4 and 256K×1 SRAM's.IEEE JOURNAL OF SOLID-STATE CIRCUITS,vol.25,NO.5,OCTOBER 1990
[28]S.Kawashima et.al.A Charge-Transfer Amplifier and an Encoded-Bus Architecture for Low-Power SRAM's.IEEE Journal of Solid-State Circuits,vol.33,no.5,pp.793-799,May 1998.
[29]I.Fukushi et,al.A Low-Power SRAM Using Improved Charge Transfer Sense Amplifiers and a Dual-Vth CMOS Circuit Scheme.in Digest of Technical Papers of Symposium on VLSI Circuits,pp.142-143,June 1998.
[30]K.Nii et.al.A Low Power SRAM using Auto-Backgate- Controlled MT-CMOS.in proceedings onf ISLPED,pp.293-298,August 1998.
[31]M.Margala and N.G.Durdle.Noncomplementary BiCMOS logic and CMOS logic styles for low-voltage operation - A Comprehensive Study.IEEE J.Solid-State Circuits,vol.33,no.10,pp.1580-1585,October 1998.
[32]Subhasis Bhattacharjee,Dhiraj K.Pradhan.LPRAM:A Novel Low Power RAM Design with Testability.IEEE Transaction on CAD 2004
[33]P.M.Carter and B.R.Wilkins.Influences on soft Error Rates in Static RAMs.IEEE J Solid State Circuits,vol SC-22(3),019430-436,June.1987.
[34]贺朝会,李国政,罗晋生,刘恩科.CMOS SRAM单粒子翻转效应的解析分析.半导体学报,pp174-178.2000.21(2).
[35]S.E.Kerns,and B.D.Shafer.The Design of Radiation-Hardened Ics for Space:A Compendium of Approaches Proceedings of the IEEE,Vo 1.76(11),pp.1470-1508,November,1988.
[36]Robert Wong,Tao Peng,Greg Landry.Design and modeling of tapered LWL architecture for high density SRAM.Cypress Semiconductors NEDC,NH,USA03063
[37]I.E.Sutherland,R.F.Sproull,D.Harris.Logical Effort:Designing Fast CMOS Circuits.Morgan Kaufmann Publisher,San Francisco,1999.
[38]H.Q.Dao,V.G.Oklobdzija.Application of Logical Effort Techniques for Speed Optimization and Analysis of Representative Adders.35th Annual Asilomar Conference on Signals,Systems and Computers,2001.
[39]D.Harris,I.Sutherland.Logical effort of carry propagate adders.Proc.37th Asilomar Conf.Signals,Systems,and Computers,pp.673-678,2003.
[40]Frank Kagan Gurkaynak.ARIES:An LSI Macro-Block for DSP Applications.http://dewww.epfl.ch/～kgf/msc
[41]方粮等.一种高速SRAM单元的设计.第九届计算机工程与工艺全国学术年会论文集
[42]Toumazou.C.,Lidgey,FJ.J.and Haigh D.G.Analogue IC design:The current-mode approach.Peter Peregrinus Ltd.,London,UK,April 1990.
[43]L.C.Sood,J.S.Golab,J.Salter,J.E.Leiss and J.J.Bames.A Fast 8K×8 CMOS SRAM with Internal Power Down Design Techniques.IEEE.J.Solid-State Circuits,vol.SC-20(5),pp941-950,October.1985.
[44]Evert Seevinck,Petrus J.van Beers,and Hans Ontrop.Current-Mode Techniques for High-speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM's.IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL.26,NO.4,APRIL 1991.
[45]P.E.艾伦、D.R.霍尔伯格著,王正华、叶小琳译.CMOS模拟电路设计.科学出版社,1995.
[46]蔡懿慈、周强编著.超大规模集成电路设计导论.清华大学出版社,2005.1.
[47]Jan M.Rabaey.Digital Integrated Circuits.清华大学出版社,Prentice-Hall International,Inc,Dec,1998
[48]李振涛,陈书明.预防闩锁效应的CMOS版图设计技术.国防科技大学首届研究生学术活动周论文集.长沙:国防科技大学出版社,2001年10月.
[49]Michael L.Bushnell,Vishwani D.Agrawal著,蒋安平,冯建华,王新安译.超大规模集成电路测试-数字、存储器和混合信号系统.北京:电子工业出版社2005.8
[50]A.J.van de Goor.Testing Semiconductor Memories:Theory and Practice.Chichester,UK:John Wiley&Sons,Inc.,1991.
[51]A.J van de Goor,Yervant Zorian.Effective March Algorithms for Testing Single-Order Addressed Memories.Vol 5,no.4 Nov.1994 pp337-345.
[52]R.Dekker,F.Beenker,A.Thijssen.Fault Modeling and Test Algorithm Development for Static Random Access Memories.IEEE International Test Conference,Sep 1988.
[53]A.J.Van De Goor and I.B.S.Tlili.March Tests for Word-Oriented Memories.Proc.Design.Automation and Test in Europe Conference and Exhibition,1998,pp501-508.
[54]Wei-Lun Wang,Kuen-Jong Lee.A Programmable Data Background Generator for March Based Memory Testing.Asic,2002,IEEE,Asia-Pacific Conference
[55]W.W.Peterson and E.J.Weldon,Jr..Error-Correcting Codes.New York:John Wiley & Sons,Inc.,1972
[56]张建民.面向SoC的USB控制器及通用IO控制器的IP核设计与实现.国防科大硕士学位论文,2003
[57]李婉萍.Design and Implementation of a High-Performance Memory Generator国立中山大学资讯工程学系硕士学位论文,2004.7