视频后处理芯片中模块的设计与探索
摘要
数字视频后处理是面向数字电视业务的多样性而产生的数字处理技术。在很长的一段时间内，电视机要同时对模拟电视信号和数字电视信号实现兼容，不同电视信号制式之间的转换将是电视芯片比不可少的功能之一。同时为了提高视觉观赏的效果，利用数字视频处理技术对电视信号进行处理也是电视芯片要处理的一个问题。
本文以视频后处理芯片为立足点，对外部存储器SDRAM的控制器和经过视频后处理算法后的多种视频显示格式产生做了深入的研究，介绍了它们的设计方法，并为后续版本提供了进一步的探索。
数据量庞大、速度要求高和视频显示格式复杂是视频后处理所要面对的主要问题。
SDRAM具有物理体积小，价格便宜、速度较快的优点，是视频后处理芯片外部存储器的理想选择，SDRAM存储着整个视频后处理过程所需要的数据，它是一切工作得以顺利进行的基础。为了解决数据量庞大、速度要求高的问题，SDRAM控制器的设计非常关键。因此，本文在介绍SDRAM基本操作方法的基础上，详细介绍了针对我们目前版本的视频后处理芯片SDRAM控制器的设计方法，同时，为了能在视频后处理芯片实现的后续版本中节省人力和时间，本文在已有SDRAM控制器的基础上，探索实现了一种适用性很强的SDRAM通用控制接口。
视频后处理算法只针对几种典型的输入制式进行隔行变逐行的转换，而多达21种的视频显示格式主要通过视频显示模块来完成，因此，本文在介绍多种视频显示格式的基础上，详细介绍了针对我们目前版本的视频后处理芯片视频显示模块的设计方法，并且为了在视频后处理芯片的后续版本中，进一步提高视频显示的质量，本文对图像插值的方法也进行了探索，通过比较和分析目前多种流行的图像插值方法，得到了后续版本图像插值方法选择的方向。
Digital video post-processing is a kind of digital signal process technology that faced to diversity of digital television formats. Analog and digital video signal will coexist in a long time, so the TV set must be compatible for both kinds of formats. Hence, the chip in the TV should have the ability to convert formats between each other and to enhance the vision effect of the TV picture.
In this dissertation, basing on digital video post-processing chip, we focus on the following two fields: external memory SDRAM controller and generation of video display format.We not only introduce their design methods,but also do some further rearch work for following edition.
In video post-processing, the main problem that we face is: enormous data flow,high speed and complicated video display format.
The advantages of SDRAM are that it is very small,very cheap and fairly faster,so it is the best selection of external memory.SDRAM stores all the required data during the whole video post-processing.it is a base for all work to go on wheels. In order to solve the problem of enormous data flow and high speed.the design of SDRAM controller is very pivotal,so we provide the design method of SDRAM controller in detail based on the introduction of SDRAM'basic operation.At the mean time, In order to save manpower and time in the following edition, we realize a universal SDRAM controller with high applicability in this dissertation.
Our video post-processing algorithm can only convert several tipycal types of interlaced signals to de-interlaced signals.while the 21 types of video display formats must be achieved by video display module. In this dissertation.we provide the design method of video display module in detail based on the introduction of multiplicate video display formats.At the mean time,in order to improve image quality further, by analyzing and comparing a variety of currently popular image sealer methods.we provide a alternative way for selecting appropriate image sealer methods.
本文以视频后处理芯片为立足点，对外部存储器SDRAM的控制器和经过视频后处理算法后的多种视频显示格式产生做了深入的研究，介绍了它们的设计方法，并为后续版本提供了进一步的探索。
数据量庞大、速度要求高和视频显示格式复杂是视频后处理所要面对的主要问题。
SDRAM具有物理体积小，价格便宜、速度较快的优点，是视频后处理芯片外部存储器的理想选择，SDRAM存储着整个视频后处理过程所需要的数据，它是一切工作得以顺利进行的基础。为了解决数据量庞大、速度要求高的问题，SDRAM控制器的设计非常关键。因此，本文在介绍SDRAM基本操作方法的基础上，详细介绍了针对我们目前版本的视频后处理芯片SDRAM控制器的设计方法，同时，为了能在视频后处理芯片实现的后续版本中节省人力和时间，本文在已有SDRAM控制器的基础上，探索实现了一种适用性很强的SDRAM通用控制接口。
视频后处理算法只针对几种典型的输入制式进行隔行变逐行的转换，而多达21种的视频显示格式主要通过视频显示模块来完成，因此，本文在介绍多种视频显示格式的基础上，详细介绍了针对我们目前版本的视频后处理芯片视频显示模块的设计方法，并且为了在视频后处理芯片的后续版本中，进一步提高视频显示的质量，本文对图像插值的方法也进行了探索，通过比较和分析目前多种流行的图像插值方法，得到了后续版本图像插值方法选择的方向。
Digital video post-processing is a kind of digital signal process technology that faced to diversity of digital television formats. Analog and digital video signal will coexist in a long time, so the TV set must be compatible for both kinds of formats. Hence, the chip in the TV should have the ability to convert formats between each other and to enhance the vision effect of the TV picture.
In this dissertation, basing on digital video post-processing chip, we focus on the following two fields: external memory SDRAM controller and generation of video display format.We not only introduce their design methods,but also do some further rearch work for following edition.
In video post-processing, the main problem that we face is: enormous data flow,high speed and complicated video display format.
The advantages of SDRAM are that it is very small,very cheap and fairly faster,so it is the best selection of external memory.SDRAM stores all the required data during the whole video post-processing.it is a base for all work to go on wheels. In order to solve the problem of enormous data flow and high speed.the design of SDRAM controller is very pivotal,so we provide the design method of SDRAM controller in detail based on the introduction of SDRAM'basic operation.At the mean time, In order to save manpower and time in the following edition, we realize a universal SDRAM controller with high applicability in this dissertation.
Our video post-processing algorithm can only convert several tipycal types of interlaced signals to de-interlaced signals.while the 21 types of video display formats must be achieved by video display module. In this dissertation.we provide the design method of video display module in detail based on the introduction of multiplicate video display formats.At the mean time,in order to improve image quality further, by analyzing and comparing a variety of currently popular image sealer methods.we provide a alternative way for selecting appropriate image sealer methods.
引文
[1] ALTERA, "APEX 20K Programmable Logic Device Family", November 1999, ver.2.05, Data Sheet.
[2] ALTERA, "Configuration Devices for ACEX, APEX, FLEX & Mercury Devices", March 2001, ver.11, Data Sheet.
[3] G-LINK Technology, GLT5160L16 ADVANCED, 16M(2-Bank×524288-Word×16-Bit)Synchronous DRAM Date Sheet.
[4] PHILIPS, "SAA7114H, PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler", Preliminary specification File under Integrated Circuits, IC22, 2000 Mar 15.
[5] Micron Technology, "SYNCHRONOUS DRAM, MT48LC2M32B2-521×32×4 banks", 2000.
[6] Samsung Electronics, "64Mbit SDRAM 1M×16Bit×4 Banks Synchronous DRAM LVTTL", Revision 0.1 January 2001.
[7] Samsung Electronics,"64Mbit SDRAM 1M×16Bit×4 Banks Synchronous DRAM LVTTL",Revision 0.1 August 2001..
[8] 《数字信号处理及其MATLAB实现》[美]Vinay K．Ingle John G．Proakis著刘树棠译 西安交通大学出版社．
[9] 《信号与系统》郑君里 杨为理 应启珩编 高等教育出版社．
[10] 《Verilog HDL 实用教程》张明编著 电子科技大学出版社．
[11] 《数字通信》(第四版)[美]John G．Proalds著 张力军 张宗橙 郑宝玉等译 电子工业出版社．
[12] 《数字电视技术：高清晰度数字视频原理与应用》(第三版)曹晨 杨作梅等译电子工业出版社
[13] 《电路设计与制版Protel 99入门与提高》 老虎工作室 高鹏 安涛 寇怀成编著 人民邮电出版社．
[14] 图像工程上册 《图像处理和分析》 章毓晋 编著 清华大学出版社．
[15] A.M.Darwish, M.S.Bedair, S.I.Shaheen, "Adaptive resampling algorithm for image zooming"IEE Proc.-Vis.Image Signal Process, Vol. 144, No.4, August 1997.
[16] Chun-Ho Kim, Si-Mun Seong, Jin-Aeon Lee, and Lee-Sup Kim, "Winscale: An Image-Scaling Algorithm Using an Area Pixel Model", IEEE TRANSACTIONSON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 13, NO.6, JUNE 2003.
[17] Thomas M. Lehmann, Member, IEEE, Claudia Gonner, and klaus Spitzer, "Survey:Interpolation Methods in Medical Image Processing",IEEE TRANSACTIONS ON MEDICALIMAGING,VOL. 18,NO. 11,NOVEMBER 1999.
[18] ALTERA, "SDR SDRAM Controller White Paper", May 2000, ver. 1.
[19] ISSI, "IS42S16400 1 Meg Bits×16 Bits×4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM", FINAL PRODUCTION MAY 2001.
[20] Gerard de Haan Philips Research Laboratories, Eindhoven, The Netherlands, "IC FOR MOTION-COMPENSATED DE-INTERLACING, NOISE REDUCTION, AND PICTURE-RATE CONVERSION".
[21] RECOMMENDATION ITU-R BT.601-5: STUDIO ENCODING PARAMETERS OF DIGITAL TELEVISION FOR STANDARD 4:3 AND WIDE-SCREEN 16:9 ASPECT RATIONS, (Question ITU-R 206/11).
[22] RECOMMENDATION ITU-R BT.656-4: INTERFACES FOR DIGITAL COMPONENT VIDEO SIGNALS IN 525-LINE AND 625-LINE TELEVISION SYSTEMS OPERATING AT THE 4:2:2 LEVEL OF RECOMMENDATION ITU-R BT.601 (PART A), (Question ITU-R 65/11).
[23] Video Electronics Standards Association, Monitor Timing Specifications, "VESA and Industry Standards and GuideIines for Computer Display Monitor Timing Version 1.0, Revision 0.8", Adoption Date: September 17, 1998.
[2] ALTERA, "Configuration Devices for ACEX, APEX, FLEX & Mercury Devices", March 2001, ver.11, Data Sheet.
[3] G-LINK Technology, GLT5160L16 ADVANCED, 16M(2-Bank×524288-Word×16-Bit)Synchronous DRAM Date Sheet.
[4] PHILIPS, "SAA7114H, PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC comb filter, VBI-data slicer and high performance scaler", Preliminary specification File under Integrated Circuits, IC22, 2000 Mar 15.
[5] Micron Technology, "SYNCHRONOUS DRAM, MT48LC2M32B2-521×32×4 banks", 2000.
[6] Samsung Electronics, "64Mbit SDRAM 1M×16Bit×4 Banks Synchronous DRAM LVTTL", Revision 0.1 January 2001.
[7] Samsung Electronics,"64Mbit SDRAM 1M×16Bit×4 Banks Synchronous DRAM LVTTL",Revision 0.1 August 2001..
[8] 《数字信号处理及其MATLAB实现》[美]Vinay K．Ingle John G．Proakis著刘树棠译 西安交通大学出版社．
[9] 《信号与系统》郑君里 杨为理 应启珩编 高等教育出版社．
[10] 《Verilog HDL 实用教程》张明编著 电子科技大学出版社．
[11] 《数字通信》(第四版)[美]John G．Proalds著 张力军 张宗橙 郑宝玉等译 电子工业出版社．
[12] 《数字电视技术：高清晰度数字视频原理与应用》(第三版)曹晨 杨作梅等译电子工业出版社
[13] 《电路设计与制版Protel 99入门与提高》 老虎工作室 高鹏 安涛 寇怀成编著 人民邮电出版社．
[14] 图像工程上册 《图像处理和分析》 章毓晋 编著 清华大学出版社．
[15] A.M.Darwish, M.S.Bedair, S.I.Shaheen, "Adaptive resampling algorithm for image zooming"IEE Proc.-Vis.Image Signal Process, Vol. 144, No.4, August 1997.
[16] Chun-Ho Kim, Si-Mun Seong, Jin-Aeon Lee, and Lee-Sup Kim, "Winscale: An Image-Scaling Algorithm Using an Area Pixel Model", IEEE TRANSACTIONSON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 13, NO.6, JUNE 2003.
[17] Thomas M. Lehmann, Member, IEEE, Claudia Gonner, and klaus Spitzer, "Survey:Interpolation Methods in Medical Image Processing",IEEE TRANSACTIONS ON MEDICALIMAGING,VOL. 18,NO. 11,NOVEMBER 1999.
[18] ALTERA, "SDR SDRAM Controller White Paper", May 2000, ver. 1.
[19] ISSI, "IS42S16400 1 Meg Bits×16 Bits×4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM", FINAL PRODUCTION MAY 2001.
[20] Gerard de Haan Philips Research Laboratories, Eindhoven, The Netherlands, "IC FOR MOTION-COMPENSATED DE-INTERLACING, NOISE REDUCTION, AND PICTURE-RATE CONVERSION".
[21] RECOMMENDATION ITU-R BT.601-5: STUDIO ENCODING PARAMETERS OF DIGITAL TELEVISION FOR STANDARD 4:3 AND WIDE-SCREEN 16:9 ASPECT RATIONS, (Question ITU-R 206/11).
[22] RECOMMENDATION ITU-R BT.656-4: INTERFACES FOR DIGITAL COMPONENT VIDEO SIGNALS IN 525-LINE AND 625-LINE TELEVISION SYSTEMS OPERATING AT THE 4:2:2 LEVEL OF RECOMMENDATION ITU-R BT.601 (PART A), (Question ITU-R 65/11).
[23] Video Electronics Standards Association, Monitor Timing Specifications, "VESA and Industry Standards and GuideIines for Computer Display Monitor Timing Version 1.0, Revision 0.8", Adoption Date: September 17, 1998.