视频后处理芯片中核心算法的硬件实现及芯片的可测试性设计
摘要
数字电视是当前蓬勃发展的一个产业，是目前发达国家争夺激烈的一个技术制高点，反映了一个国家IT产业的综合实力。我国已在2003年全面启动了数字电视的产业化工作，2015年将全面完成由模拟到数字的过渡。
数字电视的接受机中，主要包括信道解调、信源解码、视频后处理三个核心芯片。其中，数字视频后处理芯片由于数字电视出现后，各种新业务的不断加入以及各类新颖显示终端的出现，目前尚无定型产品，是当前最有市场开发价值的数字电视核心芯片之一。
2002年6月至2003年12月，作为《视频后处理芯片设计》项目的核心设计开发人员，本人参与了该芯片的全部设计过程，主要负责前端设计、硬件实现和FPGA验证。
本文以视频后处理项目为依托，详细讨论了SOC芯片硬件设计中的核心及难点。前半部分着重于论述视频后处理芯片中的核心算法及其硬件实现方案，按先后顺序依次论述了基于运动补偿的时域递归去隔行算法，基于运动补偿的帧率提升算法和一种基于九抽头滤波器的色度瞬态改善(CTI)算法；后半部分着重论述了芯片的可测试性设计，并创造性的提出了利用FPGA搭建芯片自动测试(ATE)设备、利用芯片内的扫描链(Scan Chain)进行功能故障检测的方法，并取得了成功；同时还针对FPGA系统测试的困难，提出了一种基于并口EPP模式的FPGA系统调试方案。
本文的主要贡献在于针对视频后处理芯片的特点，对其核心算法及其硬件实做了详细的论述，重点讨论了算法硬件实现的方案和难点。另外，在芯片的可测试性方面，创造性地提出了利用芯片内部的扫描链进行功能故障测试的思想；在FPGA系统的调试方面，创造性地提出来利用计算机并口的EPP模式构建测试平台的思想，同时把这两种思想成功运用于芯片测试和验证中。
Digital Television (Digital TV), as the third generation Television Technology, has become the most important industry in this century. It is now the focus of the technical contest all over the world. It reflects the general competence of a country's IT technology. In our country, the DTV industry has already started in 2003, and by the time 2015 we will finish the transforming from Analog TV to Digital TV.
There are altogether three main chips in the Digital TV's receiver, the channel demodulating chip, the source decoding chip and the Post-process chip. With the appearance of various kinds of new functions and display devices, the Post-process chip has become the most valuable one in Digital TV. It is very important to design and manufact this chip with our own independent intelligence property both for marketing and financial reasons.
From Jun.2002 to Nov.2003,1 had been an intern in the National Chip Technology Company. As a core engineer and developer in the Post-process Chip Project, I took part in the whole design process of this chip and accumulated a lot of knowledge, skills and experience in ASIC design and DTV techlonogy.
This paper focuses on the core algorithms in the Post-Process Chip and their hardware realizations in ASIC. After that, it introduces the design for test techlonogy in this chip and some valuable and important methods of debugging and testing for both the chip and FPGA systems.
The main contributions of this paper are discussing the core algorithms in Post-Process Chip and their implementations in ASIC. It also proposes some constructive ideas of the debugging and testing of the ASIC and FPGA systems.
数字电视的接受机中，主要包括信道解调、信源解码、视频后处理三个核心芯片。其中，数字视频后处理芯片由于数字电视出现后，各种新业务的不断加入以及各类新颖显示终端的出现，目前尚无定型产品，是当前最有市场开发价值的数字电视核心芯片之一。
2002年6月至2003年12月，作为《视频后处理芯片设计》项目的核心设计开发人员，本人参与了该芯片的全部设计过程，主要负责前端设计、硬件实现和FPGA验证。
本文以视频后处理项目为依托，详细讨论了SOC芯片硬件设计中的核心及难点。前半部分着重于论述视频后处理芯片中的核心算法及其硬件实现方案，按先后顺序依次论述了基于运动补偿的时域递归去隔行算法，基于运动补偿的帧率提升算法和一种基于九抽头滤波器的色度瞬态改善(CTI)算法；后半部分着重论述了芯片的可测试性设计，并创造性的提出了利用FPGA搭建芯片自动测试(ATE)设备、利用芯片内的扫描链(Scan Chain)进行功能故障检测的方法，并取得了成功；同时还针对FPGA系统测试的困难，提出了一种基于并口EPP模式的FPGA系统调试方案。
本文的主要贡献在于针对视频后处理芯片的特点，对其核心算法及其硬件实做了详细的论述，重点讨论了算法硬件实现的方案和难点。另外，在芯片的可测试性方面，创造性地提出了利用芯片内部的扫描链进行功能故障测试的思想；在FPGA系统的调试方面，创造性地提出来利用计算机并口的EPP模式构建测试平台的思想，同时把这两种思想成功运用于芯片测试和验证中。
Digital Television (Digital TV), as the third generation Television Technology, has become the most important industry in this century. It is now the focus of the technical contest all over the world. It reflects the general competence of a country's IT technology. In our country, the DTV industry has already started in 2003, and by the time 2015 we will finish the transforming from Analog TV to Digital TV.
There are altogether three main chips in the Digital TV's receiver, the channel demodulating chip, the source decoding chip and the Post-process chip. With the appearance of various kinds of new functions and display devices, the Post-process chip has become the most valuable one in Digital TV. It is very important to design and manufact this chip with our own independent intelligence property both for marketing and financial reasons.
From Jun.2002 to Nov.2003,1 had been an intern in the National Chip Technology Company. As a core engineer and developer in the Post-process Chip Project, I took part in the whole design process of this chip and accumulated a lot of knowledge, skills and experience in ASIC design and DTV techlonogy.
This paper focuses on the core algorithms in the Post-Process Chip and their hardware realizations in ASIC. After that, it introduces the design for test techlonogy in this chip and some valuable and important methods of debugging and testing for both the chip and FPGA systems.
The main contributions of this paper are discussing the core algorithms in Post-Process Chip and their implementations in ASIC. It also proposes some constructive ideas of the debugging and testing of the ASIC and FPGA systems.
引文
[
【1】 E.W. Engstrom, 'A study of Television Image Characteristics', Proc. Of the I.R.E.; Vol. 23,no.4, 1935,pp. 295-310
【2】 S. Pigeon and P.Guillotel, 'Advantages and Drawbacks of Interlaced and Progressive Scanning Formats', HAMLET report, RACE 2110,1996
【3】 E. Dubois, G. de Haan and T Kurita, 'Motion estimation and compensation technologies for standards conversion', Preface to special issue of Signal Processing:Image Communication, no. 6, 1994, pp. 189-192
【4】 G. De Haan, J. kettenis, and B. De Loore, 'IC for motion-compensated 100 Hz TV with natural motion movie-mode', IEEE Tr. On Cons. Electr, May 1996
【5】 Microsoft, 'Broadcast-Enabled Computer Hardware Requirements', WinHEC'97, Broadcast Technologies White Paper, 1997, pp. 11-12
【6】 L. J. Thorpe and T. Hanabusa, 'If Progressive Scanning is so good, how bad is interlace?', SAMPTE Journal, Dec. 1990, pp. 11-12
【7】 P. Guillotel and G.D'Agostino, "Towards the Use of a Progressive Transmission Format', Proc. Int. Workshop in HDTV and the Evolution of Television, Nov. 1995, Taipei
【8】 D. Bagni, G. de Haan, and V. Riva, 'Motion compensated post-processing for low bit rate video conferencing on ISDN lines', To appear in IEEE Tr. On Cons. Electr. Aug. 1997
【9】 A.W.M. van den Enden and N.A.M. Verhoeckx, Discrete-time signal processing, Pretice Hall, ISBN 0-13-216763-8, 1989,pp. 233
【10】 G.J Tonge, 'Television motion portrayal'Presented at Les Assises des Jeunes Chercheurs, Sep. 1985, Rennes(Fr.)
【11】 A.M. Tekalp, 'Digital video processing', Prentice Hall 1995, ISBN 0-13-190075-7,pp250-.
【12】 M. Achiha, K. Ishikura and T. Fukinuki, 'A Motion-adaptive High-definition Converter for NTSC Color TV Signals', SMPTE Journal, Vol.93, no.5, May 1984,pp. 470-476
【13】 R.S. Prodan,'Multidimensional Digital Signal Processing for Television Scan Conversion', Philips J. of Research, Vol.41, no.6, 1986,pp.576-630
【14】 A.M. Bock, 'Motion-Adaptive Standards Conversion Between Formats of Similar Field Rates', Signal Processing: Image Communication, Vol.6, no.3, Jun. 1994
【15】 N.Seth-Smith and G. Walker, 'Flexible upconversion for High Quality TV and Multimedia Displays', Proc. Of the ICCE, Jun.1996, Chicago, pp.338-339
【16】 P.D. Filliman, T.J. Christopher and R.T. Keen, 'Interlace to progressive scan converter for IDTV', IEEE Tr. On Cons. Electr., Vol.38, no. 3, Aug. 1992, pp. 135-144
【17】 C. Hentschel, 'Comparison between median filtering and vertical edge controlled interpolation
for flicker reduction', IEEE Tr. On Cons. Electr, Aug.1989, Vol.35, no.3, pp.279-289
【18】 C. Hentschel, television with increased image quality; Flicker reduction through on increased picture rate in the receiver, Ph.D. thesis, institutfur Nachrichtentechnik, Tech. Univ. Braunschweig, Germany, Feb. 1990, (in german).
【19】 T. Doyle and M. Looymans,'Progressive Scan Conversion using Edge Information', in: Signal Processing of HDTV, Ⅱ, L. Chiariglione, Ed., Elsevier Science Punlishers, 1990, pp.711-721
【20】 Preliminary data sheet of Genesis gmVLD8, 8 bit Digital Video Line Doubler, Version 1.0, Jun. 1996
【21】 M.Lee, J.Kim, J.Lee, K.Ryu and D.Song, 'A new algorithm for interlaced to progressive scan conversion based on directional correlations and its IC design', IEEE Tr. On Cons.Electr., Vlo.40, no.2, May 1994, pp.119-129
【22】 J.Salonen, S.Kalli, 'Edge Adaptive Interpolation for Scanning Rate Conversion', in Signal Processing of HDTV, IV, E.Dubois and L.Chiariglione, Eds., Elsevier Science Publishers, 1993, pp.757-764
【23】 M.J.J.C. Annegarn, T.Doyle, P.H. Frencken, and D.A. van Hees, 'Video signal processing circuit for processing an interlaced video signal', European Patent Application no. EP-A 0 192 292.
【24】 H.Hwang, M.H.Lee and D.I.Song, 'Interlaced to progressive scan conversion with double smoothing', IEEE Tr. On Cons. Electr., Vol.39, No.3,Aug. 1993, pp. 241-246
【25】 Phlips Semiconductors, 'Datasheet SAA4990, PROZONIC', 1995
【26】 Hyung-Jin, Choi, Se-Woong Park, Gyun-sil Jang, Chun-soo Kim. "Color Transient Improvement (CTI)". Consumer Electronics, 2000. ICCE. 2000 Digest of Technical Papers. International Conference on, 13-15 June 2000.
【27】 Christian Hentschel, David La Hei. "EFFECTIVE PEAKING FILTER AND ITS IMPLEMENTATION". Consumer Electronics, IEEE Transactions on, Volume: 47 Issue: 1, Feb. 2001.
【28】 Bhatnagar, Himanshu. Advanced ASIC Chip Synthesis: Using Synopsys Designer Compiler and PrimeTime, Kluwer Academic Publishers, 2000.
【29】 Nekoogar, Fazard. Timing Verification of Application-Specific Integrated Circuits
【30】 Jim Turley. "CPU and DSP cores vie for ASIC designer's attention", Computer Design, pp.75-86, Jan. 1997.
【31】 Barbara Tuck, "Integrating IP blocks to create a system-on a chip", Computer Design, pp.49-61, Nov. 1997.
【32】 王爱英，《计算机组成与结构》，清华大学出版社，1995
【33】 石教英，《计算机体系结构》，浙江大学出版社，1998
【34】 余兆明主编．数字电视和高清晰度电视．人民邮电出版社，1997．
【35】 罗胜钦编著，“数字集成系统芯片(SOC)设计”，北京希望电子出版社，2002年9月。
【36】 康宝祥，栾贵兴著，“RISC体系结构及其实现技术”，科学出版社，1996
【37】 何小艇，《数字电路》，浙江大学出版社，1995。
【38】 夏宇闻，《复杂数字电路与系统的Verilog HDL设计技术》，北京航空航天大学出版社，1998。
【39】 周祖成，王志华，“专用集成电路和集成系统自动化设计方法”，国防工业出版社，1997。
【40】 简贵胃，葛宁，冯重熙，“静态时序分析方法的基本原理和应用”，计算机工程与应用，Vol．38，No．14，pp．115-116，221，2002．
【41】 丁瑾，“可靠性与可测试性分析设计”，北京邮电大学出版社，1996年7月。
【42】 《集成电路可测性设计讲义》，“Fundamentals on Testing and Design for Testability”．
【1】 E.W. Engstrom, 'A study of Television Image Characteristics', Proc. Of the I.R.E.; Vol. 23,no.4, 1935,pp. 295-310
【2】 S. Pigeon and P.Guillotel, 'Advantages and Drawbacks of Interlaced and Progressive Scanning Formats', HAMLET report, RACE 2110,1996
【3】 E. Dubois, G. de Haan and T Kurita, 'Motion estimation and compensation technologies for standards conversion', Preface to special issue of Signal Processing:Image Communication, no. 6, 1994, pp. 189-192
【4】 G. De Haan, J. kettenis, and B. De Loore, 'IC for motion-compensated 100 Hz TV with natural motion movie-mode', IEEE Tr. On Cons. Electr, May 1996
【5】 Microsoft, 'Broadcast-Enabled Computer Hardware Requirements', WinHEC'97, Broadcast Technologies White Paper, 1997, pp. 11-12
【6】 L. J. Thorpe and T. Hanabusa, 'If Progressive Scanning is so good, how bad is interlace?', SAMPTE Journal, Dec. 1990, pp. 11-12
【7】 P. Guillotel and G.D'Agostino, "Towards the Use of a Progressive Transmission Format', Proc. Int. Workshop in HDTV and the Evolution of Television, Nov. 1995, Taipei
【8】 D. Bagni, G. de Haan, and V. Riva, 'Motion compensated post-processing for low bit rate video conferencing on ISDN lines', To appear in IEEE Tr. On Cons. Electr. Aug. 1997
【9】 A.W.M. van den Enden and N.A.M. Verhoeckx, Discrete-time signal processing, Pretice Hall, ISBN 0-13-216763-8, 1989,pp. 233
【10】 G.J Tonge, 'Television motion portrayal'Presented at Les Assises des Jeunes Chercheurs, Sep. 1985, Rennes(Fr.)
【11】 A.M. Tekalp, 'Digital video processing', Prentice Hall 1995, ISBN 0-13-190075-7,pp250-.
【12】 M. Achiha, K. Ishikura and T. Fukinuki, 'A Motion-adaptive High-definition Converter for NTSC Color TV Signals', SMPTE Journal, Vol.93, no.5, May 1984,pp. 470-476
【13】 R.S. Prodan,'Multidimensional Digital Signal Processing for Television Scan Conversion', Philips J. of Research, Vol.41, no.6, 1986,pp.576-630
【14】 A.M. Bock, 'Motion-Adaptive Standards Conversion Between Formats of Similar Field Rates', Signal Processing: Image Communication, Vol.6, no.3, Jun. 1994
【15】 N.Seth-Smith and G. Walker, 'Flexible upconversion for High Quality TV and Multimedia Displays', Proc. Of the ICCE, Jun.1996, Chicago, pp.338-339
【16】 P.D. Filliman, T.J. Christopher and R.T. Keen, 'Interlace to progressive scan converter for IDTV', IEEE Tr. On Cons. Electr., Vol.38, no. 3, Aug. 1992, pp. 135-144
【17】 C. Hentschel, 'Comparison between median filtering and vertical edge controlled interpolation
for flicker reduction', IEEE Tr. On Cons. Electr, Aug.1989, Vol.35, no.3, pp.279-289
【18】 C. Hentschel, television with increased image quality; Flicker reduction through on increased picture rate in the receiver, Ph.D. thesis, institutfur Nachrichtentechnik, Tech. Univ. Braunschweig, Germany, Feb. 1990, (in german).
【19】 T. Doyle and M. Looymans,'Progressive Scan Conversion using Edge Information', in: Signal Processing of HDTV, Ⅱ, L. Chiariglione, Ed., Elsevier Science Punlishers, 1990, pp.711-721
【20】 Preliminary data sheet of Genesis gmVLD8, 8 bit Digital Video Line Doubler, Version 1.0, Jun. 1996
【21】 M.Lee, J.Kim, J.Lee, K.Ryu and D.Song, 'A new algorithm for interlaced to progressive scan conversion based on directional correlations and its IC design', IEEE Tr. On Cons.Electr., Vlo.40, no.2, May 1994, pp.119-129
【22】 J.Salonen, S.Kalli, 'Edge Adaptive Interpolation for Scanning Rate Conversion', in Signal Processing of HDTV, IV, E.Dubois and L.Chiariglione, Eds., Elsevier Science Publishers, 1993, pp.757-764
【23】 M.J.J.C. Annegarn, T.Doyle, P.H. Frencken, and D.A. van Hees, 'Video signal processing circuit for processing an interlaced video signal', European Patent Application no. EP-A 0 192 292.
【24】 H.Hwang, M.H.Lee and D.I.Song, 'Interlaced to progressive scan conversion with double smoothing', IEEE Tr. On Cons. Electr., Vol.39, No.3,Aug. 1993, pp. 241-246
【25】 Phlips Semiconductors, 'Datasheet SAA4990, PROZONIC', 1995
【26】 Hyung-Jin, Choi, Se-Woong Park, Gyun-sil Jang, Chun-soo Kim. "Color Transient Improvement (CTI)". Consumer Electronics, 2000. ICCE. 2000 Digest of Technical Papers. International Conference on, 13-15 June 2000.
【27】 Christian Hentschel, David La Hei. "EFFECTIVE PEAKING FILTER AND ITS IMPLEMENTATION". Consumer Electronics, IEEE Transactions on, Volume: 47 Issue: 1, Feb. 2001.
【28】 Bhatnagar, Himanshu. Advanced ASIC Chip Synthesis: Using Synopsys Designer Compiler and PrimeTime, Kluwer Academic Publishers, 2000.
【29】 Nekoogar, Fazard. Timing Verification of Application-Specific Integrated Circuits
【30】 Jim Turley. "CPU and DSP cores vie for ASIC designer's attention", Computer Design, pp.75-86, Jan. 1997.
【31】 Barbara Tuck, "Integrating IP blocks to create a system-on a chip", Computer Design, pp.49-61, Nov. 1997.
【32】 王爱英，《计算机组成与结构》，清华大学出版社，1995
【33】 石教英，《计算机体系结构》，浙江大学出版社，1998
【34】 余兆明主编．数字电视和高清晰度电视．人民邮电出版社，1997．
【35】 罗胜钦编著，“数字集成系统芯片(SOC)设计”，北京希望电子出版社，2002年9月。
【36】 康宝祥，栾贵兴著，“RISC体系结构及其实现技术”，科学出版社，1996
【37】 何小艇，《数字电路》，浙江大学出版社，1995。
【38】 夏宇闻，《复杂数字电路与系统的Verilog HDL设计技术》，北京航空航天大学出版社，1998。
【39】 周祖成，王志华，“专用集成电路和集成系统自动化设计方法”，国防工业出版社，1997。
【40】 简贵胃，葛宁，冯重熙，“静态时序分析方法的基本原理和应用”，计算机工程与应用，Vol．38，No．14，pp．115-116，221，2002．
【41】 丁瑾，“可靠性与可测试性分析设计”，北京邮电大学出版社，1996年7月。
【42】 《集成电路可测性设计讲义》，“Fundamentals on Testing and Design for Testability”．