自适应回波消除器研究及其FPGA实现
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摘要
回波消除器广泛应用于公用电话交换网(PSTN)、移动通信系统和视频电话会议系统等多种语音通信领域。在PSTN系统中，由于线路阻抗不匹配，远端语音信号通过混合线圈时产生一定泄漏，一部分信号又传回远端，产生线路回波，回波的存在会严重影响语音通信质量。本文主要针对线路回波进行研究，设计并实现了满足实用要求的基于FPGA平台的回波消除器。
首先，对回波产生原理和目前几种常用回波消除算法进行了分析，在研究自适应回波消除器的各个模块，特别是深入分析各种自适应滤波算法和双讲检测算法，综合考虑各种算法的运算复杂度和性能的情况下，这里采用NLMS算法实现白适应回波消除器。针对传统双讲检测算法在近端语音幅度较低情况下容易产生误判的情况，给出一种基于子带滤波器组的改进双讲检测算法。
本文首先使用C语言实现回波消除器的各个模块，其中包括自适应滤波器、远端检测、双讲检测、非线性处理和舒适噪声产生模块。经过仿真测试，相关模块算法能够有效提高回波消除器性能。在此基础上，本文使用硬件描述语言Verilog HDL，在QuartusⅡ和ModelSim软件平台上实现各功能模块，并通过模块级和系统级功能仿真以及时序仿真验证，最终在现场可编程门阵列(Field Programmable Gate Array，FPGA)平台上实现回波消除系统。本文详细阐述了基于FPGA的设计流程与设计方法，并描述了自适应滤波器、基于分布式算法FIR滤波器、除法器和有限状态机的设计过程。
根据ITU-T G.168标准提出的测试要求，本文对基于FPGA设计实现的自适应回波消除系统进行大量主客观测试。经过测试，各项性能指标均达到或超过G.168标准的要求，具有良好的回波消除效果。
Echo canceller is widely used in PSTN system, mobile communication system, video teleconferencing system, and other speech telecommunication fields. In PSTN system, because of the resistance matching problem, signal leakage is generated and reflected to the far-end when the far-end signal go through the hybrid, which is called line echo, and the existence of line echo will seriously affect the quality of speech communication. This paper primarily studies on line echo cancellation technology, and proposes a system implementation solution based on the platform of FPGA which satisfies the demands for practical application.
In accordance with the generating principle of line echo and after analyzing main echo cancellation algorithms, and after in-depth study on the core algorithms of all the module of adaptive echo canceller, in particular, adaptive filtering algorithm and double talk detection algorithm, considering with complexities and capabilities of all the candidates, this paper chooses NLMS algorithm to implement echo canceller. In order to improve traditional double talk detection algorithm easily leads to misjudging when near-end speech signal amplitude is low, this paper proposes an improved algorithm on double talk detection based on sub-band filter banks.
This paper first completes C program version of all the echo cancellation algorithm modules, including the adaptive filter, far-end detection, double talk detection, non-linear processing and comfort noise modules. The results of simulation tests prove that the algorithm modules effectively improve the performance of echo cancellation.On the basis of C program version, all the hardware modules of the algorithms are completed, using Verilog HDL hardware description language. The hardware modules of the algorithms achieve through module-level and system-level functional simulation, timing simulation on the software platform of Quartus II and ModelSim, and ultimately this paper achieves the system based on FPGA hardware platform. This paper elaborates on FPGA-based design flow and design methods, and describes the adaptive filter algorithm, FIR filter based on distribute arithmetic, divider and finite state machine design process.
According to the ITU-T G.168 standard, large numbers of subjective and objective testing is completed on the FPGA-based adaptive echo cancellation system, which is proved effective on echo cancellation and the test results meet or even surpass the demands of ITU-T G.168 standard.
首先，对回波产生原理和目前几种常用回波消除算法进行了分析，在研究自适应回波消除器的各个模块，特别是深入分析各种自适应滤波算法和双讲检测算法，综合考虑各种算法的运算复杂度和性能的情况下，这里采用NLMS算法实现白适应回波消除器。针对传统双讲检测算法在近端语音幅度较低情况下容易产生误判的情况，给出一种基于子带滤波器组的改进双讲检测算法。
本文首先使用C语言实现回波消除器的各个模块，其中包括自适应滤波器、远端检测、双讲检测、非线性处理和舒适噪声产生模块。经过仿真测试，相关模块算法能够有效提高回波消除器性能。在此基础上，本文使用硬件描述语言Verilog HDL，在QuartusⅡ和ModelSim软件平台上实现各功能模块，并通过模块级和系统级功能仿真以及时序仿真验证，最终在现场可编程门阵列(Field Programmable Gate Array，FPGA)平台上实现回波消除系统。本文详细阐述了基于FPGA的设计流程与设计方法，并描述了自适应滤波器、基于分布式算法FIR滤波器、除法器和有限状态机的设计过程。
根据ITU-T G.168标准提出的测试要求，本文对基于FPGA设计实现的自适应回波消除系统进行大量主客观测试。经过测试，各项性能指标均达到或超过G.168标准的要求，具有良好的回波消除效果。
Echo canceller is widely used in PSTN system, mobile communication system, video teleconferencing system, and other speech telecommunication fields. In PSTN system, because of the resistance matching problem, signal leakage is generated and reflected to the far-end when the far-end signal go through the hybrid, which is called line echo, and the existence of line echo will seriously affect the quality of speech communication. This paper primarily studies on line echo cancellation technology, and proposes a system implementation solution based on the platform of FPGA which satisfies the demands for practical application.
In accordance with the generating principle of line echo and after analyzing main echo cancellation algorithms, and after in-depth study on the core algorithms of all the module of adaptive echo canceller, in particular, adaptive filtering algorithm and double talk detection algorithm, considering with complexities and capabilities of all the candidates, this paper chooses NLMS algorithm to implement echo canceller. In order to improve traditional double talk detection algorithm easily leads to misjudging when near-end speech signal amplitude is low, this paper proposes an improved algorithm on double talk detection based on sub-band filter banks.
This paper first completes C program version of all the echo cancellation algorithm modules, including the adaptive filter, far-end detection, double talk detection, non-linear processing and comfort noise modules. The results of simulation tests prove that the algorithm modules effectively improve the performance of echo cancellation.On the basis of C program version, all the hardware modules of the algorithms are completed, using Verilog HDL hardware description language. The hardware modules of the algorithms achieve through module-level and system-level functional simulation, timing simulation on the software platform of Quartus II and ModelSim, and ultimately this paper achieves the system based on FPGA hardware platform. This paper elaborates on FPGA-based design flow and design methods, and describes the adaptive filter algorithm, FIR filter based on distribute arithmetic, divider and finite state machine design process.
According to the ITU-T G.168 standard, large numbers of subjective and objective testing is completed on the FPGA-based adaptive echo cancellation system, which is proved effective on echo cancellation and the test results meet or even surpass the demands of ITU-T G.168 standard.
引文
[1] ITU-T Recommendation G. 165, Echo Cancellers, 1993.
[2] ITU-T Recommendation G. 167, Acoustic Echo Controllers, 1993.
[3] ITU-T Recommendation G. 168, Echo Cancellers, 1997.
[4] 杜慧敏等．基于Verilog的FPGA设计基础．西安：电子科技大学出版社，2006．
[5] 陈宗基．自适应技术的理论及应用．北京：航空航天大学出版社，1991．
[6] D. L. Duttweiler, Y. S. Chen. A single-chip VLSI echo canceller. BSTJ, 1980, 59(2): 149-160.
[7] ITU-T Recommendation G. 164, Echo Suppressors, 1988.
[8] 覃景繁，韦岗，欧阳景正。回波消除理论进展及其应用．电路与系统学报，1998，3(3)：73-80．
[9] Simon Haykin. Adaptive Filter Theory(Fourth Edition). 北京：电子工业出版社，2002．
[10] Altera Corporation. Stratix Device Handbook, 2006.
[11] 王宏禹．随机数字信号处理．北京：科学出版社，1988．
[12] Simon Haykin．自适应滤波器原理(第四版)．北京：电子工业出版社，2003．
[13] S. Narayan, A. M. Peterson, M. J. Narasimha. Transform domain LMS algorithm. IEEE Trans. on Acoustics, Speech and Signal Processing, 1983, 31(6): 609-615.
[14] D. T. M. Slock. On the convergence behavior of the LMS and the normalized LMS algorithm. IEEE Trans. on Signal Processing, 1993, 41(9): 2811-2825.
[15] J. M. Cioffi, T. Kailath. Fast recursive least squares transversal filters for adaptive filtering. IEEETrans. on Acoustics, Speech and Signal Processing, 1984, 32(2): 304-337.
[16] JUN H. C. Denis, R. Morgan, J. Benesty. An objective technique for evaluating double talk detectors in acoustic echo cancellers. IEEE Transactions on Speech and Audio Processing, 1999, 7(6): 718-724.
[17] J. Benesty, R. Morgan, T. H. CHO. A new class of double talk detectors based on cross correlation. IEEE Transactions on Speech and Audio Processing, 2000, 8(2): 168-172.
[18] H. Ye, B. X. Wu. A new double-talk detection algorithm based on the orthogonality theorem. IEEE Transactions on Communication, 1991, 39: 1542-1545.
[19] Soman A. K., Vaidyanthan P. P.. Theory of optimal or thonormal subband coders. IEEE Trans. on Signal Processing, 1998, 46(6): 1528-1534.
[20] Kirac A., Vaidyanathan P. P.. Theory and design of optimum FIR compaction filters. IEEE Trans. on Signal Processing, 1998, 46(4): 903-919.
[21] 王炳锡．语音编码．西安：西安电子科技大学出版社，2002．
[22] 夏宇闻．Verilog数字系统设计教程．北京：北京航空航天大学出版社，2003．
[23] 郑亚民，董晓舟．可编程逻辑器件开发软件Quartus Ⅱ．北京：国防工业出版社，2006，9
[24] Altera Corporation. Data Sheet: Stratix EP1S25DSP Development Board, 2004.
[25] 潘松，黄继业．EDA技术与VHDL．北京：清华大学出版社，2005．
[26] Altera Corporation. Quartus Ⅱ Version5.0 Handbook, 2005.
[27] 蒋璇，臧春华．数字系统设计与PLD应用技术．北京：电子工业出版社，2001．
[28] 吴继华，王诚．Altera FPGA／CPLD设计(基础篇)．北京：人民邮电出版社，2005．
[29] 吴继华，王诚．Altera FPGA／CPLD设计(高级篇)．北京：人民邮电出版社，2005．
[30] Keshab K．Parhi著，陈弘毅等译．VLSI数字信号处理系统设计与实现．北京：机械工业出版社，2004．
[31] Uwe Meyeer-Baese．数字信号处理的FPGA实现(第二版)．北京：清华大学出版社，2006，6．
[32] A. Croisier, D. Esteban, M. Levilion, V. Rizo. Digital filter for PCM encoded signals. US Patent Nr. 3777130, 1973.
[33] A. Peled, B. Liu. A new realization of digita filters. IEEE Transactions on Acoustics, Speech and Signal Processing, 1974, 24(12): 456-462.
[34] K. Yiu. On sign-bit assignment for a vector multiplier. Prceedings of the IEEE, 1976, 64: 372-373.
[35] K. Kammeyer. Quantization error on the distributed arithmetic. IEEE Transactions on Circuits and Systems, 1981, 24(12): 681-689.
[36] F. Taylor. An analysis of the distributed-arithmetic digial filter. IEEE Transactions on Acoustics, Speech and Signal Processing, 1986, 35(5): 1165-1170.
[37] F. Taylor. Digital Filter Design Handbook. Marcel Dekker, New York, 1983.
[38] H. Schmid. Fast fourier transform and convolution algorithms. Springs, Heidelberg, 1900.
[39] 王冠．面向CPLD／FPGA的Verilog设计[M]．北京：机械工业出版社，2007．3．
[40] 姜宇柏，黄志强．通信收发信机的Verilog实现与仿真．北京：机械工业出版社，2006．
[2] ITU-T Recommendation G. 167, Acoustic Echo Controllers, 1993.
[3] ITU-T Recommendation G. 168, Echo Cancellers, 1997.
[4] 杜慧敏等．基于Verilog的FPGA设计基础．西安：电子科技大学出版社，2006．
[5] 陈宗基．自适应技术的理论及应用．北京：航空航天大学出版社，1991．
[6] D. L. Duttweiler, Y. S. Chen. A single-chip VLSI echo canceller. BSTJ, 1980, 59(2): 149-160.
[7] ITU-T Recommendation G. 164, Echo Suppressors, 1988.
[8] 覃景繁，韦岗，欧阳景正。回波消除理论进展及其应用．电路与系统学报，1998，3(3)：73-80．
[9] Simon Haykin. Adaptive Filter Theory(Fourth Edition). 北京：电子工业出版社，2002．
[10] Altera Corporation. Stratix Device Handbook, 2006.
[11] 王宏禹．随机数字信号处理．北京：科学出版社，1988．
[12] Simon Haykin．自适应滤波器原理(第四版)．北京：电子工业出版社，2003．
[13] S. Narayan, A. M. Peterson, M. J. Narasimha. Transform domain LMS algorithm. IEEE Trans. on Acoustics, Speech and Signal Processing, 1983, 31(6): 609-615.
[14] D. T. M. Slock. On the convergence behavior of the LMS and the normalized LMS algorithm. IEEE Trans. on Signal Processing, 1993, 41(9): 2811-2825.
[15] J. M. Cioffi, T. Kailath. Fast recursive least squares transversal filters for adaptive filtering. IEEETrans. on Acoustics, Speech and Signal Processing, 1984, 32(2): 304-337.
[16] JUN H. C. Denis, R. Morgan, J. Benesty. An objective technique for evaluating double talk detectors in acoustic echo cancellers. IEEE Transactions on Speech and Audio Processing, 1999, 7(6): 718-724.
[17] J. Benesty, R. Morgan, T. H. CHO. A new class of double talk detectors based on cross correlation. IEEE Transactions on Speech and Audio Processing, 2000, 8(2): 168-172.
[18] H. Ye, B. X. Wu. A new double-talk detection algorithm based on the orthogonality theorem. IEEE Transactions on Communication, 1991, 39: 1542-1545.
[19] Soman A. K., Vaidyanthan P. P.. Theory of optimal or thonormal subband coders. IEEE Trans. on Signal Processing, 1998, 46(6): 1528-1534.
[20] Kirac A., Vaidyanathan P. P.. Theory and design of optimum FIR compaction filters. IEEE Trans. on Signal Processing, 1998, 46(4): 903-919.
[21] 王炳锡．语音编码．西安：西安电子科技大学出版社，2002．
[22] 夏宇闻．Verilog数字系统设计教程．北京：北京航空航天大学出版社，2003．
[23] 郑亚民，董晓舟．可编程逻辑器件开发软件Quartus Ⅱ．北京：国防工业出版社，2006，9
[24] Altera Corporation. Data Sheet: Stratix EP1S25DSP Development Board, 2004.
[25] 潘松，黄继业．EDA技术与VHDL．北京：清华大学出版社，2005．
[26] Altera Corporation. Quartus Ⅱ Version5.0 Handbook, 2005.
[27] 蒋璇，臧春华．数字系统设计与PLD应用技术．北京：电子工业出版社，2001．
[28] 吴继华，王诚．Altera FPGA／CPLD设计(基础篇)．北京：人民邮电出版社，2005．
[29] 吴继华，王诚．Altera FPGA／CPLD设计(高级篇)．北京：人民邮电出版社，2005．
[30] Keshab K．Parhi著，陈弘毅等译．VLSI数字信号处理系统设计与实现．北京：机械工业出版社，2004．
[31] Uwe Meyeer-Baese．数字信号处理的FPGA实现(第二版)．北京：清华大学出版社，2006，6．
[32] A. Croisier, D. Esteban, M. Levilion, V. Rizo. Digital filter for PCM encoded signals. US Patent Nr. 3777130, 1973.
[33] A. Peled, B. Liu. A new realization of digita filters. IEEE Transactions on Acoustics, Speech and Signal Processing, 1974, 24(12): 456-462.
[34] K. Yiu. On sign-bit assignment for a vector multiplier. Prceedings of the IEEE, 1976, 64: 372-373.
[35] K. Kammeyer. Quantization error on the distributed arithmetic. IEEE Transactions on Circuits and Systems, 1981, 24(12): 681-689.
[36] F. Taylor. An analysis of the distributed-arithmetic digial filter. IEEE Transactions on Acoustics, Speech and Signal Processing, 1986, 35(5): 1165-1170.
[37] F. Taylor. Digital Filter Design Handbook. Marcel Dekker, New York, 1983.
[38] H. Schmid. Fast fourier transform and convolution algorithms. Springs, Heidelberg, 1900.
[39] 王冠．面向CPLD／FPGA的Verilog设计[M]．北京：机械工业出版社，2007．3．
[40] 姜宇柏，黄志强．通信收发信机的Verilog实现与仿真．北京：机械工业出版社，2006．