基于FPGA的回波抵消器设计与实现
摘要
回波抵消器在免提电话、无线产品、IP电话、ATM语音服务和电话会议等系统中，都有着重要的应用。在不同应用场合对回波抵消器的要求并不完全相同，本文主要研究应用于电话系统中的电回波抵消器。电回波是由于语音信号在电话网中传输时由于阻抗不匹配而产生的。
传统回波抵消器主要是基于通用DSP处理器实现的，这种回波抵消器在系统实时性要求不高的场合能很好的满足回波抵消的性能要求，但是在实时性要求较高的场合，其处理速度等性能方面已经不能满足系统高速、实时的需要。现代大容量、高速度的FPGA的出现，克服了上诉方案的诸多不足。用FPGA来实现数字信号处理可以很好地解决并行性和速度问题，且其灵活的可配置特性使得FPGA构成的DSP系统非常易于修改、测试和硬件升级。
本文研究目标是如何在FPGA芯片上实现回波抵消器，完成的主要工作有：
(1)深入研究了回波抵消器各模块算法，包括自适应滤波算法、远端检测算法、双讲检测算法、NLP算法、舒适噪声产生算法，并实现了这些算法的C程序。
(2)深入研究了回波抵消器基于FPGA的设计流程与实现方法，并利用硬件描述语言Verilog HDL实现了各部分算法。
(3)在QuartusⅡ和ModelSim仿真环境下对该系统进行模块级和系统级的功能仿真、时序仿真和验证。并在FPGA硬件平台上实现了该系统。
(4)根据ITU-T G.168的标准和建议，对设计进行了大量的主、客测试，各项测试结果均达到或优于G.168的要求。
In system such as handfree telephone, wireless production , IP telephone , ATM speech service, telephone conference and so on echo cancellation theory has its important application. The solution of echo canceller is different in some way. This paper is focused on electrics echo canceller in PSTN. Electrics echo is produced because impedence is unsuited when speech signal transmitted in PSTN.
Echo canceller is usually implemented on DSP processor.Such echo canceller can meet performance of echo cancellation on the occasion that has lower request of real-time quality. But when the request of real-time is high, the performance such as processing speed can't meet real-time realization. FPGA which has large capacity and high speed overcome the deficiencies as before mentioned. Using FPGA to implement digital signals processing can resolve the problem about parallel and speed. The characteristic of nimble disposition make the system easier to amend, test and promote.
In this thesis, Echo canceller is implemented on FPGA. The main accomplished task of this theis concludes the following parts:
1 .Researched all modules of adaptive echo canceller include adaptive filter, far detector, double talk detector, NLP, comfort noise generator, and then implemented using C language.
2. Researched flow of designing and implementation methods, all parts of algorithms is completed in Verilog HDL.
3.The whole system is functional and timing simulated in both ModelSim and Quartus II environments, and implemented in FPGA hardware platform.
4.According to ITU-G.168, this echo canceller get kinds of testing. All the testing achieve desire.
传统回波抵消器主要是基于通用DSP处理器实现的，这种回波抵消器在系统实时性要求不高的场合能很好的满足回波抵消的性能要求，但是在实时性要求较高的场合，其处理速度等性能方面已经不能满足系统高速、实时的需要。现代大容量、高速度的FPGA的出现，克服了上诉方案的诸多不足。用FPGA来实现数字信号处理可以很好地解决并行性和速度问题，且其灵活的可配置特性使得FPGA构成的DSP系统非常易于修改、测试和硬件升级。
本文研究目标是如何在FPGA芯片上实现回波抵消器，完成的主要工作有：
(1)深入研究了回波抵消器各模块算法，包括自适应滤波算法、远端检测算法、双讲检测算法、NLP算法、舒适噪声产生算法，并实现了这些算法的C程序。
(2)深入研究了回波抵消器基于FPGA的设计流程与实现方法，并利用硬件描述语言Verilog HDL实现了各部分算法。
(3)在QuartusⅡ和ModelSim仿真环境下对该系统进行模块级和系统级的功能仿真、时序仿真和验证。并在FPGA硬件平台上实现了该系统。
(4)根据ITU-T G.168的标准和建议，对设计进行了大量的主、客测试，各项测试结果均达到或优于G.168的要求。
In system such as handfree telephone, wireless production , IP telephone , ATM speech service, telephone conference and so on echo cancellation theory has its important application. The solution of echo canceller is different in some way. This paper is focused on electrics echo canceller in PSTN. Electrics echo is produced because impedence is unsuited when speech signal transmitted in PSTN.
Echo canceller is usually implemented on DSP processor.Such echo canceller can meet performance of echo cancellation on the occasion that has lower request of real-time quality. But when the request of real-time is high, the performance such as processing speed can't meet real-time realization. FPGA which has large capacity and high speed overcome the deficiencies as before mentioned. Using FPGA to implement digital signals processing can resolve the problem about parallel and speed. The characteristic of nimble disposition make the system easier to amend, test and promote.
In this thesis, Echo canceller is implemented on FPGA. The main accomplished task of this theis concludes the following parts:
1 .Researched all modules of adaptive echo canceller include adaptive filter, far detector, double talk detector, NLP, comfort noise generator, and then implemented using C language.
2. Researched flow of designing and implementation methods, all parts of algorithms is completed in Verilog HDL.
3.The whole system is functional and timing simulated in both ModelSim and Quartus II environments, and implemented in FPGA hardware platform.
4.According to ITU-G.168, this echo canceller get kinds of testing. All the testing achieve desire.
引文
[1] Kazuo Murano. Echo cancellation and applications. IEEE Communications Magazine, 1990, 8(2): 49-55.
[2] D Messerschmitt. Echo cancellation in speech and date transmission. IEEE Journal On Selected Areas In Communications 1984, 9 (2): 283-297.
[3] Trevor N Yensen, Rafik A Goubran and Ioannis Lambadaris. Synthetic stereo acoustic echo cancellation structure for multiple participant VoIP conferences. IEEE Transaction on Speech and Audio Processing, 2001, 9 (2): 168-173.
[4] 覃景繁，韦岗，欧阳景正．回波消除理论进展及其应用．电路与系统学报，1998，3(3)：73-80．
[5] ITU-T Recommendation G.168.Echo Cancellers, 2000.
[6] Simon Haykjn．自适应滤波器原理．北京：电子工业出版社，2003．
[7] 谢胜利，何昭水，高鹰．信号处理的自适应理论．北京：科学出版社，2006．
[8] 赵春晖，张朝梓，李刚．自适应信号处理．哈尔滨：哈尔滨工程大学出版社，2005．
[9] 何振亚．自适应信号处理．北京：科学出版社，2002．
[10] 沈福民．自适应信号处理．西安：西安电子科技大学出版社，2001．
[11] D T M Slock. On the convergence behavior of the LMS and the normalized LMS algorithm. IEEE Transactions on Signal Processing, 1993, 41 (9): 2811-2825.
[12] J M Cioffi, T Kailath. Fast recursive least squares transversal filters for adaptive filtering. IEEE Transaction on Acoustics, Speech and Signal Processing, 1984, 32(2):304-337.
[13] 张贤达，保净．通信信号处理．北京：国防工业出版社，2002．
[14] J Benesty, D R Morgan and J H Cho. A new class of double-talk detector based on cross-corelation. IEEE Transactions on Speech and Audio Signal Processing, 2000, 8(3): 168-173.
[15] H Ye and B X Xu. A new double-talk detection algorithm based on orthogonality theorem. IEEE Transactions on Communication, 1991, 39(3): 1542-1545.
[16] 王炳锡．语音编码．西安：西安电子科技大学出版社，2002．
[17] Ravi N Banavar, Amit A Kalele. Mixed Norm Performance Measure for the Design of Mnltirate Filterbanks. IEEE Transactions on Signal Processing, 2001, 49(2):354-359.
[18] 袁江南．自适应回波抵消器的算法与MATLAB仿真．电子学报，2003，3(2)：53-55．
[19] Bernard Mulgrew. Orthonormal functions for nonlinear signal processing and adaptive filtering. ICASSP, 1993, 3(2):09-512.
[20] 任晓东，文博．CPLD／FPGA高级应用开发指南．北京：电子工业出版社，2003．
[21] 于枫，张丽英，廖宗建．ALTERA可编程逻辑器件．北京：科学出版社，2004．
[22] 潘松，黄继业．EDA技术与VHDL．北京：清华大学出版社，2005．
[23] 郑亚民，董晓舟．可编程逻辑器件开发软件Quartus Ⅱ．北京：国防工业出版社，2006．
[24] 杨恒，李爱国，王辉等．FPGA／CPLD最新实用技术指南．北京：清华大学出版社，2005．
[25] 蒋璇，臧春华．数字系统设计与PLD应用技术．北京：电子工业出版社，2001．
[26] 徐志军．CPLD／FPGA的开发与应用．北京：电子工业出版社，2002．
[27] 王冠．面向CPLD／FPGA的Verilog设计．北京：机械工业出版社，2007．
[28] 张明．Verilog HDL实用教程．成都：电子科技大学出版社，1999．
[29] 王金明．数字系统设计与Verilog HDL．北京：电子工业出版社，2005．
[30] 吴继华，于诚．Altera FPGA／CPLD设计(基础篇)．北京：人民邮电出版社，2005．
[31] 夏宇闻．Verilog数字系统设计教程．北京：北京航空航天大学出版社，2003．
[32] 吴继华，王诚．Altera FPGA／CPLD设计(高级篇)．北京：人民邮电出版社，2005．
[33] 贝斯．数字信号处理的FPGA实现．北京：清华大学出版社，2003．
[34] 毕占坤，吴伶锡．FIR数字滤波器分布式算法的原理及FPGA实现．电子技术应用，2004，8(7)：53-55．
[35] 金昕，黄捷，刘韬．一种用FPGA实现的FIR滤波器结构．电路与系统学报，1999，29(1)：58-61．
[36] ShoushengHe, MatsTorkelson. FPGA implementation of FIR filters using pipelined bit-serial canonical signal digit multipliers. IEEE Custom Integrated Circuit Conference, 1994, 7(3): 125-137.
[37] E Ahmed and J Rose. The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Field Programmable Gate Arrays, 2000, 9 (3): 3-12.
[38] C S Burrus. Digital filter structure described by distributed arithmetic. IEEE Transactions on Circuits and System, 6 (8) :12-26.
[39] 陆海峰．实现FPGA与PC的串行通信．电子设计应用，2004，2(8)：121-155．
[2] D Messerschmitt. Echo cancellation in speech and date transmission. IEEE Journal On Selected Areas In Communications 1984, 9 (2): 283-297.
[3] Trevor N Yensen, Rafik A Goubran and Ioannis Lambadaris. Synthetic stereo acoustic echo cancellation structure for multiple participant VoIP conferences. IEEE Transaction on Speech and Audio Processing, 2001, 9 (2): 168-173.
[4] 覃景繁，韦岗，欧阳景正．回波消除理论进展及其应用．电路与系统学报，1998，3(3)：73-80．
[5] ITU-T Recommendation G.168.Echo Cancellers, 2000.
[6] Simon Haykjn．自适应滤波器原理．北京：电子工业出版社，2003．
[7] 谢胜利，何昭水，高鹰．信号处理的自适应理论．北京：科学出版社，2006．
[8] 赵春晖，张朝梓，李刚．自适应信号处理．哈尔滨：哈尔滨工程大学出版社，2005．
[9] 何振亚．自适应信号处理．北京：科学出版社，2002．
[10] 沈福民．自适应信号处理．西安：西安电子科技大学出版社，2001．
[11] D T M Slock. On the convergence behavior of the LMS and the normalized LMS algorithm. IEEE Transactions on Signal Processing, 1993, 41 (9): 2811-2825.
[12] J M Cioffi, T Kailath. Fast recursive least squares transversal filters for adaptive filtering. IEEE Transaction on Acoustics, Speech and Signal Processing, 1984, 32(2):304-337.
[13] 张贤达，保净．通信信号处理．北京：国防工业出版社，2002．
[14] J Benesty, D R Morgan and J H Cho. A new class of double-talk detector based on cross-corelation. IEEE Transactions on Speech and Audio Signal Processing, 2000, 8(3): 168-173.
[15] H Ye and B X Xu. A new double-talk detection algorithm based on orthogonality theorem. IEEE Transactions on Communication, 1991, 39(3): 1542-1545.
[16] 王炳锡．语音编码．西安：西安电子科技大学出版社，2002．
[17] Ravi N Banavar, Amit A Kalele. Mixed Norm Performance Measure for the Design of Mnltirate Filterbanks. IEEE Transactions on Signal Processing, 2001, 49(2):354-359.
[18] 袁江南．自适应回波抵消器的算法与MATLAB仿真．电子学报，2003，3(2)：53-55．
[19] Bernard Mulgrew. Orthonormal functions for nonlinear signal processing and adaptive filtering. ICASSP, 1993, 3(2):09-512.
[20] 任晓东，文博．CPLD／FPGA高级应用开发指南．北京：电子工业出版社，2003．
[21] 于枫，张丽英，廖宗建．ALTERA可编程逻辑器件．北京：科学出版社，2004．
[22] 潘松，黄继业．EDA技术与VHDL．北京：清华大学出版社，2005．
[23] 郑亚民，董晓舟．可编程逻辑器件开发软件Quartus Ⅱ．北京：国防工业出版社，2006．
[24] 杨恒，李爱国，王辉等．FPGA／CPLD最新实用技术指南．北京：清华大学出版社，2005．
[25] 蒋璇，臧春华．数字系统设计与PLD应用技术．北京：电子工业出版社，2001．
[26] 徐志军．CPLD／FPGA的开发与应用．北京：电子工业出版社，2002．
[27] 王冠．面向CPLD／FPGA的Verilog设计．北京：机械工业出版社，2007．
[28] 张明．Verilog HDL实用教程．成都：电子科技大学出版社，1999．
[29] 王金明．数字系统设计与Verilog HDL．北京：电子工业出版社，2005．
[30] 吴继华，于诚．Altera FPGA／CPLD设计(基础篇)．北京：人民邮电出版社，2005．
[31] 夏宇闻．Verilog数字系统设计教程．北京：北京航空航天大学出版社，2003．
[32] 吴继华，王诚．Altera FPGA／CPLD设计(高级篇)．北京：人民邮电出版社，2005．
[33] 贝斯．数字信号处理的FPGA实现．北京：清华大学出版社，2003．
[34] 毕占坤，吴伶锡．FIR数字滤波器分布式算法的原理及FPGA实现．电子技术应用，2004，8(7)：53-55．
[35] 金昕，黄捷，刘韬．一种用FPGA实现的FIR滤波器结构．电路与系统学报，1999，29(1)：58-61．
[36] ShoushengHe, MatsTorkelson. FPGA implementation of FIR filters using pipelined bit-serial canonical signal digit multipliers. IEEE Custom Integrated Circuit Conference, 1994, 7(3): 125-137.
[37] E Ahmed and J Rose. The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Field Programmable Gate Arrays, 2000, 9 (3): 3-12.
[38] C S Burrus. Digital filter structure described by distributed arithmetic. IEEE Transactions on Circuits and System, 6 (8) :12-26.
[39] 陆海峰．实现FPGA与PC的串行通信．电子设计应用，2004，2(8)：121-155．