回波抵消器算法研究及其FPGA实现
摘要
回波抵消器是消除通信系统中电学回波和声学回波的功能单元。回波抵消器在免提电话、无线产品、IP电话、ATM语音服务和电话会议等系统中,都有着重要的应用。回波抵消理论及应用一直是国际上研究的热门课题之一。
在不同应用场合对回波抵消器的要求并不完全相同。本文主要研究应用于电话系统中的电回波抵消器。电回波是由于语音信号在电话网中传输时由于阻抗不匹配而产生的。电回波抵消器可以生成一个模拟的回波信号,再从近端信号中减掉该模拟信号,从而实现电回波的抵消。
传统回波抵消器主要是基于通用DSP处理器实现的,这种回波抵消器在系统实时性要求不高的场合能满足回波抵消的性能要求,但是在实时性要求较高的场合,其处理速度等性能方面已经不能满足系统高速、实时的需要。现代大容量、高速度的FPGA的出现,克服了上述方案的诸多不足。用FPGA来实现数字信号处理可以很好地解决并行性和速度问题,且其灵活的可配置特性使得FPGA构成的DSP系统非常易于修改,测试和硬件升级。
本文的目的是在FPGA芯片上实现回波抵消器,在整个系统的实现过程中,主要完成的工作有:
(1)深入研究了回波抵消器各模块算法,包括自适应滤波算法、远端检测算法、双讲检测算法,并实现了这些算法的C程序。
(2)深入研究了回波抵消器基于FPGA的设计流程与实现方法,并利用硬件描述语言'Verilog HDL实现了各部分算法。
(3)在QuartusⅡ集成环境下对该系统进行模块级和系统级的功能仿真、时序仿真和验证,并在FPGA硬件平台上实现了该系统。
(4)根据ITU-T G.168的标准和建议,对设计进行了客观测试。
Echo Canceller is a function cell which cancels electric echo or acoustic echo in communication systems. In many systems, such as handfree telephone, wireless production , IP telephone, ATM speech service, telephone conference and so on, echo cancellation technique has its important application.
For the various solution of echo canceller are different, this thesis is focused on electric echo canceller applications in PSTN. Electric echo is caused by the impedence mismatch during the transmission in PSTN. Electric echo canceller can synthesize a replica of the echo and subtract it from the real echo according to reference signal.
Echo canceller is usually implemented on DSP processor.Such echo canceller can meet performance of echo cancellation on the occasion which requires low real-time quality. But when the request of real-time is high, the performance such as processing speed can't meet real-time realization. FPGA with large capacity and high speed can overcome the deficiencies as mentioned above. Using FPGA to implement digital signals processing can resolve the problem about parallel and speed. The characteristic of nimble disposition make the system easier to modify, test and promote.
In this thesis, Echo Canceller is implemented on FPGA. The main accomplished task of this theis concludes the following parts:
(1). Research_all modules of adaptive echo canceller including adaptive filter, far detector, double talk detector, and then implement them using C language.
(2). Research flow of designing and implementation methods, all parts of algorithms is completed in Verilog HDL.
(3). The whole system is functional and timing simulated in QuartusⅡenvironments, and implemented in FPGA hardware platform.
(4). According to ITU-G.168, this echo canceller gets kinds of testing. All the testing achieve desirable requirement.
在不同应用场合对回波抵消器的要求并不完全相同。本文主要研究应用于电话系统中的电回波抵消器。电回波是由于语音信号在电话网中传输时由于阻抗不匹配而产生的。电回波抵消器可以生成一个模拟的回波信号,再从近端信号中减掉该模拟信号,从而实现电回波的抵消。
传统回波抵消器主要是基于通用DSP处理器实现的,这种回波抵消器在系统实时性要求不高的场合能满足回波抵消的性能要求,但是在实时性要求较高的场合,其处理速度等性能方面已经不能满足系统高速、实时的需要。现代大容量、高速度的FPGA的出现,克服了上述方案的诸多不足。用FPGA来实现数字信号处理可以很好地解决并行性和速度问题,且其灵活的可配置特性使得FPGA构成的DSP系统非常易于修改,测试和硬件升级。
本文的目的是在FPGA芯片上实现回波抵消器,在整个系统的实现过程中,主要完成的工作有:
(1)深入研究了回波抵消器各模块算法,包括自适应滤波算法、远端检测算法、双讲检测算法,并实现了这些算法的C程序。
(2)深入研究了回波抵消器基于FPGA的设计流程与实现方法,并利用硬件描述语言'Verilog HDL实现了各部分算法。
(3)在QuartusⅡ集成环境下对该系统进行模块级和系统级的功能仿真、时序仿真和验证,并在FPGA硬件平台上实现了该系统。
(4)根据ITU-T G.168的标准和建议,对设计进行了客观测试。
Echo Canceller is a function cell which cancels electric echo or acoustic echo in communication systems. In many systems, such as handfree telephone, wireless production , IP telephone, ATM speech service, telephone conference and so on, echo cancellation technique has its important application.
For the various solution of echo canceller are different, this thesis is focused on electric echo canceller applications in PSTN. Electric echo is caused by the impedence mismatch during the transmission in PSTN. Electric echo canceller can synthesize a replica of the echo and subtract it from the real echo according to reference signal.
Echo canceller is usually implemented on DSP processor.Such echo canceller can meet performance of echo cancellation on the occasion which requires low real-time quality. But when the request of real-time is high, the performance such as processing speed can't meet real-time realization. FPGA with large capacity and high speed can overcome the deficiencies as mentioned above. Using FPGA to implement digital signals processing can resolve the problem about parallel and speed. The characteristic of nimble disposition make the system easier to modify, test and promote.
In this thesis, Echo Canceller is implemented on FPGA. The main accomplished task of this theis concludes the following parts:
(1). Research_all modules of adaptive echo canceller including adaptive filter, far detector, double talk detector, and then implement them using C language.
(2). Research flow of designing and implementation methods, all parts of algorithms is completed in Verilog HDL.
(3). The whole system is functional and timing simulated in QuartusⅡenvironments, and implemented in FPGA hardware platform.
(4). According to ITU-G.168, this echo canceller gets kinds of testing. All the testing achieve desirable requirement.
引文
[1]David G.Messerschmitt.Echo cancellation in speech and data transmission.IEEE Journal on Selected Areas in Communication.1984,2(2):283-286.
[2]覃景繁,韦岗,欧阳景正.回波消除理论进展及其应用.电路与系统学报.1998,3(3):73-80.
[3]ITU-T Recommendation G.168,Echo Cancellers,2000.
[4]齐海兵.自适应滤波器算法设计及其FPGA实现的研究与应用:(硕士学位论文).长沙:中南大学。2006.
[5]Paulo S.R.Diniz.自适应滤波算法与实现(第二版).北京:电子工业出版社.2004.
[6]王宏禹,邱天爽.自适应噪声抵消与时间延迟估计.大连:大连理工大学出版社,1999.
[7]Simon Haykin.自适应滤波器原理.北京:电子工业出版社,2003.
[8]Saul B.Gelfand,Yongbin Wei,James V.Krogmeier.The stability of variable step-size LMS algorithms.IEEE Transactions on Signal Processing,1999,47(12):3277-3288.
[9]Zhao Shengkui,Man Zhihong,Khoo Suiyang.Modified LMS and NLMS algorithms with a new variable step size.ICARCV' 06.9th International Control,Automation,Robotics and Vision,2006:1-6.
[10]孙娟,王俊,刘斌.改进的NLMS算法及其在自适应预测中的应用.中国电子科学研究员学报.2007,2(5):507-512.
[11]S.C.Chan,Y.Zhou.On the convergence analysis of the normalized LMS and the normalized least mean m-estimate algorithms.IEEE International Symposium on Signal Processing and Information Technology,2007:1048-1053.
[12]王永德,王春霞.一种改进的快速LMS用Newton算法及其在声回波对消中的应用.电子学报,2000,25(2):97-100.
[13]GuoZhu Long,FuYun Ling,John G.Proakis.The LMS algorithm with delayed coefficient adaptation.IEEE Transactions on Acoustics.Speech and Signal Processing,1989,37(9):1397-1405.
[14]R.Haimi-Cohen,H.Herzberg,Y.Belery.Delayed adaptive LMS filtering:current result.IEEE Transactions on Signal Processing,1990,2(9):1273-1276.
[15]陈文博,耿相铭,马伟敏.高速自适应DLMS算法及其硬件实现.信息技术.1982,10:59-62.
[16]Xinyi Wang,Tingzhi Shen,Weijiang Wang.An approach for echo cancellation system based on improved NLMS algorithm.International Conference on Wireless Communications,Networking and Mobile Computing,2007:2853-2856.
[17]曹斌芳,何怡则,李建奇等.3种改进型LMS算法在噪声抵消中的仿真比较.电声技术,2007.31(9):66-69.
[18]Jianfeng Liu.A novel adaptation scheme in the NLMS algorithm for echo cancellation.IEEE Signal Processing Letters;,2001.8(1):20-22.
[19]Jianfeng Liu.Efficient and robust cancellation of echoes with long echo path delay.IEEE Transactions on Communications,2004,52(8):1288-1291.
[20]Kazuo ochiai,Takashi Araseki,Takashi Ogihara.Echo canceler with two echo path models.IEEE Transactions on Communications,1977,25(6):589-595.
[21]H.Haghshenas,M.MalmirChegini.A novel double-talk detector based on adaptive estimation of near-end power.IEEE International Conference on Teiecommunica- tions and Malaysia International Conference on Communications,2007:446-449.
[22]Jun H.Cho,Dennis R.Morgan,Jacob Benesty.An objective technique for evaluating doubletalk detectors in acoustic echo cancelers.IEEE Transactions on Speech and Audio Processing Communication.1999,7(6):718-724.
[23]夏宇闻.Verilog数字系统设计教程.北京:北京航空航天大学出版社,2003.
[24]任晓东,文博.CPLD/FPGA高级应用开发指南.北京:电子工业出版社,2003.
[25]Altera Corporation.Data sheet:Stratix EP1S25DSP development board,2004.
[26]郑亚民,董晓舟.可编程逻辑器件开发软件Quartus Ⅱ.北京:国防工业出版社,2006.
[27]吴继华,王诚.Altera FPGA/CPLD设计(基础篇).北京:人民邮电出版社,2005.
[28]褚振勇,翁木云.FPGA设计及应用.西安:西安电子科技大学出版社,2002.
[29]田耘,徐文波,张延伟等.无线通信FPGA设计.北京:电子工业出版社,2008.
[30]王冠.面向CPLD/FPGA的Verilog设计.北京:机械工业出版社,2007.
[31]毕占坤,吴伶锡.FIR数字滤波器分布式算法的原理及FPGA实现.电子技术应用,2004,7:61-66.
[32]黄建亮.基于FPGA的自适应滤波器设计与实现:(硕士学位论文).西安:西交电子科技大学,2006.
[33]雷震霖.空间图像CCSDS压缩算法研究与FPGA实现:(硕士学位论文).大连:大连理工大学,2008.
[34]A.N.Tarakanov,A.L.Moseev.Analysis of echo canceller work in double talk mode.The IEEE-Siberian Conference on Control and Communications,2003:40-42.
[2]覃景繁,韦岗,欧阳景正.回波消除理论进展及其应用.电路与系统学报.1998,3(3):73-80.
[3]ITU-T Recommendation G.168,Echo Cancellers,2000.
[4]齐海兵.自适应滤波器算法设计及其FPGA实现的研究与应用:(硕士学位论文).长沙:中南大学。2006.
[5]Paulo S.R.Diniz.自适应滤波算法与实现(第二版).北京:电子工业出版社.2004.
[6]王宏禹,邱天爽.自适应噪声抵消与时间延迟估计.大连:大连理工大学出版社,1999.
[7]Simon Haykin.自适应滤波器原理.北京:电子工业出版社,2003.
[8]Saul B.Gelfand,Yongbin Wei,James V.Krogmeier.The stability of variable step-size LMS algorithms.IEEE Transactions on Signal Processing,1999,47(12):3277-3288.
[9]Zhao Shengkui,Man Zhihong,Khoo Suiyang.Modified LMS and NLMS algorithms with a new variable step size.ICARCV' 06.9th International Control,Automation,Robotics and Vision,2006:1-6.
[10]孙娟,王俊,刘斌.改进的NLMS算法及其在自适应预测中的应用.中国电子科学研究员学报.2007,2(5):507-512.
[11]S.C.Chan,Y.Zhou.On the convergence analysis of the normalized LMS and the normalized least mean m-estimate algorithms.IEEE International Symposium on Signal Processing and Information Technology,2007:1048-1053.
[12]王永德,王春霞.一种改进的快速LMS用Newton算法及其在声回波对消中的应用.电子学报,2000,25(2):97-100.
[13]GuoZhu Long,FuYun Ling,John G.Proakis.The LMS algorithm with delayed coefficient adaptation.IEEE Transactions on Acoustics.Speech and Signal Processing,1989,37(9):1397-1405.
[14]R.Haimi-Cohen,H.Herzberg,Y.Belery.Delayed adaptive LMS filtering:current result.IEEE Transactions on Signal Processing,1990,2(9):1273-1276.
[15]陈文博,耿相铭,马伟敏.高速自适应DLMS算法及其硬件实现.信息技术.1982,10:59-62.
[16]Xinyi Wang,Tingzhi Shen,Weijiang Wang.An approach for echo cancellation system based on improved NLMS algorithm.International Conference on Wireless Communications,Networking and Mobile Computing,2007:2853-2856.
[17]曹斌芳,何怡则,李建奇等.3种改进型LMS算法在噪声抵消中的仿真比较.电声技术,2007.31(9):66-69.
[18]Jianfeng Liu.A novel adaptation scheme in the NLMS algorithm for echo cancellation.IEEE Signal Processing Letters;,2001.8(1):20-22.
[19]Jianfeng Liu.Efficient and robust cancellation of echoes with long echo path delay.IEEE Transactions on Communications,2004,52(8):1288-1291.
[20]Kazuo ochiai,Takashi Araseki,Takashi Ogihara.Echo canceler with two echo path models.IEEE Transactions on Communications,1977,25(6):589-595.
[21]H.Haghshenas,M.MalmirChegini.A novel double-talk detector based on adaptive estimation of near-end power.IEEE International Conference on Teiecommunica- tions and Malaysia International Conference on Communications,2007:446-449.
[22]Jun H.Cho,Dennis R.Morgan,Jacob Benesty.An objective technique for evaluating doubletalk detectors in acoustic echo cancelers.IEEE Transactions on Speech and Audio Processing Communication.1999,7(6):718-724.
[23]夏宇闻.Verilog数字系统设计教程.北京:北京航空航天大学出版社,2003.
[24]任晓东,文博.CPLD/FPGA高级应用开发指南.北京:电子工业出版社,2003.
[25]Altera Corporation.Data sheet:Stratix EP1S25DSP development board,2004.
[26]郑亚民,董晓舟.可编程逻辑器件开发软件Quartus Ⅱ.北京:国防工业出版社,2006.
[27]吴继华,王诚.Altera FPGA/CPLD设计(基础篇).北京:人民邮电出版社,2005.
[28]褚振勇,翁木云.FPGA设计及应用.西安:西安电子科技大学出版社,2002.
[29]田耘,徐文波,张延伟等.无线通信FPGA设计.北京:电子工业出版社,2008.
[30]王冠.面向CPLD/FPGA的Verilog设计.北京:机械工业出版社,2007.
[31]毕占坤,吴伶锡.FIR数字滤波器分布式算法的原理及FPGA实现.电子技术应用,2004,7:61-66.
[32]黄建亮.基于FPGA的自适应滤波器设计与实现:(硕士学位论文).西安:西交电子科技大学,2006.
[33]雷震霖.空间图像CCSDS压缩算法研究与FPGA实现:(硕士学位论文).大连:大连理工大学,2008.
[34]A.N.Tarakanov,A.L.Moseev.Analysis of echo canceller work in double talk mode.The IEEE-Siberian Conference on Control and Communications,2003:40-42.