基于FPGA的回波抵消算法研究与实现
摘要
回波抵消器作为消除通信系统中电学回波和声学回波的功能单元,在免提电话、无线产品、IP电话和电话会议等系统中有着非常重要的应用。
传统回波抵消器主要是基于通用DSP处理器实现的。这种回波抵消器在系统实时性要求不高的场合能很好的满足回波抵消性能要求,但是在实时性要求较高的场合,其处理速度等性能方面已经不能满足系统需求。现代大容量、高速度的FPGA的出现,克服了上述方案的诸多不足。基于FPGA来实现数字信号处理可以很好地解决并行性和速度问题,且其灵活的可配置特性使得FPGA构成的DSP系统易于修改、测试和硬件升级。
本文主要针对电话系统中的电回波进行研究,设计自适应回波消除器并基于FPGA平台进行实现。在整个回波抵消系统的实现过程中,本文主要做了如下几方面工作:
首先,研究并完成了回波消除器的各个功能模块。各功能模块算法中,重点分析了LMS、NLMS、DLMS等运算量较小而收敛速度和稳态残留回波又能满足要求的几类自适应算法。
其次,本文介绍了Altera公司的StratixEP1S25DSP开发板以及所使用的硬件描述语言Verilog HDL。结合QuartusⅡ集成开发环境,描述了基于FPGA的设计流程和实现方法。
然后,本文在给出总体设计方案后,利用硬件描述语言Verilog HDL在FPGA硬件平台上实现了各模块算法。在QuartusⅡ集成开发环境下对回波抵消系统进行模块级和系统级的功能仿真、时序仿真和验证后,给出了各功能模块的仿真结果和实现性能。
最后,根据ITU-T G.168协议所规定的要求,对所设计的回波抵消器进行了各项性能测试。
Echo canceller, a working cell that cancels electrics echo or acoustics echo in communication systems, has important application in systems such as hand-free telephone, wireless product, IP telephone, audio conference and so on.
Traditional echo canceller is usually implemented on general DSP processor. Such echo canceller can satisfy requirement of echo cancellation performance on this condition that has lower request of real-time quality. But when the request of real-time is high, the performance such as processing speed can't meet the requirement of real-time processing. FPGA which is bulky and high-performance makes up for the deficiencies as mentioned above. Implementing digital signal processing based on FPGA can resolve problems of both parallel and speed. The characteristic of flexible reconfiguration makes that DSP system easier to implement, test and upgrade.
This thesis is focused on electrics echo canceller in PSTN. An applied adaptive echo canceller based on FPGA platform is designed and implemented. During the process of implementing the whole echo canceller system, The following research works are carried out.
Firstly, all models of the echo canceller are thoroughly researched and completed using C language. Integrated with application, we put more emphasis on the adaptive filtering algorithms including LMS, NLMS, DLMS, which can get a tradeoff between the convergence performance and the computational complexity.
Secondly, the Altera StratixEP1S25DSP development board and Verilog Hardware Description Language are introduced. Combined with the integrated developing environment Quartus II, the flow of FPGA design is also described.
Finally, after the total design scheme is given, all models are implemented on FPGA platform using Verilog Hardware Description Language. The whole echo cancellation system is functional and timing simulated in Quartus II environment. Simulation results and relevant performance are given too.
传统回波抵消器主要是基于通用DSP处理器实现的。这种回波抵消器在系统实时性要求不高的场合能很好的满足回波抵消性能要求,但是在实时性要求较高的场合,其处理速度等性能方面已经不能满足系统需求。现代大容量、高速度的FPGA的出现,克服了上述方案的诸多不足。基于FPGA来实现数字信号处理可以很好地解决并行性和速度问题,且其灵活的可配置特性使得FPGA构成的DSP系统易于修改、测试和硬件升级。
本文主要针对电话系统中的电回波进行研究,设计自适应回波消除器并基于FPGA平台进行实现。在整个回波抵消系统的实现过程中,本文主要做了如下几方面工作:
首先,研究并完成了回波消除器的各个功能模块。各功能模块算法中,重点分析了LMS、NLMS、DLMS等运算量较小而收敛速度和稳态残留回波又能满足要求的几类自适应算法。
其次,本文介绍了Altera公司的StratixEP1S25DSP开发板以及所使用的硬件描述语言Verilog HDL。结合QuartusⅡ集成开发环境,描述了基于FPGA的设计流程和实现方法。
然后,本文在给出总体设计方案后,利用硬件描述语言Verilog HDL在FPGA硬件平台上实现了各模块算法。在QuartusⅡ集成开发环境下对回波抵消系统进行模块级和系统级的功能仿真、时序仿真和验证后,给出了各功能模块的仿真结果和实现性能。
最后,根据ITU-T G.168协议所规定的要求,对所设计的回波抵消器进行了各项性能测试。
Echo canceller, a working cell that cancels electrics echo or acoustics echo in communication systems, has important application in systems such as hand-free telephone, wireless product, IP telephone, audio conference and so on.
Traditional echo canceller is usually implemented on general DSP processor. Such echo canceller can satisfy requirement of echo cancellation performance on this condition that has lower request of real-time quality. But when the request of real-time is high, the performance such as processing speed can't meet the requirement of real-time processing. FPGA which is bulky and high-performance makes up for the deficiencies as mentioned above. Implementing digital signal processing based on FPGA can resolve problems of both parallel and speed. The characteristic of flexible reconfiguration makes that DSP system easier to implement, test and upgrade.
This thesis is focused on electrics echo canceller in PSTN. An applied adaptive echo canceller based on FPGA platform is designed and implemented. During the process of implementing the whole echo canceller system, The following research works are carried out.
Firstly, all models of the echo canceller are thoroughly researched and completed using C language. Integrated with application, we put more emphasis on the adaptive filtering algorithms including LMS, NLMS, DLMS, which can get a tradeoff between the convergence performance and the computational complexity.
Secondly, the Altera StratixEP1S25DSP development board and Verilog Hardware Description Language are introduced. Combined with the integrated developing environment Quartus II, the flow of FPGA design is also described.
Finally, after the total design scheme is given, all models are implemented on FPGA platform using Verilog Hardware Description Language. The whole echo cancellation system is functional and timing simulated in Quartus II environment. Simulation results and relevant performance are given too.
引文
[1]D Messerschmitt.Echo cancellation in speech and data transmission.IEEE Journal On Selected Areas In Comunications,1984,9(2):283-297.
[2]ITU-T Recommendation G.164.Echo suppressors,1988.
[3]覃景繁,韦岗,欧阳景正.回波消除理论进展及其应用.电路与系统学报,1998,3(3):73-80.
[4]田耘.徐文波,张延伟等.无线通信FPGA设计.北京:电子工业出版社,2008.2.
[5]迟男,刘杰.浮点DSP实现自适应滤波的研究.北方交通大学学报,2000,24(5):67-70.
[6]陈兴文,李敏,刘燕.基于DSP的自适应滤波器设计.大连民族学院学报,2005,7(3):22-24.
[7]宋杭宾.姚庆栋,归琳.TMS320C3XDSP实现自适应滤波的算法分析.浙江大学学报(工学报),2000,34(5):483-488.
[8]李梦醒,秦姣华.Simulink仿真技术在数字滤波器设计中的应用[J].湖南城市学院学报,2005,14(3):66-68.
[9]贺宽,黄涛.基于Matlab的自适应滤波器设计.武汉理工大学学报,2008,30(1):70-73.
[10]Paulo S.R.Diniz.自适应滤波算法与实现.北京:电子工业出版社,2004.7.
[11]A.Jalali,Sh.G.Boroujeny,M.Eshghi.Design and implementation of a fast active noise control system on FPGA.Mediterranean Conference on Control & Automation,2007:1-4.
[12]何振亚.自适应信号处理.北京:科学出版社,2002.
[13]沈福民.自适应信号处理.西安:西安电子科技大学出版社,2001.
[14]齐海兵.基于FPGA的横向LMS算法的实现.国外电子元器件,2007,(1):31-34.
[15]Zhao Shengkui,Man Zhihong,Khoo Suiyang.Modified LMS and NLMS Algorithms with a New Variable Step Size.ICARCV'06.9th International Conference on Control,Automation,Robotics and Vision,2006:1-6.
[15]S.C.Chan,Y.Zhou.On the Convergence Analysis of the Normalized LMS and the Normalized Least Mean M-Estimate Algorithms.IEEE International Symposium on Signal Processing and Information Technology,2007:1048-1053.
[17]高媛,李成海.新的变步长LMS算法及其在自适应噪声对消中的应用.沈阳航空工业学院学报,2007,24(4):83-85.
[18]Jianfeng Liu.A novel adaptation scheme in the NLMS algorithm for echo cancellation.Signal IEEE Processing Letters,2001,8(1):20-22.
[19]Yen-Tai Lai,Chi-Chou Kao,Hao-Jan Chen.Design and implementation of an adaptive FIR filter based on delayed error LMS algorithm.1999 IEEE Workshop on Signal Processing Systems,1999:704-712.
[20]陈文博,耿相铭,马伟敏.高速自适应DLMS算法及其硬件实现.信息技术,2007,10:59-60.
[21]K.R.Santha,V.Vaidehi.A new pipelined architecture for the DLMSalgorithm.IEEE Indicon 2005 conference,Chennai,India,2005.
[22]GUO LONG,FUYUN LING,JOHN G.PROAKIS.The LMS Algorithm with Delayed Coefficient Adaptation.IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING,1989,37(9):1397:1405.
[23]张贤达,保铮.通信信号处理.北京:国防工业出版社,2002.
[24]ITU-T Recommendation G.168.Echo Cancellers,2000.
[25]Jun H.Cho,Dennis R.Morgan,Jacob Benesty.An objective technique for evaluating doubletalk detectors in Acoustic Echo cancellers[J].IEEE Transactions on Speech and Audio Processing,1997,7(6):718-724.
[26]H Ye and B X xu.A new double-talk detection algorithm based on thogonality theorem.IEEE Transactions on Communication,1991,39(3):1542-1545.
[27]J Benesty,D R Morgan and J H Cho.A new class of double-talk detector based oncross-corelation.IEEE Transactions on Speech and Aution Signal Processing,2000,8(3):168-173.
[28]H.Haghshenas,M.MalmirChegini.A novel double-talk detector based on adaptive estimation of near-end power.IEEE International Conference on Telecommunications and Malaysia International Conference on Communications,2007:446 - 449.
[29]A.N.Tarakanov,A.L.Moseev.Analysis of echo canceller work in double talk mode.The IEEE-Siberian Conference on Control and Communications,2003:40-42.
[30]夏宇闻.Verilog数字系统设计教程.北京:北京航空航天大学出版社,2003.
[31]于枫,张丽英,廖宗建.ALTERA可编程逻辑器件.北京:科学出版社,2004.
[32]杨恒,李爱国,王辉等.FPGA/CPLD最新实用技术指南.北京:清华大学出版社,2005.
[33]蒋璇,臧春华.数字系统设计与PLD应用技术.北京:电子工业出版社.2001.
[34]张明.Verilog HDL实用教程.成都:电子科技大学出版社,1999.
[35]王金明.数字系统设计与Verilog HDL.北京:电子工业出版社,2005.
[36]何健标,王宏远。郭跃登.一种基于FPGA的FIR滤波器实现结构.微电子学与计算机,2008,25(3):47-50.
[37]朱维勇,傅桂生.基于VHDL语言的有限状态机设计方法.计算机技术与应用进展.2004,3(3):702-706.
[2]ITU-T Recommendation G.164.Echo suppressors,1988.
[3]覃景繁,韦岗,欧阳景正.回波消除理论进展及其应用.电路与系统学报,1998,3(3):73-80.
[4]田耘.徐文波,张延伟等.无线通信FPGA设计.北京:电子工业出版社,2008.2.
[5]迟男,刘杰.浮点DSP实现自适应滤波的研究.北方交通大学学报,2000,24(5):67-70.
[6]陈兴文,李敏,刘燕.基于DSP的自适应滤波器设计.大连民族学院学报,2005,7(3):22-24.
[7]宋杭宾.姚庆栋,归琳.TMS320C3XDSP实现自适应滤波的算法分析.浙江大学学报(工学报),2000,34(5):483-488.
[8]李梦醒,秦姣华.Simulink仿真技术在数字滤波器设计中的应用[J].湖南城市学院学报,2005,14(3):66-68.
[9]贺宽,黄涛.基于Matlab的自适应滤波器设计.武汉理工大学学报,2008,30(1):70-73.
[10]Paulo S.R.Diniz.自适应滤波算法与实现.北京:电子工业出版社,2004.7.
[11]A.Jalali,Sh.G.Boroujeny,M.Eshghi.Design and implementation of a fast active noise control system on FPGA.Mediterranean Conference on Control & Automation,2007:1-4.
[12]何振亚.自适应信号处理.北京:科学出版社,2002.
[13]沈福民.自适应信号处理.西安:西安电子科技大学出版社,2001.
[14]齐海兵.基于FPGA的横向LMS算法的实现.国外电子元器件,2007,(1):31-34.
[15]Zhao Shengkui,Man Zhihong,Khoo Suiyang.Modified LMS and NLMS Algorithms with a New Variable Step Size.ICARCV'06.9th International Conference on Control,Automation,Robotics and Vision,2006:1-6.
[15]S.C.Chan,Y.Zhou.On the Convergence Analysis of the Normalized LMS and the Normalized Least Mean M-Estimate Algorithms.IEEE International Symposium on Signal Processing and Information Technology,2007:1048-1053.
[17]高媛,李成海.新的变步长LMS算法及其在自适应噪声对消中的应用.沈阳航空工业学院学报,2007,24(4):83-85.
[18]Jianfeng Liu.A novel adaptation scheme in the NLMS algorithm for echo cancellation.Signal IEEE Processing Letters,2001,8(1):20-22.
[19]Yen-Tai Lai,Chi-Chou Kao,Hao-Jan Chen.Design and implementation of an adaptive FIR filter based on delayed error LMS algorithm.1999 IEEE Workshop on Signal Processing Systems,1999:704-712.
[20]陈文博,耿相铭,马伟敏.高速自适应DLMS算法及其硬件实现.信息技术,2007,10:59-60.
[21]K.R.Santha,V.Vaidehi.A new pipelined architecture for the DLMSalgorithm.IEEE Indicon 2005 conference,Chennai,India,2005.
[22]GUO LONG,FUYUN LING,JOHN G.PROAKIS.The LMS Algorithm with Delayed Coefficient Adaptation.IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING,1989,37(9):1397:1405.
[23]张贤达,保铮.通信信号处理.北京:国防工业出版社,2002.
[24]ITU-T Recommendation G.168.Echo Cancellers,2000.
[25]Jun H.Cho,Dennis R.Morgan,Jacob Benesty.An objective technique for evaluating doubletalk detectors in Acoustic Echo cancellers[J].IEEE Transactions on Speech and Audio Processing,1997,7(6):718-724.
[26]H Ye and B X xu.A new double-talk detection algorithm based on thogonality theorem.IEEE Transactions on Communication,1991,39(3):1542-1545.
[27]J Benesty,D R Morgan and J H Cho.A new class of double-talk detector based oncross-corelation.IEEE Transactions on Speech and Aution Signal Processing,2000,8(3):168-173.
[28]H.Haghshenas,M.MalmirChegini.A novel double-talk detector based on adaptive estimation of near-end power.IEEE International Conference on Telecommunications and Malaysia International Conference on Communications,2007:446 - 449.
[29]A.N.Tarakanov,A.L.Moseev.Analysis of echo canceller work in double talk mode.The IEEE-Siberian Conference on Control and Communications,2003:40-42.
[30]夏宇闻.Verilog数字系统设计教程.北京:北京航空航天大学出版社,2003.
[31]于枫,张丽英,廖宗建.ALTERA可编程逻辑器件.北京:科学出版社,2004.
[32]杨恒,李爱国,王辉等.FPGA/CPLD最新实用技术指南.北京:清华大学出版社,2005.
[33]蒋璇,臧春华.数字系统设计与PLD应用技术.北京:电子工业出版社.2001.
[34]张明.Verilog HDL实用教程.成都:电子科技大学出版社,1999.
[35]王金明.数字系统设计与Verilog HDL.北京:电子工业出版社,2005.
[36]何健标,王宏远。郭跃登.一种基于FPGA的FIR滤波器实现结构.微电子学与计算机,2008,25(3):47-50.
[37]朱维勇,傅桂生.基于VHDL语言的有限状态机设计方法.计算机技术与应用进展.2004,3(3):702-706.