数字电视信源解码系统架构设计与总线分析
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摘要
随着集成电路设计技术的发展和芯片集成度的提高,传统的ASIC设计方法已经不能满足系统设计复杂性和上市时间紧迫性的要求。在数字电视领域,数字电视的广泛普及和数字电视机顶盒技术的发展也给基于传统ASIC设计方法的数字电视信源解码器的设计带来了新的挑战。SoC设计理论和技术的发展则使得系统级芯片在集成电路的设计领域中越来越显现出其优势。本文基于SoC设计方法学对数字电视信源解码系统的架构设计做了理论分析和实践探索,研究了数字电视信源解码系统的设计、实现和验证分析问题。
SoC设计主要研究系统设计方法和IP核复用等问题。基于系统设计方法,本文通过分析MPEG-2标准中信源解码系统的性能要求及当前的市场情况对信源解码SoC进行了需求分析,从系统功能和性能上定出了信源解码SoC的设计目标。然后结合软硬件划分理论及解码系统各子功能特点对系统进行了软硬件划分,提出了BTV3000信源解码SoC架构。
BTV3000采用了基于ARM核的双核架构、基于AMBA2.0 AHB的总线结构和基于DDR SDRAM的存储器结构。本文重点从软硬件划分的合理性、总线带宽和存储器吞吐率等系统性能因素方面对该架构设计方案进行了定性和定量的分析。
在IP核复用技术上,本文主要以视频解码核作为研究对象分析了IP核设计和复用所需要考虑的问题。视频解码核是信源解码系统中最关键的功能模块,该模块对于系统的性能要求也最高。视频解码核的设计重点不仅仅是解码功能的实现,还需要从系统资源和性能角度去考虑。本文主要针对视频解码核中的基于桶型移位计数器的变长解码器的实现方法和基于流水线的运动补偿模块的设计方法做了分析。
总线性能是SoC设计需要考虑的问题,特别是在基于AHB总线的系统中,总线利用率以及主设备间的总线竞争对系统性能影响很大。BTV3000采用了系统总线和存储总线分开的总线方案,系统总线采用单层AHB总线结构和延迟优先级总裁方案,存储总线采用单层AHB总线结构和简单优先级总裁方案。
本文最后介绍了基于Mentor的Seamless软硬件协同验证平台,并基于此平台完成了BTV3000的系统级功能验证和性能分析,重点分析了总线仲裁方案对于系统总线和存储总线的性能影响。
With the development of IC design technology and the increasing of the circuit density, traditional ASIC design methodology can no longer satisfy the requirements of the design complexity and the time urgency to market. In the digital television area, the popularization of the digital television and the development of Set-Top Box technology also challenge the traditional ASIC based design. SoC design theory and technology make the system chip become more and more predominant in the IC design area. This thesis made some system analysis and design practice for the source decoding system of digital television based on the SoC design methodology.
SoC design mainly focused on system design methodology, IP reuse methodology, etc. With system design methodology, we made requirement analysis according to the MPEG-2 standard and the current market status. Functional and performance definitions about the system were made according to the relative theory and the features of each sub functions of the system. What’s more, this thesis proposed the BTV3000 architecture for the source decoding system.
The BTV3000 has a dual-core architecture based on ARM microprocessors, a bus architecture based on AMBA2.0 AHB and a memory architecture based on DDR SDRAM. Qualitative and quantitative analysis to the BTV3000 architecture were made from the aspects of system performance requirements such as the rationality of the hardware and software partition, memory throughput, bus bandwidth, etc.
As to the IP-reused technology, we took the design of video decoding core as an example. Video decoding is the most importance functional core and the most critical part of the system since its bandwidth consuming and computation complexity. Functional implementation is the key for the core design, but system resources and performance requirements should also be considered. Taking account of these factors, we mainly introduced the design of variable length decoding using the barrier shifter and the motion compensation using pipeline structure for the core design.
Bus performance is an important factor to system design, especially for systems based on AHB bus. Bus utilization and bus contention between multiple masters affected the system performance most. The current BTV3000 adopts divided bus architecture of system bus and memory bus. The system bus used a single-layer AHB bus structure with delayed priority arbitration scheme, while the memory bus used the single-layer AHB bus structure but a simple priority arbitration scheme.
Finally, we introduced Mentor’s Seamless co-verification platform, and finished the function verification and the performance analysis for the BTV3000 system, mainly focused on the effect of the bus arbitration schemes to the bus performance.
SoC设计主要研究系统设计方法和IP核复用等问题。基于系统设计方法,本文通过分析MPEG-2标准中信源解码系统的性能要求及当前的市场情况对信源解码SoC进行了需求分析,从系统功能和性能上定出了信源解码SoC的设计目标。然后结合软硬件划分理论及解码系统各子功能特点对系统进行了软硬件划分,提出了BTV3000信源解码SoC架构。
BTV3000采用了基于ARM核的双核架构、基于AMBA2.0 AHB的总线结构和基于DDR SDRAM的存储器结构。本文重点从软硬件划分的合理性、总线带宽和存储器吞吐率等系统性能因素方面对该架构设计方案进行了定性和定量的分析。
在IP核复用技术上,本文主要以视频解码核作为研究对象分析了IP核设计和复用所需要考虑的问题。视频解码核是信源解码系统中最关键的功能模块,该模块对于系统的性能要求也最高。视频解码核的设计重点不仅仅是解码功能的实现,还需要从系统资源和性能角度去考虑。本文主要针对视频解码核中的基于桶型移位计数器的变长解码器的实现方法和基于流水线的运动补偿模块的设计方法做了分析。
总线性能是SoC设计需要考虑的问题,特别是在基于AHB总线的系统中,总线利用率以及主设备间的总线竞争对系统性能影响很大。BTV3000采用了系统总线和存储总线分开的总线方案,系统总线采用单层AHB总线结构和延迟优先级总裁方案,存储总线采用单层AHB总线结构和简单优先级总裁方案。
本文最后介绍了基于Mentor的Seamless软硬件协同验证平台,并基于此平台完成了BTV3000的系统级功能验证和性能分析,重点分析了总线仲裁方案对于系统总线和存储总线的性能影响。
With the development of IC design technology and the increasing of the circuit density, traditional ASIC design methodology can no longer satisfy the requirements of the design complexity and the time urgency to market. In the digital television area, the popularization of the digital television and the development of Set-Top Box technology also challenge the traditional ASIC based design. SoC design theory and technology make the system chip become more and more predominant in the IC design area. This thesis made some system analysis and design practice for the source decoding system of digital television based on the SoC design methodology.
SoC design mainly focused on system design methodology, IP reuse methodology, etc. With system design methodology, we made requirement analysis according to the MPEG-2 standard and the current market status. Functional and performance definitions about the system were made according to the relative theory and the features of each sub functions of the system. What’s more, this thesis proposed the BTV3000 architecture for the source decoding system.
The BTV3000 has a dual-core architecture based on ARM microprocessors, a bus architecture based on AMBA2.0 AHB and a memory architecture based on DDR SDRAM. Qualitative and quantitative analysis to the BTV3000 architecture were made from the aspects of system performance requirements such as the rationality of the hardware and software partition, memory throughput, bus bandwidth, etc.
As to the IP-reused technology, we took the design of video decoding core as an example. Video decoding is the most importance functional core and the most critical part of the system since its bandwidth consuming and computation complexity. Functional implementation is the key for the core design, but system resources and performance requirements should also be considered. Taking account of these factors, we mainly introduced the design of variable length decoding using the barrier shifter and the motion compensation using pipeline structure for the core design.
Bus performance is an important factor to system design, especially for systems based on AHB bus. Bus utilization and bus contention between multiple masters affected the system performance most. The current BTV3000 adopts divided bus architecture of system bus and memory bus. The system bus used a single-layer AHB bus structure with delayed priority arbitration scheme, while the memory bus used the single-layer AHB bus structure but a simple priority arbitration scheme.
Finally, we introduced Mentor’s Seamless co-verification platform, and finished the function verification and the performance analysis for the BTV3000 system, mainly focused on the effect of the bus arbitration schemes to the bus performance.
引文
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[29] Jason R. Andrews. Co-Verification of Hardware and Software for ARM SoC Design. Newnes, 2005:14~19.
[30] 徐明, 夏新军, 陈吉华. SoC 设计中一种软硬件划分的性能评价方法. 计算机工程, 2004, 21(30), pp. 58~60.
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[32] G.Ascia,V. Catania and M.Palesi,“Parameterized System Design Based on Genetic Algorithms”, In 9th International Symposium on Hardware/Software Co-design, Copenhagen,Denmark,Apr.25-27 2001, pp: 177~182.
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