基于H.264/AVC视频解码器的VLSI设计与研究
摘要
H.264/AVC是ITU-T和MPEG组织共同推出的新一代视频压缩标准,其压缩效率较H.263和MPEG-4有显著提高。本文设计了一种适合H.264/AVC变字长解码器,提出了一种新的更快更高效适合解码的查表方法。在尽量减少时钟消耗和硬件开销的前提下,本文根据码流特点对解码模块结构进行了优化,使解码效率更优、时钟频率更高。解码控制电路中主要采用了桶型移位寄存器,并在解码过程中频繁使用了首一检测器。查表解码电路中,改变传统的遍历搜索比较的方法,本文根据码流的特点将码表按规律拆成多个子表,使查表效率和电路时序上有很大的突破,尤其标志符解码和非零系数值两个最难的解码模块有了突破性进展:标志符解码能够实现在两个时钟周期内完成,非零系数值解码在三个时钟周期内解出,并且该子模块电路能达到220M。同时考虑到IP可重复性设计和便于各器件移植,本文采用同步设计,外部接口都使用fifo公用接口。通过在Quart-usⅡ6.0 FPGA开发软件下仿真分析表明在该变长解码器能达到150M时钟频率,完全可以满足10M/S码率下H.264标准中Leve13.0的性能要求。
论文的主要研究工作如下:
1.研究变字长解码器的大规模集成电路设计和验证,主要包括静态时序分析、时序优化、布局布线、搭建测试平台,生成测试向量、编写参考模型等等验证和设计工作。
2.研究变字长编解码算法,并根据协议设计了变字长解码器。同时在IP可重复性设计和可移植性方面做了研究,整个系统的设计使用Verilog硬件描述语言实现。
3.解cavlc码中,本文根据码表的特点提出了一种新的查表方法,在不增加存储资源的条件下,通过优化结构提高解码效率,节省时钟周期,通过改变关键时序路径提高时钟频率。
4.指数哥伦布解码过程中,本文优化解码器结构,减少解码所需要的时钟周期。
H.264/AVC is a new video coding standard with enhanced higher compression than H.263 and MPEG raised by ITU-T and MPEG orgnizations. This paper proposes an implementation of variable length decoder for H.264/AVC. While minimizing the use of clock cycles and hardware cost, the design is separated into several parts according to the specialty of the code stream. Bucket shift register is used to control circuit, and the first one detector is used in the process of decoding. In tabular decoding circuit, the design discards the traditional way which is the way of traversing search comparison. Instead, the table is devided into a number of sub-tables according to the feature of code streams. It makes tabular efficiency and circuit timing have great breakthroughs, especially in the total_coffe and no_zero level decode modules: the total_coffe module decode need only 2 cycles and the nozero level module decode need only 3 cycles, and the frequence of the modules is 220 Mhz.. By simulating with Quartus II 6.0, the results shows that its maximal working frequency is around 220 MHz and it could fulfill the required performance of H.264/AVC standard level 3.0.
The main contents of this paper are as follows. Firstly, it is the presentation of the design and the verification of VLD decoder with VLSI, such as sythsis, fitter, STA, coding reference module and so on. Secondly, it is the introduction of video coding standard, the history of its development, and video codec theory, etc. Thirdly the protocal of H.264/AVC and the princinple about VLD CODEC is read and researched. Then it is the design of decode of VLD with Verilog. A new way of decoding the stream with faster speed and less cycle is used. At the same time we use IP reused design for tansplanting between different devices, so we use general FIFO interface with others. According the feature of code, a new way of looking for table is used when decoding cavlc. Concretely speaking, the original table is devided into many sub-tables. In this way the speed of circuit is higher and decode in less cycle. At the same time we optimised the archtecture of circuit to improve the speed of circuit. In the last part, the clock cycle of decoding is reduced, and the structure of decoder is optimized.
论文的主要研究工作如下:
1.研究变字长解码器的大规模集成电路设计和验证,主要包括静态时序分析、时序优化、布局布线、搭建测试平台,生成测试向量、编写参考模型等等验证和设计工作。
2.研究变字长编解码算法,并根据协议设计了变字长解码器。同时在IP可重复性设计和可移植性方面做了研究,整个系统的设计使用Verilog硬件描述语言实现。
3.解cavlc码中,本文根据码表的特点提出了一种新的查表方法,在不增加存储资源的条件下,通过优化结构提高解码效率,节省时钟周期,通过改变关键时序路径提高时钟频率。
4.指数哥伦布解码过程中,本文优化解码器结构,减少解码所需要的时钟周期。
H.264/AVC is a new video coding standard with enhanced higher compression than H.263 and MPEG raised by ITU-T and MPEG orgnizations. This paper proposes an implementation of variable length decoder for H.264/AVC. While minimizing the use of clock cycles and hardware cost, the design is separated into several parts according to the specialty of the code stream. Bucket shift register is used to control circuit, and the first one detector is used in the process of decoding. In tabular decoding circuit, the design discards the traditional way which is the way of traversing search comparison. Instead, the table is devided into a number of sub-tables according to the feature of code streams. It makes tabular efficiency and circuit timing have great breakthroughs, especially in the total_coffe and no_zero level decode modules: the total_coffe module decode need only 2 cycles and the nozero level module decode need only 3 cycles, and the frequence of the modules is 220 Mhz.. By simulating with Quartus II 6.0, the results shows that its maximal working frequency is around 220 MHz and it could fulfill the required performance of H.264/AVC standard level 3.0.
The main contents of this paper are as follows. Firstly, it is the presentation of the design and the verification of VLD decoder with VLSI, such as sythsis, fitter, STA, coding reference module and so on. Secondly, it is the introduction of video coding standard, the history of its development, and video codec theory, etc. Thirdly the protocal of H.264/AVC and the princinple about VLD CODEC is read and researched. Then it is the design of decode of VLD with Verilog. A new way of decoding the stream with faster speed and less cycle is used. At the same time we use IP reused design for tansplanting between different devices, so we use general FIFO interface with others. According the feature of code, a new way of looking for table is used when decoding cavlc. Concretely speaking, the original table is devided into many sub-tables. In this way the speed of circuit is higher and decode in less cycle. At the same time we optimised the archtecture of circuit to improve the speed of circuit. In the last part, the clock cycle of decoding is reduced, and the structure of decoder is optimized.
引文
[1]Iain E.G.Richardson.H.264 and MPEG-4 Video Compression Video Coding for Next-generation Multimedia.UK:Aberdeen,The Robert Gordon University,John Wiley & Sons Ltd,2003
[2]Iain E.G.Richardson.视频编解码器设计.国防科技大学出版社,2005
[3]戴春泉.H.264变字长解码器的硬件设计与实现.北京:中国科学院计算技术研究所,2004
[4]李宾,高平.H.264编码系统的特点及其应用前景.电视技术,2003,(6):19
[5]毕厚杰.新一代视频压缩编码标准——H.264/AVC.人民邮电出版社,2006
[6]王明臣等.数字电视与高清晰度电视.中国广播电视出版社,2003
[7]精英科技.视频压缩与音频编码技术.中国电力出版社,2001
[8]钟玉琢等.运动图像及伴音通用编码国际标准MPEG-2.清华大学出版社,1997
[9]常用林.基于H264AVC的HDTV视频解码芯片研究与初步设计[硕士学位论文]广州:暨南大学,2005
[10]吴子辉,石旭利,张兆扬.H.264编解码器方案综述.电路与应用,2005,12:12-14
[11]姚庆栋,毕厚杰,王兆华,等.图像编码基础.人民邮电出版社,1984
[12]Wu Di,Gao Wen,Hu Mingzeng,et al.A VLSI Architecture Design of CAVL Decoder.Proceedings.5 th International Conference on ASIC,2003,44-46
[13]Jeon J H,Park Y S,Park H W.A Fast Variable-length Decoder Using Plane Separation[J].IEEE Trans.Circuits Syst.Video Technol.,2000.10.806-812
[14]YaoWang,Jom Ostermann,Ya-Qin Zhang.Video Processing and Communication.北京:清华大学出版社,2002
[15]楼剑,陆亮,虞露等.H.264标准的特点及其改进研究.电视技术,2003(6):13-15
[16]Altera Company.FPGAs Provide Reconfigurable DSP Solutions.2002(8)
[17]Thomas Wiegand,Gary J.Sullivan,Gisle Bjentegaard,and Ajay Luthra Overview of the H.264/AVC Video Coding Standard.IEEE Transactions on Circuits and Systems for Video Technology,2003,13(7)
[18]Luthra,A;Sullivan,G J.;Wiegand,T.Introduction to the special issue on the H.264/AVC video coding standard,IEEE Transactions on Circuits and Systems for Video Technology,2003,13(7)
[19]J.Nikara,S.Vassiliadis,J.Takala,M.Sima,P.Liuha,Parallel multiple symbol variable-length decoding,Proceedings 2002 IEEE International Conference on Computer Design:VLSI in Computers and Processors,.126-131
[20]Chi-Wang Ting,Lai-Man Po,Chun-Ho Cheung.CENTER-BIASED FRAME SELECTION ALGORITHMS FOR FAST multiframe motion estimatio in H.264.Neural Networks and Signal Processing,2003.Proceedings of the 2003International Conference on.Volume 2,14-17 Dec.2003.1258-1261
[21]Gulistan RAJA,Muhammad J.MIRZA.Performance comparison of advanced video coding H.264 standard with baseline H.263 and H.263+ standards.International Symposium on Communications and Information Technologics 2004.October.2004.743-746
[22]吴伟陵.信息处理与编码.人民邮电出版社.1999.7
[23]仇佩亮 信息论与编码 高等教育出版社.2004.7
[24]Kamaci,N.and Altunbasak,Y.Performance comparison of the emerging H.264 video coding standard with the existing standards.Multimedia and Expo,2003.ICME'03.Proceedings.2003 International Conference on.1(7)
[25]H.264/MPEG-4 Part 10 White Paper,2002.7,http://www.vcodex.com Draft ITU-TRecommendation and Final Draft Intemational Standard of Joint Video Specification(2003.5.15)
[26]Ostermann,J.,Bormans,J.and List,P.Video coding with H.264/AVC:tools performance and complexity.Circuits and Systems Magazine,IEEE.2004,4(1):7-28
[27]List,P.,Joch,A.,Lainema,J.etl.Adaptive Deblocking Filter.IEEE Transactions on Circuits and Systems for Video Technology.2003,13(7)
[28]Gary,J.S.,Pankaj,T.,and Luthra,A.The H.264/AVC Advanced Video Coding Standard:Overview and Introduction to the Fidelity Range Extensions.SPIE Conference on Applications of Digital Image Processing,2004(8)
[29]姚栋,虞露.H_264指数哥伦布码解码部件的硬件设计和实现.电视技术2004(11)
[30]戴春泉,李锦涛,黄晁.适用于H.264视频解码器的VLD设计.计算机工程,2005(7):162-164
[31]谷岚.基于H.264/AVC中CAVLC算法研究及VLSI设计.[硕士学位论文]哈尔滨:哈尔滨工业大学,2006(6)
[32]路奇,方向忠,刘凌志.基于SoC平台设计的H.264/AVC CAVLC解码器.电视技术,2005(2):29-31
[33]龚建锋,金文光,季爱明.基于H.264解码中CAVLC的优化.微电子学与 计算机,2007(1):86
[34]张颖,刘济林.H.264中CAVLC解码的分组优化.信号处理,2005(21):17-21
[35]朱冬冬,戴琼海.H.264解码器中CAVLC码表查找算法的改进.电视技术,2004(1):26-27
[36]张旭东,卢国栋,冯建.图像编码基础和小波压缩技术—原理、算法和标准.北京:清华大学出版社,2004
[37]杜晓刚,秦东.何寅叶波适用于MPEG2视频解码的VLD设计.微电子学,1999(12):428-431
[38]裴昌幸,刘乃安,杜武林.电视原理与现代电视系统.第一版.西安:西安电子科技大学出版社,1997(3)
[39]张力航,林涛,周开伦.软硬件协同设计技术在H.264解码器设计中的应用.电子设计应用,2006(9):89-97
[40]张春等译.编写测试平台--HDL模型的功能验证(第二版).北京:电子工业出版社,2006(8)
[41]吴子辉,石旭利,张兆扬.H.264编解码器方案综述.电路与应用,2005(12):12-14
[42]石磊,林涛,焦孟草.H.264/AVC硬件解码器设计及其验证策略.微电子学2006(2):17-19
[43]黄琼珍,郑世宝,杨宇红.H.264/AVC中去块效应环路滤波的VLSI实现.微电子学与计算机,2006,23(4):133-135
[44]宋锐,赵波,肖嵩.适合硬件实现的运动估计方法及其VLSI实现.西安电子科技大学学报(自然科学版),2006(4):157-160
[45]谢将相,杨昆,张春,王志华.H.264/AVC中去块效应滤波系统的结构设计电视技术,2006(7),28-30
[2]Iain E.G.Richardson.视频编解码器设计.国防科技大学出版社,2005
[3]戴春泉.H.264变字长解码器的硬件设计与实现.北京:中国科学院计算技术研究所,2004
[4]李宾,高平.H.264编码系统的特点及其应用前景.电视技术,2003,(6):19
[5]毕厚杰.新一代视频压缩编码标准——H.264/AVC.人民邮电出版社,2006
[6]王明臣等.数字电视与高清晰度电视.中国广播电视出版社,2003
[7]精英科技.视频压缩与音频编码技术.中国电力出版社,2001
[8]钟玉琢等.运动图像及伴音通用编码国际标准MPEG-2.清华大学出版社,1997
[9]常用林.基于H264AVC的HDTV视频解码芯片研究与初步设计[硕士学位论文]广州:暨南大学,2005
[10]吴子辉,石旭利,张兆扬.H.264编解码器方案综述.电路与应用,2005,12:12-14
[11]姚庆栋,毕厚杰,王兆华,等.图像编码基础.人民邮电出版社,1984
[12]Wu Di,Gao Wen,Hu Mingzeng,et al.A VLSI Architecture Design of CAVL Decoder.Proceedings.5 th International Conference on ASIC,2003,44-46
[13]Jeon J H,Park Y S,Park H W.A Fast Variable-length Decoder Using Plane Separation[J].IEEE Trans.Circuits Syst.Video Technol.,2000.10.806-812
[14]YaoWang,Jom Ostermann,Ya-Qin Zhang.Video Processing and Communication.北京:清华大学出版社,2002
[15]楼剑,陆亮,虞露等.H.264标准的特点及其改进研究.电视技术,2003(6):13-15
[16]Altera Company.FPGAs Provide Reconfigurable DSP Solutions.2002(8)
[17]Thomas Wiegand,Gary J.Sullivan,Gisle Bjentegaard,and Ajay Luthra Overview of the H.264/AVC Video Coding Standard.IEEE Transactions on Circuits and Systems for Video Technology,2003,13(7)
[18]Luthra,A;Sullivan,G J.;Wiegand,T.Introduction to the special issue on the H.264/AVC video coding standard,IEEE Transactions on Circuits and Systems for Video Technology,2003,13(7)
[19]J.Nikara,S.Vassiliadis,J.Takala,M.Sima,P.Liuha,Parallel multiple symbol variable-length decoding,Proceedings 2002 IEEE International Conference on Computer Design:VLSI in Computers and Processors,.126-131
[20]Chi-Wang Ting,Lai-Man Po,Chun-Ho Cheung.CENTER-BIASED FRAME SELECTION ALGORITHMS FOR FAST multiframe motion estimatio in H.264.Neural Networks and Signal Processing,2003.Proceedings of the 2003International Conference on.Volume 2,14-17 Dec.2003.1258-1261
[21]Gulistan RAJA,Muhammad J.MIRZA.Performance comparison of advanced video coding H.264 standard with baseline H.263 and H.263+ standards.International Symposium on Communications and Information Technologics 2004.October.2004.743-746
[22]吴伟陵.信息处理与编码.人民邮电出版社.1999.7
[23]仇佩亮 信息论与编码 高等教育出版社.2004.7
[24]Kamaci,N.and Altunbasak,Y.Performance comparison of the emerging H.264 video coding standard with the existing standards.Multimedia and Expo,2003.ICME'03.Proceedings.2003 International Conference on.1(7)
[25]H.264/MPEG-4 Part 10 White Paper,2002.7,http://www.vcodex.com Draft ITU-TRecommendation and Final Draft Intemational Standard of Joint Video Specification(2003.5.15)
[26]Ostermann,J.,Bormans,J.and List,P.Video coding with H.264/AVC:tools performance and complexity.Circuits and Systems Magazine,IEEE.2004,4(1):7-28
[27]List,P.,Joch,A.,Lainema,J.etl.Adaptive Deblocking Filter.IEEE Transactions on Circuits and Systems for Video Technology.2003,13(7)
[28]Gary,J.S.,Pankaj,T.,and Luthra,A.The H.264/AVC Advanced Video Coding Standard:Overview and Introduction to the Fidelity Range Extensions.SPIE Conference on Applications of Digital Image Processing,2004(8)
[29]姚栋,虞露.H_264指数哥伦布码解码部件的硬件设计和实现.电视技术2004(11)
[30]戴春泉,李锦涛,黄晁.适用于H.264视频解码器的VLD设计.计算机工程,2005(7):162-164
[31]谷岚.基于H.264/AVC中CAVLC算法研究及VLSI设计.[硕士学位论文]哈尔滨:哈尔滨工业大学,2006(6)
[32]路奇,方向忠,刘凌志.基于SoC平台设计的H.264/AVC CAVLC解码器.电视技术,2005(2):29-31
[33]龚建锋,金文光,季爱明.基于H.264解码中CAVLC的优化.微电子学与 计算机,2007(1):86
[34]张颖,刘济林.H.264中CAVLC解码的分组优化.信号处理,2005(21):17-21
[35]朱冬冬,戴琼海.H.264解码器中CAVLC码表查找算法的改进.电视技术,2004(1):26-27
[36]张旭东,卢国栋,冯建.图像编码基础和小波压缩技术—原理、算法和标准.北京:清华大学出版社,2004
[37]杜晓刚,秦东.何寅叶波适用于MPEG2视频解码的VLD设计.微电子学,1999(12):428-431
[38]裴昌幸,刘乃安,杜武林.电视原理与现代电视系统.第一版.西安:西安电子科技大学出版社,1997(3)
[39]张力航,林涛,周开伦.软硬件协同设计技术在H.264解码器设计中的应用.电子设计应用,2006(9):89-97
[40]张春等译.编写测试平台--HDL模型的功能验证(第二版).北京:电子工业出版社,2006(8)
[41]吴子辉,石旭利,张兆扬.H.264编解码器方案综述.电路与应用,2005(12):12-14
[42]石磊,林涛,焦孟草.H.264/AVC硬件解码器设计及其验证策略.微电子学2006(2):17-19
[43]黄琼珍,郑世宝,杨宇红.H.264/AVC中去块效应环路滤波的VLSI实现.微电子学与计算机,2006,23(4):133-135
[44]宋锐,赵波,肖嵩.适合硬件实现的运动估计方法及其VLSI实现.西安电子科技大学学报(自然科学版),2006(4):157-160
[45]谢将相,杨昆,张春,王志华.H.264/AVC中去块效应滤波系统的结构设计电视技术,2006(7),28-30