基于高性能YHFT DSP的视频处理器的设计
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摘要
数字视频系统,例如视频会议、视频电话、标准清晰度电视(SDTV)、高清晰度电视(HDTV)等应用的出现极大地改变了人们的通信及娱乐方式。适用于不同应用环境的视频标准的统一进一步推进了数字视频技术的发展进步。数字视频技术的发展同时推进了数字信号处理技术的发展,使得数字信号处理器(DSP)在视频会议、视频电话、标清电视、高清电视等领域寻找到了更广阔的发展空间。但由于存储器带宽、DSP的处理能力和功耗等原因,基于DSP开发实时、高性能、高复杂度的数字视频系统也给DSP带来了极大的挑战。
目前,专用视频处理器市场主要被国外所占领,国内在此领域尚属空白。YHFT DSP是国防科学技术大学计算机学院自主设计研制的新一代通用、高性能32位定点数字信号处理器芯片,为满足即将到来的数字视频时代国内对视/音频处理专用DSP芯片的大量需求,基于YHFT DSP开发具有自主知识产权的、专用视频处理器已经变得非常必要。
本文首先介绍了常用视频编/解码国际标准,分析比较了国际主流媒体处理器的发展现状及其不同设计方案,并在此基础上分析、论证了研发具有自主产权的视频处理器的重要性和可行性。
本文基于YHFT DSP设计实现了一个MPEG-2 SDTV软件视频解码器,并详细分析了解码过程中各阶段的算法对YHFT DSP的实时处理能力、存储器带宽、功耗等方面的要求,结合YHFT DSP特点分析了YHFT DSP在视频处理方面的优势与不足。基于上述分析、借鉴国际主流媒体处理器的设计方案提出了基于YHFT DSP的高性能视频处理器--“银河飞腾”视频处理器(YHFT-VDSP)。在充分论证YHFT-VDSP系统的合理性和可行性的基础上,给出了YHFT-VDSP的详细设计方案,并详细地分析了YHFT-VDSP较之YHFT DSP在视频处理能力上所获得的增益。
本文接着讨论了2-D DCT/IDCT在视频编/解码中的应用,并对2-D IDCT算法进行了调整以降低2-D IDCT的硬件实现的复杂度,最后基于调整后的2-D IDCT算法完成了YHFT-VDSP的高速、并行IDCT单元的设计实现。
本文基于原有YHFT DSP的EDMA系统设计实现了YHFT-VDSP的EDMA系统,并完成了EDMA与片上视频端口(Vport)的互连工作。最后根据视频应用的特殊性设计了接近实际应用环境的设计平台,完成了对EDMA系统的功能级模拟验证工作。
The advent of digital video systems,such as video conference,video telephone,standard definition television (SDTV) and high definition television (HDTV) has significantly changed the way people communicate with each other and enjoy themselves. Furthermore,digital video technology is considerably advanced by the unification of different digital video standards which apply for different application environment .The development of digital video technology also promotes the advance of digital signal processing technology,providing more opportunities for Digital Signal Processor(DSP) to find its way in video conference,video telephone, SDTV ,HDTV.But it is also a great challenge to develop real-time, high-performance digital video systems with high complexity,due to the bandwidth of memory system,processing capacity and power consumption of DSP.
At present,the market of application-specific video processor is mainly shared by foreign companies,with no corresponding product in such area has been launched by domestic company.Therefore,it is highly necessary to design a application-specific video processor with independent intellegence-property based on YHFT DSP which is designed independently by computer school of NUDT in order to meet the domestic requirement for application-specific DSP for video/audio signal processing in the forthcoming age of digital video.
At the beginning of this paper,several popular video compression/decompression standards have been introduced,and discussion about current mainstream media processors in the world is also dealed with in detail.In the end of chapter 1,the necessity and feasibility of designing a video processor with independent intellegence-property is analysed and justified based on the previous discussion.
In this paper,a software MPEG-2 SDTV video decoder is implemented based on YHFT DSP.We have also discussed algorithms in the different stages of the video decoder and their requirement for processing capacity,memory bandwidth and power consumption of YHFT DSP.A high-performance video processor----YHFT-VDSP is put forward, combining the previous discussion and the different design schemes of current mainstream media processors in the world.The detailed design scheme of YHFT-VDSP is described based on the justification of the rationality and feasibility of YHFT-VDSP. Speedup of YHFT-VDSP relative toYHFT DSP in terms of video signal processing peiformance is also discussed in detail.
The application of 2-dimension DCT/IDCT in video compression/decompression is also discussed,followed by the adjustment on a fast 2-dimension IDCT algorithm in order to faciliate the hardware implementation of the algorithm.In the latter of this paper,We discussed a high-speed,parallel hardware implementation of IDCT---- a part of YHFT-VDSP,based on the adjusted algorithm.
Finally,The EDMA system of YHFT VDSP is implemented based on the EDMA of YHFT DSP. Interconnection between EDMA and on-chip video port is also designed.At the end of this paper,Functional simulation and verification on The EDMA system of YHFT VDSP is done based on testbench which is designed according to the particularity of video application systems to represent real environment.
目前,专用视频处理器市场主要被国外所占领,国内在此领域尚属空白。YHFT DSP是国防科学技术大学计算机学院自主设计研制的新一代通用、高性能32位定点数字信号处理器芯片,为满足即将到来的数字视频时代国内对视/音频处理专用DSP芯片的大量需求,基于YHFT DSP开发具有自主知识产权的、专用视频处理器已经变得非常必要。
本文首先介绍了常用视频编/解码国际标准,分析比较了国际主流媒体处理器的发展现状及其不同设计方案,并在此基础上分析、论证了研发具有自主产权的视频处理器的重要性和可行性。
本文基于YHFT DSP设计实现了一个MPEG-2 SDTV软件视频解码器,并详细分析了解码过程中各阶段的算法对YHFT DSP的实时处理能力、存储器带宽、功耗等方面的要求,结合YHFT DSP特点分析了YHFT DSP在视频处理方面的优势与不足。基于上述分析、借鉴国际主流媒体处理器的设计方案提出了基于YHFT DSP的高性能视频处理器--“银河飞腾”视频处理器(YHFT-VDSP)。在充分论证YHFT-VDSP系统的合理性和可行性的基础上,给出了YHFT-VDSP的详细设计方案,并详细地分析了YHFT-VDSP较之YHFT DSP在视频处理能力上所获得的增益。
本文接着讨论了2-D DCT/IDCT在视频编/解码中的应用,并对2-D IDCT算法进行了调整以降低2-D IDCT的硬件实现的复杂度,最后基于调整后的2-D IDCT算法完成了YHFT-VDSP的高速、并行IDCT单元的设计实现。
本文基于原有YHFT DSP的EDMA系统设计实现了YHFT-VDSP的EDMA系统,并完成了EDMA与片上视频端口(Vport)的互连工作。最后根据视频应用的特殊性设计了接近实际应用环境的设计平台,完成了对EDMA系统的功能级模拟验证工作。
The advent of digital video systems,such as video conference,video telephone,standard definition television (SDTV) and high definition television (HDTV) has significantly changed the way people communicate with each other and enjoy themselves. Furthermore,digital video technology is considerably advanced by the unification of different digital video standards which apply for different application environment .The development of digital video technology also promotes the advance of digital signal processing technology,providing more opportunities for Digital Signal Processor(DSP) to find its way in video conference,video telephone, SDTV ,HDTV.But it is also a great challenge to develop real-time, high-performance digital video systems with high complexity,due to the bandwidth of memory system,processing capacity and power consumption of DSP.
At present,the market of application-specific video processor is mainly shared by foreign companies,with no corresponding product in such area has been launched by domestic company.Therefore,it is highly necessary to design a application-specific video processor with independent intellegence-property based on YHFT DSP which is designed independently by computer school of NUDT in order to meet the domestic requirement for application-specific DSP for video/audio signal processing in the forthcoming age of digital video.
At the beginning of this paper,several popular video compression/decompression standards have been introduced,and discussion about current mainstream media processors in the world is also dealed with in detail.In the end of chapter 1,the necessity and feasibility of designing a video processor with independent intellegence-property is analysed and justified based on the previous discussion.
In this paper,a software MPEG-2 SDTV video decoder is implemented based on YHFT DSP.We have also discussed algorithms in the different stages of the video decoder and their requirement for processing capacity,memory bandwidth and power consumption of YHFT DSP.A high-performance video processor----YHFT-VDSP is put forward, combining the previous discussion and the different design schemes of current mainstream media processors in the world.The detailed design scheme of YHFT-VDSP is described based on the justification of the rationality and feasibility of YHFT-VDSP. Speedup of YHFT-VDSP relative toYHFT DSP in terms of video signal processing peiformance is also discussed in detail.
The application of 2-dimension DCT/IDCT in video compression/decompression is also discussed,followed by the adjustment on a fast 2-dimension IDCT algorithm in order to faciliate the hardware implementation of the algorithm.In the latter of this paper,We discussed a high-speed,parallel hardware implementation of IDCT---- a part of YHFT-VDSP,based on the adjusted algorithm.
Finally,The EDMA system of YHFT VDSP is implemented based on the EDMA of YHFT DSP. Interconnection between EDMA and on-chip video port is also designed.At the end of this paper,Functional simulation and verification on The EDMA system of YHFT VDSP is done based on testbench which is designed according to the particularity of video application systems to represent real environment.
引文
[1] ISO/IEC 13818-1,Generic Coding Of Moving Pictures And Associated Audio Information--system,November 1994
[2] ISO/IEC 13818-2 ,Generic Coding Of Moving Pictures And Associated Audio Information --Video,November 1994
[3] Supavadee Aramvith,Ming-Ting Sun,MPEG-1 and MPEG-2 Video Standards, University of Washington,1996
[4] ISO/IEC 14496-2 ,Coding of Moving Pictures and Audio--Visual,May 1998
[5] ISO/IEC N4668 ,Overview of the MPEG-4 Standard,March 2002
[6] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay Luthra Overview of the H.264 / AVC Video Coding Standard,IEEE,July 2003
[7] Evaluating DSP Processor Performance,Berkeley Design Technology, Inc,2002
[8] Sally A. McKee,Zhen Fang ,Mateo Valero,An MPEG-4 Performance Study for non-SIMD, General Purpose Architectures,IEEE,2003
[9] Srinivas Devadas,Sharad Malik, A Survey of Optimization Techniques Targeting Low Power VLSI Circuits,IEEE,1996
[10] PNX1300 Series Media Processors Data Book,Philips,15 February 2002
[11] PNX15xx Series Data Book,Philips,17 March 2006
[12] PNX17xx Series Data Book,Philips,17 March 2006
[13] TMS320DM642 digital Media Processor,TI,SPRS200-July 2002
[14] TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor Data Manual,TI,SPRS200C-July 2002
[15] Ketan Patel,Brian C.Smith, Lawrence A.Rowe, Performance of a software MPEG Video Decoder, Computer Science Division-EECS,University of California,1993
[16] Sundararajan Sriram,Ching-Yu Hung,MPEG-2 Video Decoding on the TMS320C6X DSP Architecture,IEEE,1998
[17] Kyeong-yuk Min,Jong-wha Chong,A memory-efficient VLC decoder architecture for MPEG-2 application,2000
[18] Cheng-The Hsieh,Seung P.Kim, A concurrent memory-efficient VLC decoder for MPEG applications,IEEE,1996
[19] Latha Pillai, Video Decompression Using IDCT,www.xilinx.com,2005
[20] Yung-Pin Lee,Liang-Gee Chen,Chung-Wei Ku,Architecture design of MPEG-2 decoder system,IEEE,1995
[21] Nathaniel J. August,Dong Sam Ha, Low Power Design of DCT and IDCT forLow Bit Rate Video Codecs,IEEE,2004
[22] He Wei-feng,Mao Zhi-gang,Wang Jin-xiang,Wang Dao-fu, Design and Implementation of Motion Compensation for MPEG-4 AS profile Streaming Decoding,IEEE,2003
[23] Chih-Da Chien,Ho-Chun Chen,Lin-Chieh Huang,Jiun-In Guo, A low-power motion compensation IP core design for MPEG1/2/4 Video Decoding,IEEE,2005
[24] Junghwan Choi,Jinhwan Jeon ,Kiyoung Choi, Power minimization of functional units by partially guarded computation,IEEE,2000
[25] Kun-Min Yang,Ming-Ting Sun,Lancelot Wu, A family of VLSI designs for the motion compensation block-matching algorithm,IEEE,1989
[26] MPEG-2 Loopback on the DM642 EVM,www.ti.com,2003
[27] Iain E G Richardson,Yafan Zhao, Video Codec Complexity Management, School of Electronic and Electrical Engineering, The Robert Gordon University,2001
[28] D.Lauzon,A.Vincent,L.wang, Performance Evaluation of MPEG-2 for HDTV,Communications Research Centre,Ottawa,Ontario,Canada,1995
[29] Peter Altenbernd, Lars-Olof Burchard, Friedhelm Stappert, Worst-Case Execution Times Analysis of MPEG-2 Decoding,IEEE,2000
[30] Peter Pirsch, Hans-Joachim Stolberg,VLSI Implementations of Image and Video Multimedia Processing Systems,IEEE, November 1998
[31] Peter Pirsch ,Nicolas Demassieux,Winfried Gehrke,VLSI architectures for video compression-a survey,IEEE,1995
[32] Konstantinos Konstantinides, key components in the design of image and video compression Ics, Hewlett-Packard Laboratories, Computer Peripherals Laboratory Imaging Peripherals Department,IEEE,2002
[33] Matjaz Verderber, Andrej Zemva, Andrej Trost, HW/SW Codesign of the MPEG-2 Video Decoder,IEEE,2003
[34] Abhik Sarkar, Kaushik Saha, Srijib Maiti, Parallel implementation of Mpeg-2 video decoder,IEEE,2003
[35] S.K.Jang,S.D.Kim,J.Lee,G.Y.Choi,J.B.Ra, HW/SW co-implementation of a H.263 video codec,IEEE,2000
[36] Mikael Karlsson Rudberg,Lars Wanhammar, An MPEG-2 video decoder DSP architecture,IEEE,1996
[37] Rick Richmond ,Decode MPEG-2 video with Virtex,www.amphion.com,2003
[38] Seong Mo Park, Miyoung Lee, Seungchul Kim, VLSI Implementation of H.264 Video Decoder, ETRI Journal, Volume 28, Number 4, August 2006
[39] Marlene Wan, Hui Zhang, Varghese George, Design Methodology of aLow-Energy Reconfigurable Single-Chip DSP System, Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley,2000
[40] Anantha P.Chandrakasan,Robert W.Brodersen,Minimizing power consumption in digital CMOS circuits,IEEE,1995
[41] 李方慧,王飞,何佩,TMS320C6000 系列 DSP 原理与应用,北京:电子工业出版社,2003
[42] 钟玉琢,王琪,赵黎,杨小勤,MPEG-2 运动图象压缩编码国际标准及 MPEG的新进展,清华大学出版社,2002
[43] 胡广书,数字信号处理――理论、算法与实现,北京:清华大学出版社,2003
[44] 王诚,薛小刚,钟信潮,FPGA/CPLD 设计工具――Xilinx ISE 5.x 使用详解,人民邮电出版社,2003
[45] 郭斌,MPEG-2 压缩编码技术原理应用,www.dvbcn.com,2004
[46] 陈胜刚,基于“银河飞腾”DSP 的视频采集子系统的设计,国防科技大学研究生院工学硕士论文,湖南长沙,2006
[47] 谷会涛,基于“银河飞腾”DSP 的视频显示子系统的设计,国防科技大学研究生院工学硕士论文,湖南长沙,2006
[48] 王旭辉,高性能视频处理器 YHFT-VDSP 中外部存储器接口的设计与实现,国防科技大学研究生院工学硕士论文,湖南长沙,2006
[2] ISO/IEC 13818-2 ,Generic Coding Of Moving Pictures And Associated Audio Information --Video,November 1994
[3] Supavadee Aramvith,Ming-Ting Sun,MPEG-1 and MPEG-2 Video Standards, University of Washington,1996
[4] ISO/IEC 14496-2 ,Coding of Moving Pictures and Audio--Visual,May 1998
[5] ISO/IEC N4668 ,Overview of the MPEG-4 Standard,March 2002
[6] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay Luthra Overview of the H.264 / AVC Video Coding Standard,IEEE,July 2003
[7] Evaluating DSP Processor Performance,Berkeley Design Technology, Inc,2002
[8] Sally A. McKee,Zhen Fang ,Mateo Valero,An MPEG-4 Performance Study for non-SIMD, General Purpose Architectures,IEEE,2003
[9] Srinivas Devadas,Sharad Malik, A Survey of Optimization Techniques Targeting Low Power VLSI Circuits,IEEE,1996
[10] PNX1300 Series Media Processors Data Book,Philips,15 February 2002
[11] PNX15xx Series Data Book,Philips,17 March 2006
[12] PNX17xx Series Data Book,Philips,17 March 2006
[13] TMS320DM642 digital Media Processor,TI,SPRS200-July 2002
[14] TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor Data Manual,TI,SPRS200C-July 2002
[15] Ketan Patel,Brian C.Smith, Lawrence A.Rowe, Performance of a software MPEG Video Decoder, Computer Science Division-EECS,University of California,1993
[16] Sundararajan Sriram,Ching-Yu Hung,MPEG-2 Video Decoding on the TMS320C6X DSP Architecture,IEEE,1998
[17] Kyeong-yuk Min,Jong-wha Chong,A memory-efficient VLC decoder architecture for MPEG-2 application,2000
[18] Cheng-The Hsieh,Seung P.Kim, A concurrent memory-efficient VLC decoder for MPEG applications,IEEE,1996
[19] Latha Pillai, Video Decompression Using IDCT,www.xilinx.com,2005
[20] Yung-Pin Lee,Liang-Gee Chen,Chung-Wei Ku,Architecture design of MPEG-2 decoder system,IEEE,1995
[21] Nathaniel J. August,Dong Sam Ha, Low Power Design of DCT and IDCT forLow Bit Rate Video Codecs,IEEE,2004
[22] He Wei-feng,Mao Zhi-gang,Wang Jin-xiang,Wang Dao-fu, Design and Implementation of Motion Compensation for MPEG-4 AS profile Streaming Decoding,IEEE,2003
[23] Chih-Da Chien,Ho-Chun Chen,Lin-Chieh Huang,Jiun-In Guo, A low-power motion compensation IP core design for MPEG1/2/4 Video Decoding,IEEE,2005
[24] Junghwan Choi,Jinhwan Jeon ,Kiyoung Choi, Power minimization of functional units by partially guarded computation,IEEE,2000
[25] Kun-Min Yang,Ming-Ting Sun,Lancelot Wu, A family of VLSI designs for the motion compensation block-matching algorithm,IEEE,1989
[26] MPEG-2 Loopback on the DM642 EVM,www.ti.com,2003
[27] Iain E G Richardson,Yafan Zhao, Video Codec Complexity Management, School of Electronic and Electrical Engineering, The Robert Gordon University,2001
[28] D.Lauzon,A.Vincent,L.wang, Performance Evaluation of MPEG-2 for HDTV,Communications Research Centre,Ottawa,Ontario,Canada,1995
[29] Peter Altenbernd, Lars-Olof Burchard, Friedhelm Stappert, Worst-Case Execution Times Analysis of MPEG-2 Decoding,IEEE,2000
[30] Peter Pirsch, Hans-Joachim Stolberg,VLSI Implementations of Image and Video Multimedia Processing Systems,IEEE, November 1998
[31] Peter Pirsch ,Nicolas Demassieux,Winfried Gehrke,VLSI architectures for video compression-a survey,IEEE,1995
[32] Konstantinos Konstantinides, key components in the design of image and video compression Ics, Hewlett-Packard Laboratories, Computer Peripherals Laboratory Imaging Peripherals Department,IEEE,2002
[33] Matjaz Verderber, Andrej Zemva, Andrej Trost, HW/SW Codesign of the MPEG-2 Video Decoder,IEEE,2003
[34] Abhik Sarkar, Kaushik Saha, Srijib Maiti, Parallel implementation of Mpeg-2 video decoder,IEEE,2003
[35] S.K.Jang,S.D.Kim,J.Lee,G.Y.Choi,J.B.Ra, HW/SW co-implementation of a H.263 video codec,IEEE,2000
[36] Mikael Karlsson Rudberg,Lars Wanhammar, An MPEG-2 video decoder DSP architecture,IEEE,1996
[37] Rick Richmond ,Decode MPEG-2 video with Virtex,www.amphion.com,2003
[38] Seong Mo Park, Miyoung Lee, Seungchul Kim, VLSI Implementation of H.264 Video Decoder, ETRI Journal, Volume 28, Number 4, August 2006
[39] Marlene Wan, Hui Zhang, Varghese George, Design Methodology of aLow-Energy Reconfigurable Single-Chip DSP System, Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley,2000
[40] Anantha P.Chandrakasan,Robert W.Brodersen,Minimizing power consumption in digital CMOS circuits,IEEE,1995
[41] 李方慧,王飞,何佩,TMS320C6000 系列 DSP 原理与应用,北京:电子工业出版社,2003
[42] 钟玉琢,王琪,赵黎,杨小勤,MPEG-2 运动图象压缩编码国际标准及 MPEG的新进展,清华大学出版社,2002
[43] 胡广书,数字信号处理――理论、算法与实现,北京:清华大学出版社,2003
[44] 王诚,薛小刚,钟信潮,FPGA/CPLD 设计工具――Xilinx ISE 5.x 使用详解,人民邮电出版社,2003
[45] 郭斌,MPEG-2 压缩编码技术原理应用,www.dvbcn.com,2004
[46] 陈胜刚,基于“银河飞腾”DSP 的视频采集子系统的设计,国防科技大学研究生院工学硕士论文,湖南长沙,2006
[47] 谷会涛,基于“银河飞腾”DSP 的视频显示子系统的设计,国防科技大学研究生院工学硕士论文,湖南长沙,2006
[48] 王旭辉,高性能视频处理器 YHFT-VDSP 中外部存储器接口的设计与实现,国防科技大学研究生院工学硕士论文,湖南长沙,2006