纳米级电路分辨率增强技术及可制造性设计研究
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摘要
指导集成电路生产发展四十余年的摩尔定律并非物理定律,而是人类创造力的定律,不断发展的科学技术保证了它的持续有效性,尤其是集成电路生产中的关键技术——光刻及分辨率增强技术(Resolution Enhancement Technology, RET)的发展,极大地减小了生产过程中图形失真的情况。基于模型的光学邻近校正技术(Model-Based Optical Proximity Correction, MBOPC)作为应用最为广泛的分辨率增强技术之一,已成为亚波长光刻生产过程中所必须的步骤。反向光刻技术(Inverse Lithography Technology, ILT)被认为是面向45纳米、32纳米乃至22纳米光刻的新一代分辨率增强技术。为设计者和生产者提供交流平台的可制造性设计技术(Design for Manufacturability, DfM)致力于在版图设计阶段即校正版图中可能引发生产时出现问题的地方。本文主要内容及创新点集中在基于模型的光学邻近校正技术、反向光刻技术及可制造性模型建模这三个方面：
光学邻近校正中的基于模型的动态自适应切分技术和校正线段与光强校正点的映射模型。多边形边的切分和校正线段与光强校正点的映射是光学邻近校正中的两个关键步骤。针对切分配置文件越来越难于书写和调试而导致的校正质量下降的问题,本文提出了一种无需配置文件的自动切分方法。该方法通过轮廓采样及相应的计算,切分出与轮廓节奏相符的校正线段,并在校正过程中对校正线段动态调整。校正线段和光强校正点之间简单的一对一关系在纳米级光学邻近校正中已不再适用,针对该问题,本文提出了校正线段与光强校正点之间的映射模型。该模型考察对中心光强变化影响最大的区域,以此来确定映射关系。实验表明,以上两种技术提高了基于模型的光学邻近校正技术的精度,使之在面临纳米级光刻时有较好的表现。
热点感知的反向光刻技术和面向无缝拼接的并行反向光刻技术。反向光刻技术采用优化方法,通过大量的计算得出基于格点的掩模,其具有很高的精度但是非常耗时。本文提出的热点(Hot-spots)感知的反向光刻技术可以在优化过程后期定位热点,在保持非热点版图不变的情况下,单独优化热点版图,减少了计算量,同时可以给出潜在热点的信息。本文提出的面向无缝拼接的反向光刻技术通过在代价函数中加入收敛惩罚项的方法,在获得并行计算所带来的速度优势的同时,很好的解决了环境变化和简单拼接易引发热点的问题。实验表明,以上两种反向光刻技术在提高优化速度的同时保证了质量。
基于卷积核的可制造性模型建模。本文提出了一种基于卷积核的可制造性模型,描述从原始版图到硅片上轮廓这一过程。其卷积核中的元素是通过优化的方法得到,因而该模型具有较大的自由度和较高的精度；建模过程中没有显式的使用工艺参数,因而模型可以发行给设计者；同时该模型可以无需中间步骤直接从原始版图仿真出硅片上轮廓。实现表明,该模型具有较高的精度,使得在设计端进行版图的可制造性验证成为可能。
Moore's Law, which is the guide for IC manufacturing for more than 40 years, is a human creativity law instead of physical law, and continuous development of science and technology keeps Moore's Law continuously valid, especially that the development of lithography and RETs (Resolution Enhancement Technologies), which is the key process of IC manufacturing, greatly reduces the distortion in manufacturing. As one of the most widely used RETs, MB-OPC (Model-Based Optical Proximity Correction) has become an essential step in sub-wavelength lithography. ILT (Inverse Lithography Technology) is believed as a new generation of RETs for 45nm,32nm and even 22nm lithography. DfM (Design for Manufacturability) provides a platform for the communication between designers and manufacturers, and aims at fixing the manufacturing-error-prone spots at the layout design stage. The main contents and innovations of this paper focus on the following three aspects, MB-OPC, ILT and DfM modeling.
Model-based dynamic self-adapting dissection and model-based mapping between segments and correction sites in OPC. Dissection of the polygon edges and the mapping between segments and correction sites are two critical steps in MB-OPC. To ease the quality reduction caused by dissection recipe that is hard to write and debug, a recipe-less and automatic dissection method is proposed in this paper. This method dissects the segments in accord with the rhythm of contour through contour sampling and corresponding calculation, and then adjusts the segments in correction loops. The simple one-to-one mapping between segments and correction sites are not suitable for nano-lithography, and to solve the problem, a mapping model is proposed in this paper. The mapping model inspects the areas that contribute most to the central intensity to determine the mapping. Experiments show that the two techniques improve the accuracy of MB-OPC and make it a better performer in nano-lithography.
Hot-spots aware ILT and seamless-merging-oriented parallel ILT. ILT uses optimization methods to obtain the pixel-based mask through massive calculations, and it is highly accurate but time-consuming. Hot-spots aware ILT proposed in this paper can locate the hot-spots late in the optimization process, and fix the hot-spots layout alone while keeping hot-spots clean layout unchanged to reduce the calculation, and give the information about the latent hot-spots. Seamless-merging-oriented parallel ILT proposed in this paper adds convergence penalty terms in cost function to fix the problem that the changing environment and simple merging may induce hot-spots, while reaping the benefits of high speed inherited from parallel computing. Experiments show that the two kinds of ILT increase the speed without sacrificing the quality.
Modeling of kernel-based DfM model. A new kind of kernel-based DfM model is proposed to describe the process from original layout to silicon contour. The kernel elements in this model are obtained through optimization, thus the model has more freedoms and high accuracy; no process parameters are used in modeling explicitly, so the model can be released to designers; and the contour can be predicted by the model directly from original layout without layout correction steps. Experiments show that the model has good accuracy and makes the DfM check of layout in designer side possible.
光学邻近校正中的基于模型的动态自适应切分技术和校正线段与光强校正点的映射模型。多边形边的切分和校正线段与光强校正点的映射是光学邻近校正中的两个关键步骤。针对切分配置文件越来越难于书写和调试而导致的校正质量下降的问题,本文提出了一种无需配置文件的自动切分方法。该方法通过轮廓采样及相应的计算,切分出与轮廓节奏相符的校正线段,并在校正过程中对校正线段动态调整。校正线段和光强校正点之间简单的一对一关系在纳米级光学邻近校正中已不再适用,针对该问题,本文提出了校正线段与光强校正点之间的映射模型。该模型考察对中心光强变化影响最大的区域,以此来确定映射关系。实验表明,以上两种技术提高了基于模型的光学邻近校正技术的精度,使之在面临纳米级光刻时有较好的表现。
热点感知的反向光刻技术和面向无缝拼接的并行反向光刻技术。反向光刻技术采用优化方法,通过大量的计算得出基于格点的掩模,其具有很高的精度但是非常耗时。本文提出的热点(Hot-spots)感知的反向光刻技术可以在优化过程后期定位热点,在保持非热点版图不变的情况下,单独优化热点版图,减少了计算量,同时可以给出潜在热点的信息。本文提出的面向无缝拼接的反向光刻技术通过在代价函数中加入收敛惩罚项的方法,在获得并行计算所带来的速度优势的同时,很好的解决了环境变化和简单拼接易引发热点的问题。实验表明,以上两种反向光刻技术在提高优化速度的同时保证了质量。
基于卷积核的可制造性模型建模。本文提出了一种基于卷积核的可制造性模型,描述从原始版图到硅片上轮廓这一过程。其卷积核中的元素是通过优化的方法得到,因而该模型具有较大的自由度和较高的精度；建模过程中没有显式的使用工艺参数,因而模型可以发行给设计者；同时该模型可以无需中间步骤直接从原始版图仿真出硅片上轮廓。实现表明,该模型具有较高的精度,使得在设计端进行版图的可制造性验证成为可能。
Moore's Law, which is the guide for IC manufacturing for more than 40 years, is a human creativity law instead of physical law, and continuous development of science and technology keeps Moore's Law continuously valid, especially that the development of lithography and RETs (Resolution Enhancement Technologies), which is the key process of IC manufacturing, greatly reduces the distortion in manufacturing. As one of the most widely used RETs, MB-OPC (Model-Based Optical Proximity Correction) has become an essential step in sub-wavelength lithography. ILT (Inverse Lithography Technology) is believed as a new generation of RETs for 45nm,32nm and even 22nm lithography. DfM (Design for Manufacturability) provides a platform for the communication between designers and manufacturers, and aims at fixing the manufacturing-error-prone spots at the layout design stage. The main contents and innovations of this paper focus on the following three aspects, MB-OPC, ILT and DfM modeling.
Model-based dynamic self-adapting dissection and model-based mapping between segments and correction sites in OPC. Dissection of the polygon edges and the mapping between segments and correction sites are two critical steps in MB-OPC. To ease the quality reduction caused by dissection recipe that is hard to write and debug, a recipe-less and automatic dissection method is proposed in this paper. This method dissects the segments in accord with the rhythm of contour through contour sampling and corresponding calculation, and then adjusts the segments in correction loops. The simple one-to-one mapping between segments and correction sites are not suitable for nano-lithography, and to solve the problem, a mapping model is proposed in this paper. The mapping model inspects the areas that contribute most to the central intensity to determine the mapping. Experiments show that the two techniques improve the accuracy of MB-OPC and make it a better performer in nano-lithography.
Hot-spots aware ILT and seamless-merging-oriented parallel ILT. ILT uses optimization methods to obtain the pixel-based mask through massive calculations, and it is highly accurate but time-consuming. Hot-spots aware ILT proposed in this paper can locate the hot-spots late in the optimization process, and fix the hot-spots layout alone while keeping hot-spots clean layout unchanged to reduce the calculation, and give the information about the latent hot-spots. Seamless-merging-oriented parallel ILT proposed in this paper adds convergence penalty terms in cost function to fix the problem that the changing environment and simple merging may induce hot-spots, while reaping the benefits of high speed inherited from parallel computing. Experiments show that the two kinds of ILT increase the speed without sacrificing the quality.
Modeling of kernel-based DfM model. A new kind of kernel-based DfM model is proposed to describe the process from original layout to silicon contour. The kernel elements in this model are obtained through optimization, thus the model has more freedoms and high accuracy; no process parameters are used in modeling explicitly, so the model can be released to designers; and the contour can be predicted by the model directly from original layout without layout correction steps. Experiments show that the model has good accuracy and makes the DfM check of layout in designer side possible.
引文
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