基于FPGA的NoC通讯架构的设计与测试
摘要
随着微电子技术的发展,超大规模集成电路的集成度越来越高,基于片上总线的SoC(System-on-a-Chip)在设计上遇到了全局时钟难以同步、地址空间有限、无法支持多节点并行通讯与系统扩展不够灵活等问题,严重制约了集成在单一芯片上SoC的规模及系统性能。片上网络(Network-on-Chip,NoC)将计算机宏观网络技术移植到芯片设计中来,采用由虫孔交换的路由机制组成的通讯架构来代替传统的总线架构,实现处理单元(IP核)之间的互联通信,从体系结构上解决了SoC总线架构带来的问题。NoC具有良好的空间可扩展性,低传输功耗和低延迟的特点,并具备良好的并行通讯能力。
论文的主要工作正是为了验证NoC通讯架构的有效性,本文基于2D-Mesh拓扑结构展开研究,重点介绍了基于FPGA(Filed Programmable Gate Array)的NoC通讯架构的设计与测试。论文的工作主要包括三个方面:( 1) NoC通讯架构总体设计、IP核的添加以及内部模块的设计,其中NoC通讯架构内部模块主要包括路由器模块和资源网络接口(Resource-Network-Interface,RNI)模块以及通讯链路;(2)FPGA的概念介绍,重点描述了FPGA开发软件QuartusⅡ的设计流程以及基于FPGA的NoC的设计方法;(3)利用相关的综合测试软件对NoC通讯架构的设计分别进行详细的测试与性能分析。
为了实现NoC架构的实际应用,我们搭建了基于FPGA的一种简单的2D-Mesh NoC通讯架构平台,通过添加相应的IP核实现两个ROM核中的数据传输到加法器核中相加,然后将运算结果存储到RAM核中。在此基础上给出了NoC架构中所有模块的结构设计与验证过程、数据包格式定义、并对各模块进行了必要的面积综合、功耗分析以及时序约束与时序分析,最后确定能够将整个NoC架构下载到FPGA开发板中进行实际验证。
With the development of the microelectronics technology, the integrity of very large scale integrated circuit is getting higher and higher. SoC has to be designed with global clock synchronization, limited address space, unparallel communicate- on among multiple nodes and inflexible extension enough which has restricted in the scale and performance capabilities seriously in a single chip. NoC has been put forward the idea of the computer network technology to migrate to chip design. The IP cores communicate with each other by the wormholes exchange routing mechanism which has replaced the traditional bus architecture. NoC can solve the problems posed by the bus architecture. Besides, NoC has good expansibility, low transmission power consumption, low latency and parallel communication ability.
This thesis is mainly targeted on verifying the effectiveness of the communication structure on the NoC. This have studied topology structure based on 2D-Mesh and the design and test methods about communication architecture based on FPGA of NoC. This thesis mainly includes three aspects: (1) the communication architecture to design on the NoC, the IP cores to add and the internal module to design. The internal module of NoC mainly include router, resource-network-inter- face and interconnects. (2) we have introduced the concept of FPGA, the design of software QuartusⅡdevelopment process and the NoC based on FPGA.(3) we use the related comprehensive software to test and verify the communication architecture and evaluate the performance of the NoC.
In order to realize the practical application on the NoC, It have built a communication structure terrace of 2D-Mesh based on FPGA. We have accomplish- ed the data transferred and added in two ROM and saved the result into RAM by adding two IP cores. It have given the structural design, the verification process and the packet format defined about all modules on the NoC. Further more, This have given the area of the necessary comprehensive of all modules, power analysis, timing constraints and time-series analysis. It can verify the NoC architecture by downloading all to FPGA developing board.
论文的主要工作正是为了验证NoC通讯架构的有效性,本文基于2D-Mesh拓扑结构展开研究,重点介绍了基于FPGA(Filed Programmable Gate Array)的NoC通讯架构的设计与测试。论文的工作主要包括三个方面:( 1) NoC通讯架构总体设计、IP核的添加以及内部模块的设计,其中NoC通讯架构内部模块主要包括路由器模块和资源网络接口(Resource-Network-Interface,RNI)模块以及通讯链路;(2)FPGA的概念介绍,重点描述了FPGA开发软件QuartusⅡ的设计流程以及基于FPGA的NoC的设计方法;(3)利用相关的综合测试软件对NoC通讯架构的设计分别进行详细的测试与性能分析。
为了实现NoC架构的实际应用,我们搭建了基于FPGA的一种简单的2D-Mesh NoC通讯架构平台,通过添加相应的IP核实现两个ROM核中的数据传输到加法器核中相加,然后将运算结果存储到RAM核中。在此基础上给出了NoC架构中所有模块的结构设计与验证过程、数据包格式定义、并对各模块进行了必要的面积综合、功耗分析以及时序约束与时序分析,最后确定能够将整个NoC架构下载到FPGA开发板中进行实际验证。
With the development of the microelectronics technology, the integrity of very large scale integrated circuit is getting higher and higher. SoC has to be designed with global clock synchronization, limited address space, unparallel communicate- on among multiple nodes and inflexible extension enough which has restricted in the scale and performance capabilities seriously in a single chip. NoC has been put forward the idea of the computer network technology to migrate to chip design. The IP cores communicate with each other by the wormholes exchange routing mechanism which has replaced the traditional bus architecture. NoC can solve the problems posed by the bus architecture. Besides, NoC has good expansibility, low transmission power consumption, low latency and parallel communication ability.
This thesis is mainly targeted on verifying the effectiveness of the communication structure on the NoC. This have studied topology structure based on 2D-Mesh and the design and test methods about communication architecture based on FPGA of NoC. This thesis mainly includes three aspects: (1) the communication architecture to design on the NoC, the IP cores to add and the internal module to design. The internal module of NoC mainly include router, resource-network-inter- face and interconnects. (2) we have introduced the concept of FPGA, the design of software QuartusⅡdevelopment process and the NoC based on FPGA.(3) we use the related comprehensive software to test and verify the communication architecture and evaluate the performance of the NoC.
In order to realize the practical application on the NoC, It have built a communication structure terrace of 2D-Mesh based on FPGA. We have accomplish- ed the data transferred and added in two ROM and saved the result into RAM by adding two IP cores. It have given the structural design, the verification process and the packet format defined about all modules on the NoC. Further more, This have given the area of the necessary comprehensive of all modules, power analysis, timing constraints and time-series analysis. It can verify the NoC architecture by downloading all to FPGA developing board.
引文
[1] W. J. Daly and B. Towles."Route Packets, Not Wires: On-Chip Interconnection Networks."[C], In DAC, Jun. 2001.
[2] L. Benini and G. D. Micheli."Networks on chips: a new soc paradigm."[J], IEEE Computer, January 2002, pages 70–78.
[3] Semiconductor Industry Association. International Technology Roadmap for Semiconductors 2003 Edition Executive Summary, 2003.
[4]周干民. NoC基础研究[D] .合肥:合肥工业大学博士学位论文. 2005.
[5] Benini L, De Micheli G. Networks on chips: a new SoC paradigm [J]. Computer, 2002, 35 (1), PP:70-78.
[6] Jerraya A, Wolf W, eds. Multiprocessor systems-on-chips [M]. San Francisco, Morgan Kaufman / Elsevier, 2004.
[7] A. Hemani , S. Kumar, A. Postula , J.Oberg , M. Millberg, D. Lindqvist. An architecture for billion transistor era[J]. In Proceeding of the IEEE NoC-Chip Conference , November 2000.
[8] Guerrier P, Grenier A. A generic architecture for on-chip packet-switched interconnections [C]. Des Automand Test in Euro Conf. Paris , France. 2000, PP:250-256.
[9] Adrijean Adriallantenalna, Herve Charlery, Alain Greinerr, et al. SPIN: A Scalable Packet Switched On-Chip Mico-Network [J]. Proceedings of the conference on Design, Automation and Test in Europe: Dsigner’s Forum, March, 2003, PP;70-73.
[10] Davide Bertozzi and Luca Benini. X-pipes: A Network-on-Chip Architecture for Giga-scale Systems-on-Chip [J]. IEEE Circuits and Systems Magazine, 4, 2004,pp:18-31.
[11] Zhang hai Lu, Rikd Thid, Mikael Millbeg, et al. NNES: Nostrum Network on Chip simulation environment [J]. In Swedish System-on-Chip Conference (SSoCC’03), April 2005, pp:1-4.
[12] Mikael Millbeg, Erland Nilsson, Rikard Thid, et al. The Nostrum backbone a communication protocol stack for networks on chip [J]. In Proceedings of the VLSL Design Conference, Mumbai, India, January 2004, pp: 693-696.
[13] W. J. Bainbridge and S. B. Furber. CHAIN: A D-lay Insensitive Chip Area Interconnect [J]. IEEE Mico special issue on Design and Test of System on Chip, 142, No.4, September 2002, pp: 16-23.
[14] Pham D. The design and implementation of a first-generation CELL processor [C]. Int Sol Sta Circ Conf. San Francisco, CA, USA. 2005,pp:184-185.
[15] Glossner G. The sand bridge sandblaster SB3000 multithreaded CMP platform [C]. 5th Int Forum Appl Spec Multi-Processor SoC. Relais de Margaux, France. 2005, pp: 18-23.
[16] J. Huand, R. Marculescu. Energy and performance aware mapping for regular NoC architectures [J]. IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems.
[17] Umit Y. Ogras, Jingcao Hu, and Radu Marculescu. Key research problems in NoC design:A holistic perspective [J]. Proceedings of the International Conference on Hardware/software Codesign and System Synthesis, 2005.
[18] Shashi Kumar, Axel Jantsch, et a1A network on chip architecture and design methodology[J]. in Proc.Int’s Symp.VLSI(ISVLSI),2002,pp: l17-124.
[19] HAN Yin-He, LI Xiao-Wei, XU Yong-Jun, et al. System-on-a-Chip Test-Data Coding Compression Technology [J]. Microelectronics & Computer, 2003, 20(2): 44-47(in Chinese).
[20] JoséDuato, Stuhakar Yalamanchili, Lionel Ni. Interconnection Networks: An Engineering Approach [M]. Beijing: Publishing House of Electronics Industry, 2004.
[21] S. Kumar, A. Jantsch, J. Soininen, M. Forsell. A networks on chip architecture and design methodology [J], Proceedings of IEEE Computer SocietyAnnual Symposium on VLSI. 2002: 105 - 112.
[22] W. Dally, B. Towles. Route Packets, NotWires: On-Chip Interconnection Networks[C], Proceedings. the 38th Design Automation Conference, 2001 (6) : 684 - 689.
[23] Rashinkar P.System-On-a-Chip Verification Methodology and Techniques [M].USA: Kluwer Academic Publishers, 2001: 6- 10.
[24] Sarbazi-Azad, H.Ould-Khaoua, M.Mackenzie, L.M.Performance analysis of k-ary n-cubes with fully adaptive routing Parallel and Distributed Systems[C], 2000. Proceedings. Seventh International Conference on Publication Date: 2000 : 249-255.
[25] Leiserson, Fat-trees: Universal Networks for Hardware-Efficient Supercomputing [J], IEEE Transactions on Computers, 34(10), 1985: 892-901.
[26] F. Karim et al. An Interconnect Architecture for Networking Systems on Chips [J], IEEE Micro, 22(5), 2002: 36- 45.
[27] Marcello Coppola, Riccardo Locatelli, Giuseppe Maruccia, et al, Spidergon: a novel on- chip communication network[C], System-on-Chip, 2004. Proceedings. 2004 International Symposiumon, 2004: 15-18.
[28] P. Guerrier and A. Greiner, A Generic Architecture for On- Chip Packet- Switched Interconnections, Design, Automation and Test in Europe Conference and Exhibition 2000[C]. Proceedings, 2000: 250- 256.
[29] T. Ahonen , D.S.Tortosa, and J.Nurmi. Topology optimization for application-specific networks-on-chip [J]. In Proc. 6th International Workshop on System Level Interconnect Prediction, Paris, 2004: 8.
[30] Tobias. B and Shankar M. A survey of research and practices of Network on Chip [J]. ACM Computing Surveys , 2006, 38(l),pp:1-54.
[31] Shashi Kumar, Axel Jantsch, et a1A network on chip architecture and design methodology[J]. in Proc.Int’s Symp.VLSI(ISVLSI),2002,pp: l17-124.
[32] E.Bolotin, I.Cidon,R.Ginosar and A.Kolodny. QNoC: QoS architecture and design process for network on chip[J].Journal of Systems Architecture,special issue on Network on Chip,50,February 2004,pp:105—128.
[33]吴继华,王诚,范丽珍,薛小刚等.Altera FPGA/CPLD设计(基础版)[M].北京:人民邮电出版社,2005.
[34]吴继华,王诚.Altera FPGA/CPLD设计(高级版)[M].北京:人民邮电出版社,2005.
[35] Chris Rowen.Engineering the Complex SoC:Fast,Flexible Design with Configurable Processors[M],Prentice Hall PTR,2004:90-93.
[36] Ran Ginosar, Fourteen Ways to Fool Your Synchronizer[C], In Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems, 2003.
[37]董少周.NoC路由算法及仿真模型的设计与研究[D].合肥:合肥工业大学硕士学位论文.2009.
[38]葛亚明,彭永丰,薛冰等.零基础学FPGA[M].北京:机械工业出版社,2010.
[39] Wu Ning, Ge Fen, Wang Qi. Simulation and performance analysis of network on chip architectures using OPNET [C]. ASIC, 2007.7th International Conference on,Oct.2007 pp:1285– 1288.
[40] Everton Carara, Fernando Moraes, Ney Calazans, Router architecture for high-performance NoCs[C], In Proceedings of the 20th annual conference on Integrated circuits and systems design, 2007: 111-116.
[2] L. Benini and G. D. Micheli."Networks on chips: a new soc paradigm."[J], IEEE Computer, January 2002, pages 70–78.
[3] Semiconductor Industry Association. International Technology Roadmap for Semiconductors 2003 Edition Executive Summary, 2003.
[4]周干民. NoC基础研究[D] .合肥:合肥工业大学博士学位论文. 2005.
[5] Benini L, De Micheli G. Networks on chips: a new SoC paradigm [J]. Computer, 2002, 35 (1), PP:70-78.
[6] Jerraya A, Wolf W, eds. Multiprocessor systems-on-chips [M]. San Francisco, Morgan Kaufman / Elsevier, 2004.
[7] A. Hemani , S. Kumar, A. Postula , J.Oberg , M. Millberg, D. Lindqvist. An architecture for billion transistor era[J]. In Proceeding of the IEEE NoC-Chip Conference , November 2000.
[8] Guerrier P, Grenier A. A generic architecture for on-chip packet-switched interconnections [C]. Des Automand Test in Euro Conf. Paris , France. 2000, PP:250-256.
[9] Adrijean Adriallantenalna, Herve Charlery, Alain Greinerr, et al. SPIN: A Scalable Packet Switched On-Chip Mico-Network [J]. Proceedings of the conference on Design, Automation and Test in Europe: Dsigner’s Forum, March, 2003, PP;70-73.
[10] Davide Bertozzi and Luca Benini. X-pipes: A Network-on-Chip Architecture for Giga-scale Systems-on-Chip [J]. IEEE Circuits and Systems Magazine, 4, 2004,pp:18-31.
[11] Zhang hai Lu, Rikd Thid, Mikael Millbeg, et al. NNES: Nostrum Network on Chip simulation environment [J]. In Swedish System-on-Chip Conference (SSoCC’03), April 2005, pp:1-4.
[12] Mikael Millbeg, Erland Nilsson, Rikard Thid, et al. The Nostrum backbone a communication protocol stack for networks on chip [J]. In Proceedings of the VLSL Design Conference, Mumbai, India, January 2004, pp: 693-696.
[13] W. J. Bainbridge and S. B. Furber. CHAIN: A D-lay Insensitive Chip Area Interconnect [J]. IEEE Mico special issue on Design and Test of System on Chip, 142, No.4, September 2002, pp: 16-23.
[14] Pham D. The design and implementation of a first-generation CELL processor [C]. Int Sol Sta Circ Conf. San Francisco, CA, USA. 2005,pp:184-185.
[15] Glossner G. The sand bridge sandblaster SB3000 multithreaded CMP platform [C]. 5th Int Forum Appl Spec Multi-Processor SoC. Relais de Margaux, France. 2005, pp: 18-23.
[16] J. Huand, R. Marculescu. Energy and performance aware mapping for regular NoC architectures [J]. IEEE Trans. On Computer-Aided Design of Integrated Circuits and Systems.
[17] Umit Y. Ogras, Jingcao Hu, and Radu Marculescu. Key research problems in NoC design:A holistic perspective [J]. Proceedings of the International Conference on Hardware/software Codesign and System Synthesis, 2005.
[18] Shashi Kumar, Axel Jantsch, et a1A network on chip architecture and design methodology[J]. in Proc.Int’s Symp.VLSI(ISVLSI),2002,pp: l17-124.
[19] HAN Yin-He, LI Xiao-Wei, XU Yong-Jun, et al. System-on-a-Chip Test-Data Coding Compression Technology [J]. Microelectronics & Computer, 2003, 20(2): 44-47(in Chinese).
[20] JoséDuato, Stuhakar Yalamanchili, Lionel Ni. Interconnection Networks: An Engineering Approach [M]. Beijing: Publishing House of Electronics Industry, 2004.
[21] S. Kumar, A. Jantsch, J. Soininen, M. Forsell. A networks on chip architecture and design methodology [J], Proceedings of IEEE Computer SocietyAnnual Symposium on VLSI. 2002: 105 - 112.
[22] W. Dally, B. Towles. Route Packets, NotWires: On-Chip Interconnection Networks[C], Proceedings. the 38th Design Automation Conference, 2001 (6) : 684 - 689.
[23] Rashinkar P.System-On-a-Chip Verification Methodology and Techniques [M].USA: Kluwer Academic Publishers, 2001: 6- 10.
[24] Sarbazi-Azad, H.Ould-Khaoua, M.Mackenzie, L.M.Performance analysis of k-ary n-cubes with fully adaptive routing Parallel and Distributed Systems[C], 2000. Proceedings. Seventh International Conference on Publication Date: 2000 : 249-255.
[25] Leiserson, Fat-trees: Universal Networks for Hardware-Efficient Supercomputing [J], IEEE Transactions on Computers, 34(10), 1985: 892-901.
[26] F. Karim et al. An Interconnect Architecture for Networking Systems on Chips [J], IEEE Micro, 22(5), 2002: 36- 45.
[27] Marcello Coppola, Riccardo Locatelli, Giuseppe Maruccia, et al, Spidergon: a novel on- chip communication network[C], System-on-Chip, 2004. Proceedings. 2004 International Symposiumon, 2004: 15-18.
[28] P. Guerrier and A. Greiner, A Generic Architecture for On- Chip Packet- Switched Interconnections, Design, Automation and Test in Europe Conference and Exhibition 2000[C]. Proceedings, 2000: 250- 256.
[29] T. Ahonen , D.S.Tortosa, and J.Nurmi. Topology optimization for application-specific networks-on-chip [J]. In Proc. 6th International Workshop on System Level Interconnect Prediction, Paris, 2004: 8.
[30] Tobias. B and Shankar M. A survey of research and practices of Network on Chip [J]. ACM Computing Surveys , 2006, 38(l),pp:1-54.
[31] Shashi Kumar, Axel Jantsch, et a1A network on chip architecture and design methodology[J]. in Proc.Int’s Symp.VLSI(ISVLSI),2002,pp: l17-124.
[32] E.Bolotin, I.Cidon,R.Ginosar and A.Kolodny. QNoC: QoS architecture and design process for network on chip[J].Journal of Systems Architecture,special issue on Network on Chip,50,February 2004,pp:105—128.
[33]吴继华,王诚,范丽珍,薛小刚等.Altera FPGA/CPLD设计(基础版)[M].北京:人民邮电出版社,2005.
[34]吴继华,王诚.Altera FPGA/CPLD设计(高级版)[M].北京:人民邮电出版社,2005.
[35] Chris Rowen.Engineering the Complex SoC:Fast,Flexible Design with Configurable Processors[M],Prentice Hall PTR,2004:90-93.
[36] Ran Ginosar, Fourteen Ways to Fool Your Synchronizer[C], In Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems, 2003.
[37]董少周.NoC路由算法及仿真模型的设计与研究[D].合肥:合肥工业大学硕士学位论文.2009.
[38]葛亚明,彭永丰,薛冰等.零基础学FPGA[M].北京:机械工业出版社,2010.
[39] Wu Ning, Ge Fen, Wang Qi. Simulation and performance analysis of network on chip architectures using OPNET [C]. ASIC, 2007.7th International Conference on,Oct.2007 pp:1285– 1288.
[40] Everton Carara, Fernando Moraes, Ney Calazans, Router architecture for high-performance NoCs[C], In Proceedings of the 20th annual conference on Integrated circuits and systems design, 2007: 111-116.