可进化硬件平台研究
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摘要
可进化硬件(EHWW)能够模拟生物进化过程,在进化算法的指导下进行自重构而接近目标功能,在电路设计、自适应系统等领域有着广泛的应用前景。EHW技术虽然经过了近二十年的发展,但在如何根据应用需求提供层次化的研究平台、有效地对个体进行评估、提高进化速度及规模等方面还存在很大探索空间。
本文基于课题组自主FPGA技术,关注不同层次、不同粒度的可进化硬件平台对可重构技术、进化算法及评估策略的需求,研究了LUT(查找表)级、模块级、芯片级与网络级四种可进化硬件平台。
首先,基于课题组自主研发的FPGA芯片建立了LUT级可进化硬件平台,为此平台开发了一种可防止进化停滞的进化算法；设计了LUT级可重构电路,统一了组合逻辑与时序逻辑的进化流程,并提供了自适应评估算法对电路进行评估。实验表明,此平台比已有报道中的同类平台进化速度快十倍以上。
然后,基于自主FPGA芯片,进一步研究了模块级可进化硬件平台,重点研究其核心需求：模块级部份动态可重构硬件。为此创新设计了一种基于纵向CLB的传输线宏,提供了相应的工具链,并开发了部分动态可重构图像滤波器演示系统。实验表明,该演示系统中硬件电路可在50毫秒内完成模块级重构,适应模块级可进化硬件平台的核心需求。
再者,为了进一步提高进化速度,研究了一种芯片级可进化硬件平台。此平台以自主设计的集成了CPU核和FPGA核的可编程芯片为主体。在芯片设计时,开发了一种快速重构配置技术,可显著减少重构操作所需的时间；提供了针对不同适应度评估方案的数据交互接口,提高系统可靠性和灵活性；通过硬件加速的方法实现了遗传算法加速。此平台上的进化实验结果表明,进化速度比已有文献中的示例快一个数量级。
最后,为了提供更高效的模块级进化方案,将自主FPGA技术与片上网络(NOC)技术相结合,研究了一种网络级可进化硬件平台,其核心是一种以多个FPGA核为网络节点的可重构NOC芯片,通过对片上路由器及网络资源接口进行创新设计,使此网络级平台支持网络结构可重构以及网络节点可重构两种特性。仿真和FPGA验证结果表明,此平台原型功能正确,且支持平均每节点每周期每点向网络注入0.7个数据。
Evolvable Hardware (EHW) simulates the biological evolution in nature. It can evolve towards a target function with the guidance of the evolutionary algorithm (EA). It can be promising in the fields such as automated design of circuits and adaptive systems. Being developing for almost 20 years, EHW is still seeking for better platform with different granularity. Solutions for better evaluation strategy, higer evolving speed and larger evolving scale are still to be studied.
Based on self developed FPGA technologies, this thesis focuses on solutions for muti-level EHW platforms, provides reconfigurable capacity in different granularities, proper EA and tool chains. Solutions for LUT (look up table) level, module level, on-Chip level and network level EHW platforms are proposed here.
Firstly, based on the FDP FPGA chip designed on our own, an LUT level EHW platform is proposed. An EA that can keep evolving from stagnated is provided on this platform. A new structure of reconfigurable circuit is presented, which can be used for evolving combination logic and sequential logic. And an adaptive evaluation algorithm is used. The experiment result shows that the proposed EHW platform outperforms the previously proposed platform by 10 times of evolving speed.
Secondly, module level EHW platform is studied. And the emphasis goes to its key requirement:the partially and dynamically recofonfigurable (PDR) hardware. A novel Transfer-Bus macro is proposed to provide PDR capacity. The tool chain for PDR system design is also provided. A PDR image filter was developed and the result shows that less than 50 ms are needed for modular replacement, meeting the main requirements of the module level EHW platform.
Thirdly, to further improve the speed of evolution, an SOC chip is designed to build an on-chip level EHW platform. The SOC chip proposed here was integrated with a CPU IP and an FPGA IP. A fast self-reconfiguration technology was introduced to accelerate the reconfiguration; according to the requirements for different fitness evaluation strategies, a dedicated data-exchange interface was designed to provide a more flexible and robust platform; to accelerate the EA, a hardware random number generator (RNG) was designed to provide random numbers. Experiment results show that these proposed technology speeds up the whole platform in an order of magnitude.
Lastly, to provide a platform with better modularization capacity, a network level EHW platform is proposed. The main solution for network level EHW platform is a reconfigurable "network on chip" (NOC) prototype. The key modules of the NOC chip are designed to provide two features:reconfigurable network topology and reconfigurable nodes.Simulation and FPGA validation show that the proposed NOC prototype functions correctly and the network can support a maxium throughput of injecting 0.7 packets of data per node per cycle in a set pattern.
本文基于课题组自主FPGA技术,关注不同层次、不同粒度的可进化硬件平台对可重构技术、进化算法及评估策略的需求,研究了LUT(查找表)级、模块级、芯片级与网络级四种可进化硬件平台。
首先,基于课题组自主研发的FPGA芯片建立了LUT级可进化硬件平台,为此平台开发了一种可防止进化停滞的进化算法；设计了LUT级可重构电路,统一了组合逻辑与时序逻辑的进化流程,并提供了自适应评估算法对电路进行评估。实验表明,此平台比已有报道中的同类平台进化速度快十倍以上。
然后,基于自主FPGA芯片,进一步研究了模块级可进化硬件平台,重点研究其核心需求：模块级部份动态可重构硬件。为此创新设计了一种基于纵向CLB的传输线宏,提供了相应的工具链,并开发了部分动态可重构图像滤波器演示系统。实验表明,该演示系统中硬件电路可在50毫秒内完成模块级重构,适应模块级可进化硬件平台的核心需求。
再者,为了进一步提高进化速度,研究了一种芯片级可进化硬件平台。此平台以自主设计的集成了CPU核和FPGA核的可编程芯片为主体。在芯片设计时,开发了一种快速重构配置技术,可显著减少重构操作所需的时间；提供了针对不同适应度评估方案的数据交互接口,提高系统可靠性和灵活性；通过硬件加速的方法实现了遗传算法加速。此平台上的进化实验结果表明,进化速度比已有文献中的示例快一个数量级。
最后,为了提供更高效的模块级进化方案,将自主FPGA技术与片上网络(NOC)技术相结合,研究了一种网络级可进化硬件平台,其核心是一种以多个FPGA核为网络节点的可重构NOC芯片,通过对片上路由器及网络资源接口进行创新设计,使此网络级平台支持网络结构可重构以及网络节点可重构两种特性。仿真和FPGA验证结果表明,此平台原型功能正确,且支持平均每节点每周期每点向网络注入0.7个数据。
Evolvable Hardware (EHW) simulates the biological evolution in nature. It can evolve towards a target function with the guidance of the evolutionary algorithm (EA). It can be promising in the fields such as automated design of circuits and adaptive systems. Being developing for almost 20 years, EHW is still seeking for better platform with different granularity. Solutions for better evaluation strategy, higer evolving speed and larger evolving scale are still to be studied.
Based on self developed FPGA technologies, this thesis focuses on solutions for muti-level EHW platforms, provides reconfigurable capacity in different granularities, proper EA and tool chains. Solutions for LUT (look up table) level, module level, on-Chip level and network level EHW platforms are proposed here.
Firstly, based on the FDP FPGA chip designed on our own, an LUT level EHW platform is proposed. An EA that can keep evolving from stagnated is provided on this platform. A new structure of reconfigurable circuit is presented, which can be used for evolving combination logic and sequential logic. And an adaptive evaluation algorithm is used. The experiment result shows that the proposed EHW platform outperforms the previously proposed platform by 10 times of evolving speed.
Secondly, module level EHW platform is studied. And the emphasis goes to its key requirement:the partially and dynamically recofonfigurable (PDR) hardware. A novel Transfer-Bus macro is proposed to provide PDR capacity. The tool chain for PDR system design is also provided. A PDR image filter was developed and the result shows that less than 50 ms are needed for modular replacement, meeting the main requirements of the module level EHW platform.
Thirdly, to further improve the speed of evolution, an SOC chip is designed to build an on-chip level EHW platform. The SOC chip proposed here was integrated with a CPU IP and an FPGA IP. A fast self-reconfiguration technology was introduced to accelerate the reconfiguration; according to the requirements for different fitness evaluation strategies, a dedicated data-exchange interface was designed to provide a more flexible and robust platform; to accelerate the EA, a hardware random number generator (RNG) was designed to provide random numbers. Experiment results show that these proposed technology speeds up the whole platform in an order of magnitude.
Lastly, to provide a platform with better modularization capacity, a network level EHW platform is proposed. The main solution for network level EHW platform is a reconfigurable "network on chip" (NOC) prototype. The key modules of the NOC chip are designed to provide two features:reconfigurable network topology and reconfigurable nodes.Simulation and FPGA validation show that the proposed NOC prototype functions correctly and the network can support a maxium throughput of injecting 0.7 packets of data per node per cycle in a set pattern.
引文
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[2]Stoica Adrian.,Zebulum R.,Keymeulen D..Progress and challenges in building evolvable device[A].In:Proceedings of The Third NASA/DoD Workshop on, Evolvable Hardware[C]. Piscataway, United States:IEEE,2001:33.
[3]Mange D,Sipper M,Stauffer A, Toward self-Repairing and self-replicating hardware:the embryonics apporach[A].In:Proceedings of The 2nd NASA/DoD workshop on Evolvable Hardware[C]. Palo Alto, CA, USA,2000,205-214.
[4]T. Higuchi, M. Iwata,1. Kajitani. Evolvable Hardware with Genetic Learning[A].In:Proceedings of the IEEE International Symposium on Circuits and Systems Vol.4 [C].Piscataway, United States:IEEE,1996:29-32.
[5]T. Higuchi, M. Iwata, I. Kajitani.Evolvable Hardware and its Applications to Pattern Recognition and Fault-tolerant System[J]. Towards Evolvable Hardware:The Evolutionary Engineering Approach (Lecture Notes in Computer Science).Springer-Verlag,1996, Vol. 1062:118-135.
[6]T. Higuchi. Real-World Applications of Analog and Digital Evolvable Hardware[J]. IEEE Transaction on Evolutionary Computation.1999,3 (3),220-235.
[7]S. Thorsten, X. Yao. Using Negative Correlation to Evolve Fault-Tolerant Circuits[A].In:The 5th International Conference on Evolvable Systems[C]. Trondheim, Norway, 2003:35-46.
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