可重构指令集处理器设计中的软件重定向关键技术研究
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摘要
电子信息技术、网络技术和硬件工艺的迅猛发展使得计算机系统越来越复杂。新应用领域的兴起对程序与计算能力提出了越来越严格的要求,多变的用户群体使得处理器的执行任务具有了高动态性的特点,而传统的基于静态指令集设计的处理器已经无法满足这类需要兼顾性能和灵活性两方面因素的应用需求。为了能够高效地适应用户动态变化的任务需求,可重构指令集处理器应运而生。
可重构指令集处理器将可重构技术应用到专用指令集处理器的实现中,利用可重构逻辑器件的硬件可编程性,针对不同的应用特征自适应地定制其最优的执行环境,从而在保有专用指令集处理器优点的前提下更有效地满足嵌入式领域的不同应用要求。由于可重构指令集处理器的指令集能够在设计完成后根据应用程序特点进行动态更改,与传统的固定指令集的处理器设计有很大的不同。这就使得针对传统处理器设计的软件工具链不适合于可重构指令集处理器应用程序的开发,需要有新的设计方法用于构造适应动态指令集特征的工具链,以便充分挖掘系统的处理性能。
本文针对上述的问题,以所设计的支持动态剖析的可重构指令集处理器为基础平台,提出了一个能够实现软件工具链可重定向设计的开发方案。该方案在对应用程序进行初始快速编译后利用仿真器执行二进制代码,通过对执行信息的剖析、映射等过程获得处理器的扩展指令集合。然后利用新的指令集体系结构完成对编译器和仿真器的可重定向扩展,实现对应用程序的优化编译。所提出的方案能够保证所设计的可重构指令集处理器在针对不同应用任务进行指令定制和硬件重构后,其上层应用程序开发模式的一致性和可重用性,满足对应用程序的兼容性要求,从而能够提高开发效率,降低开发人员的负担,并且对新的嵌入式处理器的开发设计和仿真评估具有积极的意义。
在所设计的软件工具链可重定向开发方案中,剖析机制和编译代码生成是整个方案的核心问题,而这两者之间的联系在于实现动态指令序列与静态代码结构的映射匹配。因此,为了实现针对可重构指令集处理器体系结构的工具链可重定向设计,快速有效地生成能够高性能执行的二进制代码,本文深入地研究了软件工具链可重定向开发方案中的三个关键技术,包括高效的热点动态剖析技术、热点代码映射匹配机制和编译后端可重定向实现。
本论文的主要贡献体现在下述几个方面：
1)提出了一种适合所设计的具有动态剖析特性的可重构指令集处理器的软件工具链可重定向开发方案,融合了热点剖析、动静代码映射及编译后端重定向等关键技术,能很好地适应动态变化的软硬件环境,提高开发效率。
2)研究了一种基于路径剖析的可配置热点剖析机制。其与处理器松散耦合,不需了解处理器微体系结构信息而完成剖析。同时,兼具对全过程剖析和采样剖析的支持,能够针对不同的应用需求而采取不同的剖析方案,使得用户可以权衡剖析准确度和剖析开销两方面的因素而作出选择。
3)研究了一种基于代数多项式表示的动-静代码映射匹配算法。该算法利用代数多项式来表示代码中的基本块乃至函数体与循环体等结构,在此基础上结合串匹配和多层次搜索的思想,通过多项式搜索匹配的方法实现动态序列表示与静态代码多项式集合的映射匹配,进而用于对源代码的注释标识。
4)研究了一个扩展传统编译后端代码生成三阶段方法的代码混合优化生成算法。该算法能够根据可用资源情况和系统重构配置针对可重构指令的代码生成进行优化处理,获得切合平台特性的可执行程序,并且很大程度地复用原有三阶段方法中对基本指令集的代码生成算法,简化了实现的复杂度。
Computer system has been more complicated because of the rapid development of electronic, network and hardware technique. With the emergence of new applications and varied user requirements, the programmability and calculability of processors become more and more challenging. The conventional processor design based on static instruction sets can't achieve the requirements on both of performance and flexibility. So the reconfigurable instruction set processor (RISP) emerged.
RISP is the application specific instruction-set processor combined with reconfiguration technology. Through the programmability of reconfigurable arrays, RISP can custom the best appropriate environment for a special application executing, so that it can efficiently meet diverse requirements in the embedded domain. RISP is very different from the conventional processor that its instruction set can be modified when executing, and so the software tools which are designed for the conventional processor don't adapt to code generation of RISP. To take full advantage of the performance of RISP, the new software tools design methodology for fitting dynamic instruction sets is needed.
According to the above, this dissertation presents a design flow of retargetable software tools development environment (RSTDE) based on our RISP framework named DP-RISP which supports dynamic profiling. RSTDE profiles the simulating execution of applications, generates new extended reconfigurable instructions and maps them to source codes. Then it retargets compiler and simulator with the new instructions to generate the optimized binary codes for applications. RSTDE can keep the consistency and reusability of applications after the architecture of DP-RISP has been reconfigured. It can accelerate development of software tools, reduce workload of developers and expedite the design and evaluation of new embedded processors.
In RSTDE, profiler and compiler are the main parts and the interface between them is the mapping mechanism for dynamic traces to static codes. Therefore, to implement the design of RSTDE, the dissertation focus on the three key techniques including dynamic profiling for hot spots of applications, mapping the dynamic spots to static codes and code generation of the retargetable compiler.
The novelties and contributions of this dissertation are as below:
1) Presents a design flow of retargetable software tools development environment for our DP-RISP. The flow includes dynamic profiling, dynamic-to-static mapping and retargetable compiling, which adapts to the change of hardware and software.
2) Presents a configurable profiler for dynamic hot path detection. It can work with processors loosely and accurately obtain sensitive hot information of executing programs on instruction level while supports multiple sampling policies. Through configuration, the profiler can perform different profiling policies and profile target programs continuously or discretely.
3) Presents a dynamic-to-static code mapping algorithm which is based on the polynomial representation. Through the polynomial representations of basic blocks and even functions and loops in codes, a method of polynomials matching by layering exploration is used to map dynamic traces to static codes. The results are then used to annotate and instrument source codes.
4) Presents a mixed code-generating algorithm based on the extension of the conventional three-step method in compilation. The algorithm generates the binary codes for extended reconfigurable instructions according to the reconfigurable resources and configuration and makes the best reuse of the conventional method.
可重构指令集处理器将可重构技术应用到专用指令集处理器的实现中,利用可重构逻辑器件的硬件可编程性,针对不同的应用特征自适应地定制其最优的执行环境,从而在保有专用指令集处理器优点的前提下更有效地满足嵌入式领域的不同应用要求。由于可重构指令集处理器的指令集能够在设计完成后根据应用程序特点进行动态更改,与传统的固定指令集的处理器设计有很大的不同。这就使得针对传统处理器设计的软件工具链不适合于可重构指令集处理器应用程序的开发,需要有新的设计方法用于构造适应动态指令集特征的工具链,以便充分挖掘系统的处理性能。
本文针对上述的问题,以所设计的支持动态剖析的可重构指令集处理器为基础平台,提出了一个能够实现软件工具链可重定向设计的开发方案。该方案在对应用程序进行初始快速编译后利用仿真器执行二进制代码,通过对执行信息的剖析、映射等过程获得处理器的扩展指令集合。然后利用新的指令集体系结构完成对编译器和仿真器的可重定向扩展,实现对应用程序的优化编译。所提出的方案能够保证所设计的可重构指令集处理器在针对不同应用任务进行指令定制和硬件重构后,其上层应用程序开发模式的一致性和可重用性,满足对应用程序的兼容性要求,从而能够提高开发效率,降低开发人员的负担,并且对新的嵌入式处理器的开发设计和仿真评估具有积极的意义。
在所设计的软件工具链可重定向开发方案中,剖析机制和编译代码生成是整个方案的核心问题,而这两者之间的联系在于实现动态指令序列与静态代码结构的映射匹配。因此,为了实现针对可重构指令集处理器体系结构的工具链可重定向设计,快速有效地生成能够高性能执行的二进制代码,本文深入地研究了软件工具链可重定向开发方案中的三个关键技术,包括高效的热点动态剖析技术、热点代码映射匹配机制和编译后端可重定向实现。
本论文的主要贡献体现在下述几个方面：
1)提出了一种适合所设计的具有动态剖析特性的可重构指令集处理器的软件工具链可重定向开发方案,融合了热点剖析、动静代码映射及编译后端重定向等关键技术,能很好地适应动态变化的软硬件环境,提高开发效率。
2)研究了一种基于路径剖析的可配置热点剖析机制。其与处理器松散耦合,不需了解处理器微体系结构信息而完成剖析。同时,兼具对全过程剖析和采样剖析的支持,能够针对不同的应用需求而采取不同的剖析方案,使得用户可以权衡剖析准确度和剖析开销两方面的因素而作出选择。
3)研究了一种基于代数多项式表示的动-静代码映射匹配算法。该算法利用代数多项式来表示代码中的基本块乃至函数体与循环体等结构,在此基础上结合串匹配和多层次搜索的思想,通过多项式搜索匹配的方法实现动态序列表示与静态代码多项式集合的映射匹配,进而用于对源代码的注释标识。
4)研究了一个扩展传统编译后端代码生成三阶段方法的代码混合优化生成算法。该算法能够根据可用资源情况和系统重构配置针对可重构指令的代码生成进行优化处理,获得切合平台特性的可执行程序,并且很大程度地复用原有三阶段方法中对基本指令集的代码生成算法,简化了实现的复杂度。
Computer system has been more complicated because of the rapid development of electronic, network and hardware technique. With the emergence of new applications and varied user requirements, the programmability and calculability of processors become more and more challenging. The conventional processor design based on static instruction sets can't achieve the requirements on both of performance and flexibility. So the reconfigurable instruction set processor (RISP) emerged.
RISP is the application specific instruction-set processor combined with reconfiguration technology. Through the programmability of reconfigurable arrays, RISP can custom the best appropriate environment for a special application executing, so that it can efficiently meet diverse requirements in the embedded domain. RISP is very different from the conventional processor that its instruction set can be modified when executing, and so the software tools which are designed for the conventional processor don't adapt to code generation of RISP. To take full advantage of the performance of RISP, the new software tools design methodology for fitting dynamic instruction sets is needed.
According to the above, this dissertation presents a design flow of retargetable software tools development environment (RSTDE) based on our RISP framework named DP-RISP which supports dynamic profiling. RSTDE profiles the simulating execution of applications, generates new extended reconfigurable instructions and maps them to source codes. Then it retargets compiler and simulator with the new instructions to generate the optimized binary codes for applications. RSTDE can keep the consistency and reusability of applications after the architecture of DP-RISP has been reconfigured. It can accelerate development of software tools, reduce workload of developers and expedite the design and evaluation of new embedded processors.
In RSTDE, profiler and compiler are the main parts and the interface between them is the mapping mechanism for dynamic traces to static codes. Therefore, to implement the design of RSTDE, the dissertation focus on the three key techniques including dynamic profiling for hot spots of applications, mapping the dynamic spots to static codes and code generation of the retargetable compiler.
The novelties and contributions of this dissertation are as below:
1) Presents a design flow of retargetable software tools development environment for our DP-RISP. The flow includes dynamic profiling, dynamic-to-static mapping and retargetable compiling, which adapts to the change of hardware and software.
2) Presents a configurable profiler for dynamic hot path detection. It can work with processors loosely and accurately obtain sensitive hot information of executing programs on instruction level while supports multiple sampling policies. Through configuration, the profiler can perform different profiling policies and profile target programs continuously or discretely.
3) Presents a dynamic-to-static code mapping algorithm which is based on the polynomial representation. Through the polynomial representations of basic blocks and even functions and loops in codes, a method of polynomials matching by layering exploration is used to map dynamic traces to static codes. The results are then used to annotate and instrument source codes.
4) Presents a mixed code-generating algorithm based on the extension of the conventional three-step method in compilation. The algorithm generates the binary codes for extended reconfigurable instructions according to the reconfigurable resources and configuration and makes the best reuse of the conventional method.
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