面向密码应用的定制处理器关键技术研究
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摘要
密码算法及其应用程序是人们为了保障信息安全而发明的信息技术手段,作为安全加密技术的基础,在信息安全领域得到了广泛的运用。随着互联网技术的发展以及敏感数据越来越多的存储在网络上,密码算法在云计算、在线事务处理等网络应用中扮演着越来越重要的角色。同时由于通信技术、漏洞攻击技术和旁路攻击技术的进步,各应用对密码算法运算平台的计算速率、安全性能以及灵活性能提出了更高的要求。
传统的软硬件运算平台如CPU、GPU、FPGA和ASIC对密码算法的各项性能支持互不相同,CPU的灵活性能高,但是计算速率和安全性低；GPU的计算速率高但安全性低功耗过大；ASIC的计算速率和安全性都很好,但是造价高同时灵活性太低；FPGA的安全性高功耗低,但计算速率平常且灵活性偏低。各计算平台对密码应用都分别只能满足一项或两项性能要求,且都分别具有过低的性能指标。
本课题在对安全加密应用程序和加密算法深入分析的基础上,设计实现了两款面向密码应用的定制处理器IPCCP(IP Core Compute Processor)和FUMCP(frequent used mode Compute Processor),提供了相应的编译器,同时设计了面向密码应用的可视化编程环境以供定制处理器的使用者方便的开发相应的密码应用程序。我们还设计了用于自动分析代码、发掘密码算法中频繁使用模式的新型快速频繁子图挖掘算法Top-FFSM。
我们设计的IPCCP在运行示例程序时获得了相对于通用CPU 57、相对于FPGA 1.8的加速比；而FUMCP在运行示例程序时获得了相对于通用CPU 1.5至2的加速比,FUMCP相对于IPCCP的优势则是灵活性几乎与CPU完全一样。我们设计的频繁子图挖掘算法Top-FFSM在子图覆盖率和指令周期减少率上都取得了比通过C代码分析定制频繁使用部件更好的效果。本课题设计的可视化编程环境通过实验检验也被证明可以充分表达各种密码算法应用程序,同时对新的密码算法和密码程序都具有高度的可扩展性。
People invented Cipher algorithm and applications to ensure the safety of information. As the base of security technology, Cipher algorithm has been used widly in information field. The Internet developed quickly and more secret information has been stored on the Internet, hence the cipher algorithm become more and more important in applications like Cloud computing and On-line transaction processing. At the same time, due to the development of communication, hole attack and side-channel attack technology, the platform of cipher compute should be faster, safer and more flexible.
The traditional hardware and software computing platforms such as CPU, GPU, FPGA and ASIC have a different support on cipher algorithm performance. CPU has a high flexible performance but low performance of computation rate and safety; GPU has a high of compute rate but low safety and of excessive power dissipation; ASIC has high performance in compute rate and security, but the cost is too high and the flexibility is too low; FPGA is of high security and low power consumption, but the computation of rate is normal and flexibility is too low. Each computing platform for cryptographic applications are met only one or two performance requirements.
Based on the basis of deep analysis to cryptography algorithm and its application, we designed two customized processors IPCCP and FUMCP for cryptographic applications and providesd the corresponding compiler. At the same time, we designed a visual programming environment oriented to cryptographic application for the customized processor users to facilitate the development of the corresponding cipher application. We also designed a new type of fast frequent subgraph mining algorithm Top-FFSM for excavation frequently used model in cipher algorithm.
The IPCCP obtained 57 speedup compared to CPU and 1.8 speedup relative to FPGA. At the same time, FUMCP obtained 1.5 speedup compared to CPU, but the advantage of FUMCP relative to IPCCP is that it has almost exactly the same flexibility as CPU. The frequent subgraph mining algorithm Top-FFSM we designed obtained better effective than C code analysis in both subgraph coverage and execution cycle reduction rate. The visual programming environment we designed has been shown to fully express various cryptographic algorithm application, while the new encryption and password procedures are highly scalable.
传统的软硬件运算平台如CPU、GPU、FPGA和ASIC对密码算法的各项性能支持互不相同,CPU的灵活性能高,但是计算速率和安全性低；GPU的计算速率高但安全性低功耗过大；ASIC的计算速率和安全性都很好,但是造价高同时灵活性太低；FPGA的安全性高功耗低,但计算速率平常且灵活性偏低。各计算平台对密码应用都分别只能满足一项或两项性能要求,且都分别具有过低的性能指标。
本课题在对安全加密应用程序和加密算法深入分析的基础上,设计实现了两款面向密码应用的定制处理器IPCCP(IP Core Compute Processor)和FUMCP(frequent used mode Compute Processor),提供了相应的编译器,同时设计了面向密码应用的可视化编程环境以供定制处理器的使用者方便的开发相应的密码应用程序。我们还设计了用于自动分析代码、发掘密码算法中频繁使用模式的新型快速频繁子图挖掘算法Top-FFSM。
我们设计的IPCCP在运行示例程序时获得了相对于通用CPU 57、相对于FPGA 1.8的加速比；而FUMCP在运行示例程序时获得了相对于通用CPU 1.5至2的加速比,FUMCP相对于IPCCP的优势则是灵活性几乎与CPU完全一样。我们设计的频繁子图挖掘算法Top-FFSM在子图覆盖率和指令周期减少率上都取得了比通过C代码分析定制频繁使用部件更好的效果。本课题设计的可视化编程环境通过实验检验也被证明可以充分表达各种密码算法应用程序,同时对新的密码算法和密码程序都具有高度的可扩展性。
People invented Cipher algorithm and applications to ensure the safety of information. As the base of security technology, Cipher algorithm has been used widly in information field. The Internet developed quickly and more secret information has been stored on the Internet, hence the cipher algorithm become more and more important in applications like Cloud computing and On-line transaction processing. At the same time, due to the development of communication, hole attack and side-channel attack technology, the platform of cipher compute should be faster, safer and more flexible.
The traditional hardware and software computing platforms such as CPU, GPU, FPGA and ASIC have a different support on cipher algorithm performance. CPU has a high flexible performance but low performance of computation rate and safety; GPU has a high of compute rate but low safety and of excessive power dissipation; ASIC has high performance in compute rate and security, but the cost is too high and the flexibility is too low; FPGA is of high security and low power consumption, but the computation of rate is normal and flexibility is too low. Each computing platform for cryptographic applications are met only one or two performance requirements.
Based on the basis of deep analysis to cryptography algorithm and its application, we designed two customized processors IPCCP and FUMCP for cryptographic applications and providesd the corresponding compiler. At the same time, we designed a visual programming environment oriented to cryptographic application for the customized processor users to facilitate the development of the corresponding cipher application. We also designed a new type of fast frequent subgraph mining algorithm Top-FFSM for excavation frequently used model in cipher algorithm.
The IPCCP obtained 57 speedup compared to CPU and 1.8 speedup relative to FPGA. At the same time, FUMCP obtained 1.5 speedup compared to CPU, but the advantage of FUMCP relative to IPCCP is that it has almost exactly the same flexibility as CPU. The frequent subgraph mining algorithm Top-FFSM we designed obtained better effective than C code analysis in both subgraph coverage and execution cycle reduction rate. The visual programming environment we designed has been shown to fully express various cryptographic algorithm application, while the new encryption and password procedures are highly scalable.
引文
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[6]J. Huang, R. Berry and M.L. Honig. Distributed interference compensation for wireless networks[J]. IEEE Journal on Selected Areas in Communications,2006,24(5):1074-1084.
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[13]彭湘凯.VPN及其核心技术[J].成都大学学报,2001,20(1)：12-15.
[14]LIANG Quan, ZHANG Hong Zheng, LIANG, Kai Jian, YANG Yang. Research on Grid Quality of Service(QoS)[J]. Computer science,2006,33(7): 42-46.
[15]Foster I, Kesselman C, Lee C, et al. A Distributed Resource Management Architecture that Supports Advance Reservation and Co Allocation[C]. Proceedings of the International Workshop on QoS(IWQoS), London,1999: 27-36.
[16]Yutu Liu, Anne H.H. Ngu, Liangzhao Zeng. QoS Computation and Policing in Dynamlic Web Service Selection[C]. Proceedings of the 13th International Conference on World Wide Web(WWW),New York, USA,2004:66-73.
[17]雅奇880.[EB/OL]http://www.yqmis.com/
[18]Elisabeth Oswald,Stefan Mangard. Template Attacks on Masking—Resistance Is Futile[C]. Proceedings of The Cryptographers' Track at the RSA Conference 2007(CTRSA 2007), San Francisco, CA, USA,2007:12-27.
[19]ZHANG Tao, FAN Mingyu, ZHENG Xiulin.Method on building self-headling cryptosystem resistant to side-channal attack [J].Application Research of Comuters,2008,25(9):2829-2833.
[20]OSWALD E, MANGARD S, HERBST C, et al. Pract ical second-order DPA attacks for m asked sm artcard implementations of block ciphers[C]. Proceedings of The Cryptographers' Track at the RSA Conference 2006(CTRSA 2006), San Jose, CA, USA,2006:192-207.
[21]Tillich S, GroBschadl J. Accelerating AES Using Instruction Set Extensions for Elliptic Curve Cryptography[C]. Proceedings of 2005 International Workshop on Information Security & and Hiding, Singapore,2005:43-59.
[22]Dai Z Bibin, Li Wei, Yang X Hiaohui, et al. The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing[C]. Proceedings of 2008 International Conference on Embedded Software and Systems:587-594.
[23]Kubilay Atasu, Laura Pozzi, Paolo Ienne. Automatic application-specific instruction-set extensions under microarchitectural constraints[C]. Proceedings of the 40th conference on Design automation,CA, USA,2003:176-184.
[24]薄拾,葛宁,林孝康.面向安全与加密应用的定制指令设计[J].计算机工程,2010,36(20)：1-4.
[25]F.L.Ni, M.H.Jin, Z.W.Xie, Sh.C.Shi,Y.Ch.Liu, H.Liu, G.Hirzinger. Highly Integrated Joint Servo System Based on FPGA with Nios II Processor[C]. Proceedings of the 2006 IEEE International Conference on Mechatronics and Automation, Luoyang, China,2006:973-978.
[26]Joshi Nivedita N.,Dakhole P.K.,Zode P.P. Embedded Web Server on Nios II Embedded FPGA Platform[C]. Proceedings of 2009 2nd International Conference on Emerging Trends in Engineering and Technology(ICETET 2009):372-377.
[27]黄崧,曾芳玲,杨景曙.基于NIOS Ⅱ的嵌入式云发生器电路设计[J].应用电路设计,2007,(29)3：74-76.
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