面向YHFT-DSP的GCC编译器移植
摘要
随着数字信号处理技术的高速发展,数字信号处理器(Digital Signal Processor, DSP)已广泛应用于雷达、音频视频、生物医学仪器等诸多领域。
YHFT-DSP是国防科学技术大学计算机学院自主研制的我国新一代高性能32位定点数字信号处理器。它采用的是分簇的超长指令字体系结构,其主要特点在于运用静态指令调度技术。在运行过程中完全依赖编译器对程序中指令的相关性进行静态的分析,并以此决定指令是否可以并行执行,以及执行的顺序。可见编译器的编译效率在很大程度上决定了YHFT-DSP性能的发挥。由于目前并不存在与之完全匹配的开源编译器,完全重新设计又费时费力,因此面向YHFT-DSP的编译器重定向移植技术的研究具有非常现实的理论与实践意义。
论文基于可重定向编译器GCC,深入研究了GCC编译器后端移植技术,设计实现了面向YHFT-DSP的YHFT-GCC编译器。
论文的主要工作及贡献如下:
在全面研究YHFT-DSP体系结构和指令系统以及GCC编译器结构的基础上,对GCC编译器的后端展开深入分析,提出了面向YHFT-DSP的GCC编译器后端移植方案,并完成了对YHFT-DSP的机器描述。
设计实现了YHFT-GCC的函数调用、跳转指令、条件执行、指令调度等关键模块。这些模块的实现在GCC的后端移植过程中是不可或缺的。
根据本文所研究的编译技术,完成了面向YHFT-DSP的GCC编译器移植,并对移植成功的YHFT-GCC编译器进行了具体测试和性能分析。结果显示,YHFT-GCC可以满足YHFT-DSP的编译要求。
鉴于GCC编译器的开源特性,相信在后续的研究工作中,随着对其进行进一步的优化,能够获得更好的编译效果。论文最后给出了本文未来工作的发展方向。
With the development of Digital Signal Processing, the Digital Signal Processor (DSP) has been widely used in radar, audio and video processing, biomedical instruments etc.
YHFT-DSP is a new generation of 32-bit fixed point high performance Digital Signal Processor of our country, which is independently designed by the Computer College of National University of Defense Technology. It uses a clustered of Very Long Instruction Word (VLIW) architecture, and the main feature of this chip is the use of static instruction scheduling techniques. It determines if the instructions can be parallel executed and be executed with which order, by statically analyses the dependencies between instructions, which is completely handled by compiler. This shows that the efficiency of the compiler mostly determines the performance of YHFT-DSP. Currently, there is no absolutely suited open source compiler being available and therefore it has very real theoretical and practical significance to make an effort in studying the compiler porting technology for YHFT-DSP.
Based on retargetable compiler infrastructure GCC, we study the backend porting technology of GCC, design and implement the YHFT-GCC compiler for YHFT-DSP.
The main works and contributions of this thesis are as follows:
Based on the comprehensive study on the instruction system of the YHFT-DSP and the architecture of the GCC compiler, we deeply analyze the backend of the GCC compiler, and then propose the scheme of porting backend of GCC for the chip of YHFT-DSP. And the machine description to YHFT-DSP is also accomplished.
We Design and implement the key modules of YHFT-GCC, such as: function call, instruction jump, condition execution, instruction scheduling and so on. These are the most important part of the porting work.
Based on the compiler technology we deeply investigate in the thesis, we accomplish the porting of GCC compilers for YHFT-DSP. The results of the benchmark testing and performance analysis on the achieved YHFT-GCC compiler show that it can be suitable for YHFT-DSP.
Whereas the GCC is an Open Source Compiler, it will be more efficiency by following research work on further optimization. Finally, the direction of future work is given at the end of the thesis.
YHFT-DSP是国防科学技术大学计算机学院自主研制的我国新一代高性能32位定点数字信号处理器。它采用的是分簇的超长指令字体系结构,其主要特点在于运用静态指令调度技术。在运行过程中完全依赖编译器对程序中指令的相关性进行静态的分析,并以此决定指令是否可以并行执行,以及执行的顺序。可见编译器的编译效率在很大程度上决定了YHFT-DSP性能的发挥。由于目前并不存在与之完全匹配的开源编译器,完全重新设计又费时费力,因此面向YHFT-DSP的编译器重定向移植技术的研究具有非常现实的理论与实践意义。
论文基于可重定向编译器GCC,深入研究了GCC编译器后端移植技术,设计实现了面向YHFT-DSP的YHFT-GCC编译器。
论文的主要工作及贡献如下:
在全面研究YHFT-DSP体系结构和指令系统以及GCC编译器结构的基础上,对GCC编译器的后端展开深入分析,提出了面向YHFT-DSP的GCC编译器后端移植方案,并完成了对YHFT-DSP的机器描述。
设计实现了YHFT-GCC的函数调用、跳转指令、条件执行、指令调度等关键模块。这些模块的实现在GCC的后端移植过程中是不可或缺的。
根据本文所研究的编译技术,完成了面向YHFT-DSP的GCC编译器移植,并对移植成功的YHFT-GCC编译器进行了具体测试和性能分析。结果显示,YHFT-GCC可以满足YHFT-DSP的编译要求。
鉴于GCC编译器的开源特性,相信在后续的研究工作中,随着对其进行进一步的优化,能够获得更好的编译效果。论文最后给出了本文未来工作的发展方向。
With the development of Digital Signal Processing, the Digital Signal Processor (DSP) has been widely used in radar, audio and video processing, biomedical instruments etc.
YHFT-DSP is a new generation of 32-bit fixed point high performance Digital Signal Processor of our country, which is independently designed by the Computer College of National University of Defense Technology. It uses a clustered of Very Long Instruction Word (VLIW) architecture, and the main feature of this chip is the use of static instruction scheduling techniques. It determines if the instructions can be parallel executed and be executed with which order, by statically analyses the dependencies between instructions, which is completely handled by compiler. This shows that the efficiency of the compiler mostly determines the performance of YHFT-DSP. Currently, there is no absolutely suited open source compiler being available and therefore it has very real theoretical and practical significance to make an effort in studying the compiler porting technology for YHFT-DSP.
Based on retargetable compiler infrastructure GCC, we study the backend porting technology of GCC, design and implement the YHFT-GCC compiler for YHFT-DSP.
The main works and contributions of this thesis are as follows:
Based on the comprehensive study on the instruction system of the YHFT-DSP and the architecture of the GCC compiler, we deeply analyze the backend of the GCC compiler, and then propose the scheme of porting backend of GCC for the chip of YHFT-DSP. And the machine description to YHFT-DSP is also accomplished.
We Design and implement the key modules of YHFT-GCC, such as: function call, instruction jump, condition execution, instruction scheduling and so on. These are the most important part of the porting work.
Based on the compiler technology we deeply investigate in the thesis, we accomplish the porting of GCC compilers for YHFT-DSP. The results of the benchmark testing and performance analysis on the achieved YHFT-GCC compiler show that it can be suitable for YHFT-DSP.
Whereas the GCC is an Open Source Compiler, it will be more efficiency by following research work on further optimization. Finally, the direction of future work is given at the end of the thesis.
引文
[1] Steven S. Muchnick. Advanced Compiler Design and Implementation. [M] San Francisco, California: Morgan Kaufmann, 1997
[2] Randy Allen & Ken Kennedy. Optimizing Compilers Modern Architectures, A Dependence-Based Approach. [M] San Francisco, California: Morgan Kaufmann, 2001
[3] Kenneth C. Louden. Compiler Construction Principles and Practice. [M] PWS Publishing Company, 1997
[4] A. V. Aho, R. Sethi, J. D. Ullman. Compilers: Principles, Techniques, and Tools. [M] Addison-Wesley, Longman Publishing Co., Inc., 1986.
[5] S. Rajagopalan, S. P. Rajan, S. Malik, G. Araujo, K. Takayama. A Retargetable VLIW Compiler Framework for DSPs with Instruction-level Parallelism. [J] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2001, 20(11): 1319-1328.
[6] The Free Software Definition. Free Software Foundation.[EB/OL] http://www.gnu.org/philosophy/free-sw.html
[7] GCC Internals (v4.0). Free Software Foundation. [EB/OL] 2004. http://gcc.gnu.org
[8] Host/Target specific installation notes for GCC. [EB/OL] Free Software Foundation. http://gcc.gnu.org/install/specific.html.
[9] Lcc, A Retargetable Compiler for ANSIC. [EB/OL] http://www.cs.princeton.edu/software/lcc/.
[10] C. W. Fraser, D. R. Hanson. A Retargetable C Compiler: Design and Implementation.[M] Addison-Wesley, Longman Publishing Co., Inc., 1995.
[11] C. W. Fraser, D. R. Hanson. Compile C Faster on Linux. [EB/OL] http://www.cs.princeton.edu/software/lcc/.
[12] Watcom C/C++ and Fortran. SciTech Software. 2004. http://www.openwatcom.org/index.html.
[13] The Stanford SUIF Compiler Group. [EB/OL] http://suif.stanford.edu/
[14] GNU Binutils. Free Software Foundation. 2000–2004. http://gcc.gnu.org
[15] J. Fridman, Z. Greenfield. The TigerSHARC DSP Architecture. [J] IEEE Micro, 2000, 20(1):66-76.
[16] P. Farabochi, G. Brown. J. A. Fisher, ecl. Lx: A Technology Platform for Customizable VLIW Embedded Processing. [J] ISCA’00: Proceedings of the 27th annual international symposium on Computer Architecture. ACM Press, 2000. 203-213.
[17] J. Merrill. GENERIC and GIMPLE: A New Tree Representation for Entire Functions. [C] In Proceedings of the 2003 GCC Summit, Ottawa, Canada, May2003.
[18] R. Cytron, J. Ferrante, B. Rosen, M. Wegman, K. Zadeck. Efficiently computing static single assignment form and the control dependence graph. [J] ACM Transactions on Programming Languages and Systems, 13(4):451–490, October 1991.
[19] D. Novillo. Tree SSA - A New Optimization Infrastructure for GCC. [C] 2003 GCC Developer’s Summit, pages 181-193, Ottawa, Canada, May 2003.
[20] D. Novillo. Design and Implementation of Tree SSA. [C] In Proceedings of the 2004 GCC Summit, Ottawa, Canada, June 2004.
[21] J. W. Davidson and C. W. Fraser. The Design and Application of a Retargetable Peephole Optimizer. [J] ACM Transactions on Programming Languages and Systems, 2(2):191–202, April 1980.
[22] J. W. Davidson and D. B. Whalley. Quick Compilers Using Peephole Optimization. [J] Software - Practice and Experience, 19(1):79–97, 1989.
[23] V. Makarov. Fighting Register Pressure in GCC. [C] In Proceedings of the 2004 GCC Summit, Ottawa, Canada, June 2004.
[24] V. Makarov. Yet Another GCC Register Allocator. [C] In Proceedings of the 2005 GCC Summit, Ottawa, Canada, June 2005.
[25] M. Matz. Design and Implementation of the Graph Coloring Register Allocator for GCC. [C] In Proceedings of the 2003 GCC Summit, Ottawa, Canada, June 2003.
[26] M. Punjani. Register Rematerialization in GCC. [C] In Proceedings of the 2004 GCC Summit, Ottawa, Canada, June 2004.
[27] GNU Compiler Collection (v4.0). [EB/OL] Free Software Foundation. June 2008, http://gcc.gnu.org/
[28]任小西,李仁发,张克环等.一种基于多目标设计方法的嵌入式编译技术[J].计算机应用,2004,(2):165-167.
[29] Shishir Mondal. Compiler Back End Generation from nML Machine Description[D]. Department of Computer Science & Engineering, Indian Institute of Technology, Kanpur, 1999.
[30] Arthur Griffith著,胡恩华译.GCC技术参考大全[M].北京:清华大学出版社,2004.
[31] M. L. Software pipelining: An Effective Scheduling Technique for VLIW Machines. [J] Proceedings of the ACM SIGPLAN 1988 Conference on Programming Language Design and Implementation. ACM Press, 1988. 318-328.
[32] J. A. Fisher. Trace scheduling: A technique for global microcode compaction. [J] IEEE Transactions on Computers Vol. C-30, July 1981, 30(7): 478-490
[33] W. W. Hwu, S. A. Mablke, W. Y. Chen, P. P. Chang. The Superblock: An Effective Technique for VLIW and Superscalar Compilation. [J] The Journal of Supercomputing, 1993, 7(1/2):229-248
[34] S. A. Mablke, D. C. Lin, W. Y. Chen, R. E. Hank, R. A. Bringmann. Effective compiler support for predicated execution using the hyperblock. [J] SIGMICRO Newsl., 1992,23(1-2):45-54
[35] John Hennessy and David Patterson, Computer Architecture, Fourth Edition: A Quantitative Approach. [M] Morgan Kaufmann Publishers Inc., San Francisco, CA, USA.
[36] V. Makarov. The Finite State Automaton Based Pipeline Hazard Recognizer and Instruction Scheduler in GCC. [C] Proceedings of the GCC Developer’s Summit, 2003.
[37] G. Desch. Instruction assignment for clustered VLIW DSP compilers: A new approach. [R] Technical Report HPL-98-13. Hewlett-Packard Company. Feb,1998.
[38] TMS320C6000 Assembly Language Tools User’s Guide(spru186). [EB/OL]. Texas Instruments. http://www.ti.com/.
[39]徐明.GCC中文手册.[EB/OL] http://cmpp.linuxforum.net/
[2] Randy Allen & Ken Kennedy. Optimizing Compilers Modern Architectures, A Dependence-Based Approach. [M] San Francisco, California: Morgan Kaufmann, 2001
[3] Kenneth C. Louden. Compiler Construction Principles and Practice. [M] PWS Publishing Company, 1997
[4] A. V. Aho, R. Sethi, J. D. Ullman. Compilers: Principles, Techniques, and Tools. [M] Addison-Wesley, Longman Publishing Co., Inc., 1986.
[5] S. Rajagopalan, S. P. Rajan, S. Malik, G. Araujo, K. Takayama. A Retargetable VLIW Compiler Framework for DSPs with Instruction-level Parallelism. [J] Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 2001, 20(11): 1319-1328.
[6] The Free Software Definition. Free Software Foundation.[EB/OL] http://www.gnu.org/philosophy/free-sw.html
[7] GCC Internals (v4.0). Free Software Foundation. [EB/OL] 2004. http://gcc.gnu.org
[8] Host/Target specific installation notes for GCC. [EB/OL] Free Software Foundation. http://gcc.gnu.org/install/specific.html.
[9] Lcc, A Retargetable Compiler for ANSIC. [EB/OL] http://www.cs.princeton.edu/software/lcc/.
[10] C. W. Fraser, D. R. Hanson. A Retargetable C Compiler: Design and Implementation.[M] Addison-Wesley, Longman Publishing Co., Inc., 1995.
[11] C. W. Fraser, D. R. Hanson. Compile C Faster on Linux. [EB/OL] http://www.cs.princeton.edu/software/lcc/.
[12] Watcom C/C++ and Fortran. SciTech Software. 2004. http://www.openwatcom.org/index.html.
[13] The Stanford SUIF Compiler Group. [EB/OL] http://suif.stanford.edu/
[14] GNU Binutils. Free Software Foundation. 2000–2004. http://gcc.gnu.org
[15] J. Fridman, Z. Greenfield. The TigerSHARC DSP Architecture. [J] IEEE Micro, 2000, 20(1):66-76.
[16] P. Farabochi, G. Brown. J. A. Fisher, ecl. Lx: A Technology Platform for Customizable VLIW Embedded Processing. [J] ISCA’00: Proceedings of the 27th annual international symposium on Computer Architecture. ACM Press, 2000. 203-213.
[17] J. Merrill. GENERIC and GIMPLE: A New Tree Representation for Entire Functions. [C] In Proceedings of the 2003 GCC Summit, Ottawa, Canada, May2003.
[18] R. Cytron, J. Ferrante, B. Rosen, M. Wegman, K. Zadeck. Efficiently computing static single assignment form and the control dependence graph. [J] ACM Transactions on Programming Languages and Systems, 13(4):451–490, October 1991.
[19] D. Novillo. Tree SSA - A New Optimization Infrastructure for GCC. [C] 2003 GCC Developer’s Summit, pages 181-193, Ottawa, Canada, May 2003.
[20] D. Novillo. Design and Implementation of Tree SSA. [C] In Proceedings of the 2004 GCC Summit, Ottawa, Canada, June 2004.
[21] J. W. Davidson and C. W. Fraser. The Design and Application of a Retargetable Peephole Optimizer. [J] ACM Transactions on Programming Languages and Systems, 2(2):191–202, April 1980.
[22] J. W. Davidson and D. B. Whalley. Quick Compilers Using Peephole Optimization. [J] Software - Practice and Experience, 19(1):79–97, 1989.
[23] V. Makarov. Fighting Register Pressure in GCC. [C] In Proceedings of the 2004 GCC Summit, Ottawa, Canada, June 2004.
[24] V. Makarov. Yet Another GCC Register Allocator. [C] In Proceedings of the 2005 GCC Summit, Ottawa, Canada, June 2005.
[25] M. Matz. Design and Implementation of the Graph Coloring Register Allocator for GCC. [C] In Proceedings of the 2003 GCC Summit, Ottawa, Canada, June 2003.
[26] M. Punjani. Register Rematerialization in GCC. [C] In Proceedings of the 2004 GCC Summit, Ottawa, Canada, June 2004.
[27] GNU Compiler Collection (v4.0). [EB/OL] Free Software Foundation. June 2008, http://gcc.gnu.org/
[28]任小西,李仁发,张克环等.一种基于多目标设计方法的嵌入式编译技术[J].计算机应用,2004,(2):165-167.
[29] Shishir Mondal. Compiler Back End Generation from nML Machine Description[D]. Department of Computer Science & Engineering, Indian Institute of Technology, Kanpur, 1999.
[30] Arthur Griffith著,胡恩华译.GCC技术参考大全[M].北京:清华大学出版社,2004.
[31] M. L. Software pipelining: An Effective Scheduling Technique for VLIW Machines. [J] Proceedings of the ACM SIGPLAN 1988 Conference on Programming Language Design and Implementation. ACM Press, 1988. 318-328.
[32] J. A. Fisher. Trace scheduling: A technique for global microcode compaction. [J] IEEE Transactions on Computers Vol. C-30, July 1981, 30(7): 478-490
[33] W. W. Hwu, S. A. Mablke, W. Y. Chen, P. P. Chang. The Superblock: An Effective Technique for VLIW and Superscalar Compilation. [J] The Journal of Supercomputing, 1993, 7(1/2):229-248
[34] S. A. Mablke, D. C. Lin, W. Y. Chen, R. E. Hank, R. A. Bringmann. Effective compiler support for predicated execution using the hyperblock. [J] SIGMICRO Newsl., 1992,23(1-2):45-54
[35] John Hennessy and David Patterson, Computer Architecture, Fourth Edition: A Quantitative Approach. [M] Morgan Kaufmann Publishers Inc., San Francisco, CA, USA.
[36] V. Makarov. The Finite State Automaton Based Pipeline Hazard Recognizer and Instruction Scheduler in GCC. [C] Proceedings of the GCC Developer’s Summit, 2003.
[37] G. Desch. Instruction assignment for clustered VLIW DSP compilers: A new approach. [R] Technical Report HPL-98-13. Hewlett-Packard Company. Feb,1998.
[38] TMS320C6000 Assembly Language Tools User’s Guide(spru186). [EB/OL]. Texas Instruments. http://www.ti.com/.
[39]徐明.GCC中文手册.[EB/OL] http://cmpp.linuxforum.net/