基于FPGA的可重配置片上系统
|
摘要
随着半导体制造工艺的进步,ASIC芯片开发的费用迅速增长,面市时间要求日益紧迫,用户对产品设计的灵活性也提出越来越高的要求,导致ASIC芯片的设计越来越困难。近些年来,可重配置硬件由于灵活性和费用低等优点表现出了明显强于ASIC的发展势头。但可重配置硬件固有的弱点如功耗高、速度慢、资源冗余等使其在面对复杂功能设计时还是不能够达到要求,因此人们开始考虑通过技术上的融合在ASIC与可重配置硬件之间寻找一条中间道路——可编程片上系统SOPC。SOPC不仅可以降低开发SOC芯片的风险,缩短上市时间,而且其可重构的灵活能力提供了将同一芯片用到不同应用中去的机会,尤其适用于不断变化和发展标准的产品开发中,例如通讯和网络芯片产品等。
动态可重构是指在系统运行过程中可重配置部分能够被重复配置,在不同的时刻完成不同的功能。和静态可重构相比,动态可重构可以更充分的利用可重配置硬件。动态可重构技术是国际上研究的热点,尤其是在可重配置计算方面。该技术在理论上已经有了很大发展,但是目前仍然存在很多不足。
FPGA组未来的发展方向之一是做支持动态可重配置的SOPC硬件。这是一项浩大的工程,本文所做的工作是其中的一部分。本文工作共包含两个部分:第一个部分集中在通用SOPC硬件平台的设计;第二部分是针对特定应用的动态可重构硬件平台设计。
本文的创新点如下:
1.本文参考已有SOPC硬件平台,并考虑动态可重配置的要求,提出了一个新的SOPC硬件平台,该平台由CPU、多个FPGAIP核、片上存储器、系统互连、配置用硬件等组成,FPGA IP核通过可编程的系统互连资源与片上存储器连接。为了支持硬件平台的设计,进一步提炼出了面临的问题及解决方案。
2.考虑针对特定应用设计优化的可重配置硬件平台。应用选取为JPEG2000及MPEG-4静态纹理图像压缩标准中所需的小波变换。提出了可重构的二维一级小波变换硬件平台,整体结构采用流水操作,数据分组输入,行列变换之间无需存储器。结果显示该硬件平台是一种高效高速的结构。
3.在分组输入数据的方式下进行行方向小波变换时,不同组的运算在时间上是串行的,且所需的运算是不同的。行方向小波变换采用动态可重配置的思想,硬件设计用可重构硬件实现,在系统运行时切换多路选择器从而实现不同组对应的运算,在不影响速度的同时节省了系统的面积。
Due to dramatically increasing development cost, shorter time to market and flexibility demand, ASIC designs are more and more difficult. Meanwhile, reconfigurable devices are developing fast because of its flexibility and less development cost. But intrinsic shortcomings of reconfigurable devices, for example, high power, low speed, etc. induce difficulties in complex designs realizations. So people began to consider combination of ASIC and reconfigurable device on a single chip, which is SOPC. SOPC can not only decrease development risk and timing to market, but also can be used in different applications, especially of products that keep varying, for example, communication and network products.
Dynamically reconfiguration means reconfigurable device of the chip can be reconfigured repeatable, and performs different functions at different times. Compared with static reconfiguration, dynamic reconfiguration can use the reconfigurable device more thoroughly. It's a hot research in the world, especially in reconfigurable computing. This technology has developed a lot in theory, but it still has many deficiencies.
One of the futures of FPGA development group is to design a SOPC chip that can support dynamic reconfiguration, which is a very big project. Work of this paper is part of this job. The research can be divided into two parts. The first part focuses on design of a universal SOPC chip. The second part is dynamic hardware platform for a specific application.
Following work is done:
1. Proposes a primary hardware platform of SOPC, problems in future design, and next a flow to solve the problem, also research of dynamic reconfiguration. Clear of what consist in dynamic reconfiguration and the steps to develop a dynamic reconfiguration system from the very front end of high level language description to mapping to the device.
2. Consider of hardware design for a specific application, finally discrete wavelet transform is chosen. A reconfigurable hardware platform is proposed. Results show it's a high efficient and high speed design.
3. Row module design of the discrete wavelet transform platform adopts idea of dynamic reconfiguration. It can save hardware area at no speed decrease.
动态可重构是指在系统运行过程中可重配置部分能够被重复配置,在不同的时刻完成不同的功能。和静态可重构相比,动态可重构可以更充分的利用可重配置硬件。动态可重构技术是国际上研究的热点,尤其是在可重配置计算方面。该技术在理论上已经有了很大发展,但是目前仍然存在很多不足。
FPGA组未来的发展方向之一是做支持动态可重配置的SOPC硬件。这是一项浩大的工程,本文所做的工作是其中的一部分。本文工作共包含两个部分:第一个部分集中在通用SOPC硬件平台的设计;第二部分是针对特定应用的动态可重构硬件平台设计。
本文的创新点如下:
1.本文参考已有SOPC硬件平台,并考虑动态可重配置的要求,提出了一个新的SOPC硬件平台,该平台由CPU、多个FPGAIP核、片上存储器、系统互连、配置用硬件等组成,FPGA IP核通过可编程的系统互连资源与片上存储器连接。为了支持硬件平台的设计,进一步提炼出了面临的问题及解决方案。
2.考虑针对特定应用设计优化的可重配置硬件平台。应用选取为JPEG2000及MPEG-4静态纹理图像压缩标准中所需的小波变换。提出了可重构的二维一级小波变换硬件平台,整体结构采用流水操作,数据分组输入,行列变换之间无需存储器。结果显示该硬件平台是一种高效高速的结构。
3.在分组输入数据的方式下进行行方向小波变换时,不同组的运算在时间上是串行的,且所需的运算是不同的。行方向小波变换采用动态可重配置的思想,硬件设计用可重构硬件实现,在系统运行时切换多路选择器从而实现不同组对应的运算,在不影响速度的同时节省了系统的面积。
Due to dramatically increasing development cost, shorter time to market and flexibility demand, ASIC designs are more and more difficult. Meanwhile, reconfigurable devices are developing fast because of its flexibility and less development cost. But intrinsic shortcomings of reconfigurable devices, for example, high power, low speed, etc. induce difficulties in complex designs realizations. So people began to consider combination of ASIC and reconfigurable device on a single chip, which is SOPC. SOPC can not only decrease development risk and timing to market, but also can be used in different applications, especially of products that keep varying, for example, communication and network products.
Dynamically reconfiguration means reconfigurable device of the chip can be reconfigured repeatable, and performs different functions at different times. Compared with static reconfiguration, dynamic reconfiguration can use the reconfigurable device more thoroughly. It's a hot research in the world, especially in reconfigurable computing. This technology has developed a lot in theory, but it still has many deficiencies.
One of the futures of FPGA development group is to design a SOPC chip that can support dynamic reconfiguration, which is a very big project. Work of this paper is part of this job. The research can be divided into two parts. The first part focuses on design of a universal SOPC chip. The second part is dynamic hardware platform for a specific application.
Following work is done:
1. Proposes a primary hardware platform of SOPC, problems in future design, and next a flow to solve the problem, also research of dynamic reconfiguration. Clear of what consist in dynamic reconfiguration and the steps to develop a dynamic reconfiguration system from the very front end of high level language description to mapping to the device.
2. Consider of hardware design for a specific application, finally discrete wavelet transform is chosen. A reconfigurable hardware platform is proposed. Results show it's a high efficient and high speed design.
3. Row module design of the discrete wavelet transform platform adopts idea of dynamic reconfiguration. It can save hardware area at no speed decrease.
引文
[1] http://www.smte.net/Get/Docs/Ele/2008-l/14/1001140510131101316673283 6.htm
[2] S. Hauck. The Roles of FPGAs in Reprogrammable Systems [J]. Proceedings of the IEEE, Vol. 86, No. 4, pp. 615-638, April, 1998
[3] Vassiliadis, Stamatis; Soudris, Dimitrios (Eds.). Fine- and Coarse-Grain Reconfigurable Computing. 2007, XVI, 384 p. ISBN: 978-1-4020-6504-0
[4] http://www.idcnews.net/html/edu/hardwaretechnology/20070411/231281 .html
[5] http://www.altera.com.cn/products/devices/stratix3/st3-index.jsp
[6] Brown S, Francis R, Rose J, et al. Field-programmable gate arrays [M] Norwell: Kluwer, 1992.
[7] http://brass.cs.berkeley.edu/
[8] http://brass.cs.berkeley.edu/SCORE/
[9] http://www.eecg.toronto.edu/-jece/OneChip/
[10]Actel Corp, "VariCore Embedded Programmable Gate Array Core (EPGA) 0.18μm Family", Datasheet, December 2001. 2.
[11] http://www.atmel.com/products/FPSLIC/default.asp
[12]Gericota M.G, Alves G.R, Silva M.L, Ferreira, J.M. Run-time management of logic resources on reconfigurable systems [C]. Design, Automation and Test in Europe Conference and Exhibition, 2003. pp.974 - 979
[13]http://www.acm.org/crossroads/xrds5-3/rcconcept.html
[14]Wim Sweldens. The Lifting Scheme: A Construction of Second Generation Wavelets [J]. SIAM Journal of Mathematical Analysis. 1997. pp.511-546
[15] http://www.jpeg.org/public/fcdl 5444-1 .pdf
[16] http://mcuol.com/download/upfile/2-SystemOnaProgrammableChip.pdf
[17] http://www.ece.cmu.edu/research/piperench/
[18]Hartenstein, Reiner. RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances. Parallel and Distributed Processing Symposium [M]. 2006. ISBN: 1-4244-0054-6
[19] Ralph D. Wittig. OneChip: An FPGA Processor with Reconfigurable Logic [D]. Master's thesis. University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
[20]Philips S,Hauck S.Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip[C].ACM International Symposium on FPGA.2002.
[21]http://chameleon.ctit.utwente.nl/
[22]Nikolaos S.Voros and Konstantinos Masselos.Introduction to Reconfigurable Hardware.System Level Design of Reconfigurable Systems-on-Chip[M].2005.ISBN 978-0-387-26103-4(Print).pp.15-26
[23]Prakash Rashinkar等著.孙海半等译.系统芯片(SOC)验证方法与技术[M].电子工业出版社.
[24]Kamal,R.编著,陈曙晖等译.嵌入式系统:体系结构、编程设计[M].清华大学出版社.2005
[25]Compton.K,Hauck.S.Reconfigurable computing:A survey of systems and software[J].ACM Computing Surveys.2002.Vol(34).pp.171-210
[26]T.J.Todman,G.A.Constantinides.Reconfigurable computing:architectures and design methods[J].IEE Proc.-Comput.Digit.Tech.2005.Vol(152).pp.193-207
[27]http://www.acm.uiuc.edu/sigarch/projects/reconf/report_ 1.html
[28]http://www.ece.lsu.edu/vaidy/raw05
[29]T.J.Callahan,J.R.Hause.The Garp architecture and C compiler[J].Computer 2000(33) pp.62-69
[30]Claus.C,Muller.F.H,Zeppenfeld.J.A new framework to accelerate Virtex-Ⅱ Pro dynamic partial self-reconfiguration[C].Parallel and Distributed Processing Symposium.2007.pp.1-7
[31]Ullmann.M,Hubner.M,Becker.J.On-demand FPGA run-time system for flexible and dynamical reconfiguration[J].Journal of Embedded Systems.2006.Vol(1) pp.193-204
[32]K.Compton,Z.Li,J.Cooley,etc.Configuration Relocation and Defragmentation for Run-Time Reconfigurable Computing[J].Trans.Very Large Scale Integration(VLSI) Systems.2002.Vol(10).No.3,pp.209-220.
[33]Dynamically Reconfigurable Devices & Technology [R].http://dec.bournemouth.ac.uk/drhw_lib/technology.html.
[34]Two flows for Partial reconfiguration:Module based or difference based[R].Xilinx Inc.Xilinx Application Note 290,version 1.2 July 2004
[35]P.Sedcole,B.Blodget,T.Becker.Modular Dynamic Reconfiguration in Virtex FGPAs[J].Computers and Digital Techniques.2006.Vol(153)
[36]Brandon.B,Philip.J,Eric.K,etc.A Self-reconfiguring Platform[C].FPL 2003.pp.565-574.
[37]Delahaye.J.P.,Palicot.J,Moy.C,etc.Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform[J].Mobile and Wireless Communications.2007.pp.1-5
[38]Moscu.P,E.,Bertels,K,Vassiliadis.S.Dynamic hard-ware reconfigurations:Performance impact on mpeg2[C].In:Proceedings of SAMOS.Volume 3133.Samos,Greece,Computer Science.2004.pp.284-292
[39]Juanjo Noguera and Rosa M.Badia.HW/SW Codesign Techniques for Dynamically Reconfigurable Architectures[J].Transactions on VLSI.vol(10),No.4,AUGUST 2002:399-415
[40]Banerjee.S,Bozorgzadeh.E,Dutt.N.D.Integrating Physical Constraints in HW-SW Partitioning for Architectures with Partial Dynamic Reconfiguration[J].Transactions on Very Large Scale Integration Systems.Volume 14.Issue 11.2006.pp.1189-1202
[41]C.Steiger,H.Walder and M.Platzner,Operating systems for reconfigurable embedded platforms:online scheduling of real-time tasks[J].IEEE Transactions on Computers.2004.Vol(53),pp.1393-1407.
[42]周博.可重构计算的操作系统支持研究[D].上海:复旦大学计算机与信息技术系.2006.
[43]Hinkelmann.H,Gunberg.A,Zipf.P,etc.Multitasking Support for Dynamically Reconfigurable Systems[J].Field Programmable Logic and Applications.2006.pp.1-6
[44]D.Andrews,D.Niehaus,etc.Programming models for hybrid FPGA-cpu computational components:a missing link[J].Micro,2004.IEEE 24,pp.42-53
[45]Razali.J,David.A,Wesley.P.Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms[C].Parallel and Distributed Processing Symposium,2005.
[46]Erik Anderson,Jason Agron,Wesley Peck.Enabling a Uniform Programming Model across the Software/Hardware Boundary,FCCM 2006.
[47]H.Walder and M.Platzner,Non-Preemptive Multitasking on FPGAs:Task Placement and Footprint Transform[C].Proc.Int'l Conf.Eng.of Reconfigurable Systems and Algorithms(ERSA).2002.pp.24-30.
[48]齐骥等.基于硬件任务顶点的可重构系统资源管理算法[J].电子学报.2006(11)vol.34:2094-2098.
[49]Heng Tan,DeMara R.F.A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead[J].Reconfigurable Computing and FPGA's,2006.pp.1-5
[50]Z.Li,K.Compton and S.Hauck.Configuration caching management techniques for reconfigurable computing[C].IEEE Symposium on Field-Programmable Custom Computing Machines,2000.pp.22-36.
[51]C.Steiger,H.Walder and M.Platzner,Operating systems for reconfigurable embedded platforms:online scheduling of real-time tasks[J].IEEE Transactions on Computers.2004.53.pp.1393-1407
[52]C.Steiger,H.Walder and M.Platzner,Operating systems for reconfigurable embedded platforms:online scheduling of real-time tasks[J].IEEE Transactions on Computers.2004.53.pp.1393-1407
[53]Q.Wei-Dong,Z.Bo,C.Yan and P.Cheng-Lian.Fast on-line real-time scheduling algorithm for reconfigurable computing[C].Proceedings of the Ninth International Conference on Computer Supported Cooperative Work in Design.2005.2.pp.793-798.
[54]封建,卢国栋,张旭东.图像编码基础和小波压缩技术—原理、算法和标准[M].2004.清华大学出版社
[55]程正兴.小波分析算法与应用[M].西安:西安交通大学出版社,2003,3.成礼智,郭汉伟.小波与离散变换理论与工程实践[M].北京:清华大学出版社,2005,1.
[56]Tan K C B,Arslan T,An embedded extension algorithm for the lifting based discrete wavelet transform in JPEG2000[A],Proceedings of IEEE International Conference on Acoustics,Speech,and Signal Processing (ICASSP),2002,4:3513-3516
[57]http://zhidao.baidu.com/question/25988501.html?fr=qrl
[58]Sweldens W.The Lifting Scheme:A Construction of Second Generation Wavelets[J].Siam J Math.Anal,1997,29(2).pp.511-546
[59]刘文耀.小波图像编码与专用VLSI设计[M].2006.电子工业出版社.ISBN:7121026929
[60]C.C.Liu,Y.H.Shiau,and J.M.Jou.Design and implementation of a progressive image coding chip based on the lifted wavelet transform[C].Proc.of the 11 th VLSI Design/CAD Symposium,Taiwan,August 2000.
[61]C.J Lian,K.F.Chen,H.H.Chen,and L.G.Chen,Lifting Based Discrete Wavelet Transform Architecture for JPEG2000[C].IEEE International Symposium on Circuits and Systems,Sydney,Australia,2001,pp.445-448
[62]Cheng-Yi Xiong;Jin-Wen Tian;Jian Liu.A note on "Flipping structure:an efficient VLSI architecture for lifting-based discrete wavelet Transform".Signal Processing[J].IEEE Transactions on Signal Processing.Volume 54,Issue 5,2006 Page(s):1910 - 1916
[63]朱柯.基于JPEG2000的静态图像压缩算法及VLSI实现的结构研究[D].复旦大学博士论文.2004
[64]T.Acharya and P.S.Tsai,JPEG2000 standard for image compression:concepts,algorithms and VLSI architectures[M].John Wiley & Sons,Hoboken,New Jersey,2004.
[65]Tinku Acharya,Chaitali Chakrabarti.A Survey on Lifting-based Discrete Wavelet Transform Architectures[J].Journal of VLSI Signal Processing Systems.Volume 42.Issue 3.2006.Pages:321 - 339
[66]Wei-Hsin Chang,Yew-San Lee,Wen-shiaw Peng,Chen-Yi Lee.A line-based,memory efficient and programmable architecture for 2D DWT using lifting sheme[C].IEEE International Symposium on Circuits and Systems,2001.
[67]C.-T.Huang,E-C.Tseng,and L.-G.Chen.Memory analysis and architecture for two-dimensional discrete wavelet transform[C].Proceedings of the IEEE Int.Conf.on Acoustics,Speech and Signal Processing,2004,pp.V 13-V 16.
[68]C.J Lian,K.F.Chen,H.H.Chen,and L.G.Chen.Lifting Based discrete wavelet transform architecture for JPEG2000[C].IEEE International Symposium on Circuits and Systems,Sydney,Australia,2001,pp.445-448
[69]Chao-Tsung Huang,Po-Chih Tseng,Liang-Gee Chen,"Genetic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method[J].IEEE Transactions on Circuits and Systems for Video Technology,Volume 15,Issue 7,July 2005 Page(s):910-920
[70]Keshab K.Parhi.VLSI数字信号处理系统:设计与实现[M].机械工业出版社ISBN:711114108.2004
[71]Flipping C.T.Huang,P.C.Tseng,and L.G.Chen.Flipping structure:an efficient VLSI architecture for lifting-based discrete wavelet transform[J]. IEEE Transactions on Signal Processing, 2004, pp. 1080-1089.
[72] Jain, R. , Panda, P.R. An efficient pipelined VLSI architecture for lifting-based 2D-discrete wavelet transform [C]. Int. Conf. on Circuits and Systems, 2007, pp.1377-1380.
[73]Bing-Fei Wu, Chung-Fu Lin. A high-performance and memory efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec [J]. IEEE Transactions on Circuits and Systems for Video Technology, Volume 15, Issue 12. Dec. 2005. Page(s):1615 - 1628
[2] S. Hauck. The Roles of FPGAs in Reprogrammable Systems [J]. Proceedings of the IEEE, Vol. 86, No. 4, pp. 615-638, April, 1998
[3] Vassiliadis, Stamatis; Soudris, Dimitrios (Eds.). Fine- and Coarse-Grain Reconfigurable Computing. 2007, XVI, 384 p. ISBN: 978-1-4020-6504-0
[4] http://www.idcnews.net/html/edu/hardwaretechnology/20070411/231281 .html
[5] http://www.altera.com.cn/products/devices/stratix3/st3-index.jsp
[6] Brown S, Francis R, Rose J, et al. Field-programmable gate arrays [M] Norwell: Kluwer, 1992.
[7] http://brass.cs.berkeley.edu/
[8] http://brass.cs.berkeley.edu/SCORE/
[9] http://www.eecg.toronto.edu/-jece/OneChip/
[10]Actel Corp, "VariCore Embedded Programmable Gate Array Core (EPGA) 0.18μm Family", Datasheet, December 2001. 2.
[11] http://www.atmel.com/products/FPSLIC/default.asp
[12]Gericota M.G, Alves G.R, Silva M.L, Ferreira, J.M. Run-time management of logic resources on reconfigurable systems [C]. Design, Automation and Test in Europe Conference and Exhibition, 2003. pp.974 - 979
[13]http://www.acm.org/crossroads/xrds5-3/rcconcept.html
[14]Wim Sweldens. The Lifting Scheme: A Construction of Second Generation Wavelets [J]. SIAM Journal of Mathematical Analysis. 1997. pp.511-546
[15] http://www.jpeg.org/public/fcdl 5444-1 .pdf
[16] http://mcuol.com/download/upfile/2-SystemOnaProgrammableChip.pdf
[17] http://www.ece.cmu.edu/research/piperench/
[18]Hartenstein, Reiner. RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances. Parallel and Distributed Processing Symposium [M]. 2006. ISBN: 1-4244-0054-6
[19] Ralph D. Wittig. OneChip: An FPGA Processor with Reconfigurable Logic [D]. Master's thesis. University of Toronto, Department of Electrical and Computer Engineering, Toronto, Ontario, M5S 3G4, 1995.
[20]Philips S,Hauck S.Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip[C].ACM International Symposium on FPGA.2002.
[21]http://chameleon.ctit.utwente.nl/
[22]Nikolaos S.Voros and Konstantinos Masselos.Introduction to Reconfigurable Hardware.System Level Design of Reconfigurable Systems-on-Chip[M].2005.ISBN 978-0-387-26103-4(Print).pp.15-26
[23]Prakash Rashinkar等著.孙海半等译.系统芯片(SOC)验证方法与技术[M].电子工业出版社.
[24]Kamal,R.编著,陈曙晖等译.嵌入式系统:体系结构、编程设计[M].清华大学出版社.2005
[25]Compton.K,Hauck.S.Reconfigurable computing:A survey of systems and software[J].ACM Computing Surveys.2002.Vol(34).pp.171-210
[26]T.J.Todman,G.A.Constantinides.Reconfigurable computing:architectures and design methods[J].IEE Proc.-Comput.Digit.Tech.2005.Vol(152).pp.193-207
[27]http://www.acm.uiuc.edu/sigarch/projects/reconf/report_ 1.html
[28]http://www.ece.lsu.edu/vaidy/raw05
[29]T.J.Callahan,J.R.Hause.The Garp architecture and C compiler[J].Computer 2000(33) pp.62-69
[30]Claus.C,Muller.F.H,Zeppenfeld.J.A new framework to accelerate Virtex-Ⅱ Pro dynamic partial self-reconfiguration[C].Parallel and Distributed Processing Symposium.2007.pp.1-7
[31]Ullmann.M,Hubner.M,Becker.J.On-demand FPGA run-time system for flexible and dynamical reconfiguration[J].Journal of Embedded Systems.2006.Vol(1) pp.193-204
[32]K.Compton,Z.Li,J.Cooley,etc.Configuration Relocation and Defragmentation for Run-Time Reconfigurable Computing[J].Trans.Very Large Scale Integration(VLSI) Systems.2002.Vol(10).No.3,pp.209-220.
[33]Dynamically Reconfigurable Devices & Technology [R].http://dec.bournemouth.ac.uk/drhw_lib/technology.html.
[34]Two flows for Partial reconfiguration:Module based or difference based[R].Xilinx Inc.Xilinx Application Note 290,version 1.2 July 2004
[35]P.Sedcole,B.Blodget,T.Becker.Modular Dynamic Reconfiguration in Virtex FGPAs[J].Computers and Digital Techniques.2006.Vol(153)
[36]Brandon.B,Philip.J,Eric.K,etc.A Self-reconfiguring Platform[C].FPL 2003.pp.565-574.
[37]Delahaye.J.P.,Palicot.J,Moy.C,etc.Partial Reconfiguration of FPGAs for Dynamical Reconfiguration of a Software Radio Platform[J].Mobile and Wireless Communications.2007.pp.1-5
[38]Moscu.P,E.,Bertels,K,Vassiliadis.S.Dynamic hard-ware reconfigurations:Performance impact on mpeg2[C].In:Proceedings of SAMOS.Volume 3133.Samos,Greece,Computer Science.2004.pp.284-292
[39]Juanjo Noguera and Rosa M.Badia.HW/SW Codesign Techniques for Dynamically Reconfigurable Architectures[J].Transactions on VLSI.vol(10),No.4,AUGUST 2002:399-415
[40]Banerjee.S,Bozorgzadeh.E,Dutt.N.D.Integrating Physical Constraints in HW-SW Partitioning for Architectures with Partial Dynamic Reconfiguration[J].Transactions on Very Large Scale Integration Systems.Volume 14.Issue 11.2006.pp.1189-1202
[41]C.Steiger,H.Walder and M.Platzner,Operating systems for reconfigurable embedded platforms:online scheduling of real-time tasks[J].IEEE Transactions on Computers.2004.Vol(53),pp.1393-1407.
[42]周博.可重构计算的操作系统支持研究[D].上海:复旦大学计算机与信息技术系.2006.
[43]Hinkelmann.H,Gunberg.A,Zipf.P,etc.Multitasking Support for Dynamically Reconfigurable Systems[J].Field Programmable Logic and Applications.2006.pp.1-6
[44]D.Andrews,D.Niehaus,etc.Programming models for hybrid FPGA-cpu computational components:a missing link[J].Micro,2004.IEEE 24,pp.42-53
[45]Razali.J,David.A,Wesley.P.Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms[C].Parallel and Distributed Processing Symposium,2005.
[46]Erik Anderson,Jason Agron,Wesley Peck.Enabling a Uniform Programming Model across the Software/Hardware Boundary,FCCM 2006.
[47]H.Walder and M.Platzner,Non-Preemptive Multitasking on FPGAs:Task Placement and Footprint Transform[C].Proc.Int'l Conf.Eng.of Reconfigurable Systems and Algorithms(ERSA).2002.pp.24-30.
[48]齐骥等.基于硬件任务顶点的可重构系统资源管理算法[J].电子学报.2006(11)vol.34:2094-2098.
[49]Heng Tan,DeMara R.F.A Physical Resource Management Approach to Minimizing FPGA Partial Reconfiguration Overhead[J].Reconfigurable Computing and FPGA's,2006.pp.1-5
[50]Z.Li,K.Compton and S.Hauck.Configuration caching management techniques for reconfigurable computing[C].IEEE Symposium on Field-Programmable Custom Computing Machines,2000.pp.22-36.
[51]C.Steiger,H.Walder and M.Platzner,Operating systems for reconfigurable embedded platforms:online scheduling of real-time tasks[J].IEEE Transactions on Computers.2004.53.pp.1393-1407
[52]C.Steiger,H.Walder and M.Platzner,Operating systems for reconfigurable embedded platforms:online scheduling of real-time tasks[J].IEEE Transactions on Computers.2004.53.pp.1393-1407
[53]Q.Wei-Dong,Z.Bo,C.Yan and P.Cheng-Lian.Fast on-line real-time scheduling algorithm for reconfigurable computing[C].Proceedings of the Ninth International Conference on Computer Supported Cooperative Work in Design.2005.2.pp.793-798.
[54]封建,卢国栋,张旭东.图像编码基础和小波压缩技术—原理、算法和标准[M].2004.清华大学出版社
[55]程正兴.小波分析算法与应用[M].西安:西安交通大学出版社,2003,3.成礼智,郭汉伟.小波与离散变换理论与工程实践[M].北京:清华大学出版社,2005,1.
[56]Tan K C B,Arslan T,An embedded extension algorithm for the lifting based discrete wavelet transform in JPEG2000[A],Proceedings of IEEE International Conference on Acoustics,Speech,and Signal Processing (ICASSP),2002,4:3513-3516
[57]http://zhidao.baidu.com/question/25988501.html?fr=qrl
[58]Sweldens W.The Lifting Scheme:A Construction of Second Generation Wavelets[J].Siam J Math.Anal,1997,29(2).pp.511-546
[59]刘文耀.小波图像编码与专用VLSI设计[M].2006.电子工业出版社.ISBN:7121026929
[60]C.C.Liu,Y.H.Shiau,and J.M.Jou.Design and implementation of a progressive image coding chip based on the lifted wavelet transform[C].Proc.of the 11 th VLSI Design/CAD Symposium,Taiwan,August 2000.
[61]C.J Lian,K.F.Chen,H.H.Chen,and L.G.Chen,Lifting Based Discrete Wavelet Transform Architecture for JPEG2000[C].IEEE International Symposium on Circuits and Systems,Sydney,Australia,2001,pp.445-448
[62]Cheng-Yi Xiong;Jin-Wen Tian;Jian Liu.A note on "Flipping structure:an efficient VLSI architecture for lifting-based discrete wavelet Transform".Signal Processing[J].IEEE Transactions on Signal Processing.Volume 54,Issue 5,2006 Page(s):1910 - 1916
[63]朱柯.基于JPEG2000的静态图像压缩算法及VLSI实现的结构研究[D].复旦大学博士论文.2004
[64]T.Acharya and P.S.Tsai,JPEG2000 standard for image compression:concepts,algorithms and VLSI architectures[M].John Wiley & Sons,Hoboken,New Jersey,2004.
[65]Tinku Acharya,Chaitali Chakrabarti.A Survey on Lifting-based Discrete Wavelet Transform Architectures[J].Journal of VLSI Signal Processing Systems.Volume 42.Issue 3.2006.Pages:321 - 339
[66]Wei-Hsin Chang,Yew-San Lee,Wen-shiaw Peng,Chen-Yi Lee.A line-based,memory efficient and programmable architecture for 2D DWT using lifting sheme[C].IEEE International Symposium on Circuits and Systems,2001.
[67]C.-T.Huang,E-C.Tseng,and L.-G.Chen.Memory analysis and architecture for two-dimensional discrete wavelet transform[C].Proceedings of the IEEE Int.Conf.on Acoustics,Speech and Signal Processing,2004,pp.V 13-V 16.
[68]C.J Lian,K.F.Chen,H.H.Chen,and L.G.Chen.Lifting Based discrete wavelet transform architecture for JPEG2000[C].IEEE International Symposium on Circuits and Systems,Sydney,Australia,2001,pp.445-448
[69]Chao-Tsung Huang,Po-Chih Tseng,Liang-Gee Chen,"Genetic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method[J].IEEE Transactions on Circuits and Systems for Video Technology,Volume 15,Issue 7,July 2005 Page(s):910-920
[70]Keshab K.Parhi.VLSI数字信号处理系统:设计与实现[M].机械工业出版社ISBN:711114108.2004
[71]Flipping C.T.Huang,P.C.Tseng,and L.G.Chen.Flipping structure:an efficient VLSI architecture for lifting-based discrete wavelet transform[J]. IEEE Transactions on Signal Processing, 2004, pp. 1080-1089.
[72] Jain, R. , Panda, P.R. An efficient pipelined VLSI architecture for lifting-based 2D-discrete wavelet transform [C]. Int. Conf. on Circuits and Systems, 2007, pp.1377-1380.
[73]Bing-Fei Wu, Chung-Fu Lin. A high-performance and memory efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec [J]. IEEE Transactions on Circuits and Systems for Video Technology, Volume 15, Issue 12. Dec. 2005. Page(s):1615 - 1628