星载信号处理平台单粒子效应检测与加固技术研究
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摘要
卫星技术在国民经济和以信息化为特征的新军事变革中发挥着越来越突出的作用。随着技术的发展,卫星平台和载荷对诸如FPGA、DSP等超大规模集成电路的依赖性越来越强。作为空间电子仪器设备的关键信号处理器件,FPGA和DSP自开始应用以来,单粒子效应就备受关注。器件的集成度越高,单粒子效应的影响就越显著,单粒子效应故障检测与加固设计已经成为空间电子仪器设计必须慎重考虑的问题。
本文以星载测控/通信信号处理平台的研制为背景,以提高FPGA和DSP的抗单粒子效应能力为研究目标,研究了FPGA和DSP的单粒子效应故障分析模型与故障特性、单粒子效应故障检测与加固设计方法和基于单粒子效应故障特性的故障注入验证技术。主要研究内容如下:
(1)根据FPGA和DSP单粒子效应故障的特点,建立了单粒子效应故障分析模型,提出了单粒子效应故障在FPGA和DSP中的伴随特性,为FPGA和DSP的单粒子效应研究提供了一个新的途径;针对FPGA和DSP位置不可访问故障的注入问题,以伴随特性为依据,研究了FPGA和DSP位置不可访问故障的模型修正方法和注入过程,提高了单粒子效应故障注入的故障覆盖度和访问深度;
(2)针对FPGA单粒子效应故障的检测与加固设计问题,根据单粒子效应故障的伴随特性,从布局布线的角度提出了基于“逻辑探针”的FPGA单粒子效应故障间接检测方法,降低了单粒子效应故障检测带来的资源与性能的损失;分析了FPGA配置存储器单粒子翻转引起的多个功能模块同时故障(SEU-MBE)的发生条件,提出了解决SEU-MBE问题的区域约束法和布线修正算法,提高了FPGA布线资源对单粒子效应故障的容错能力;
(3)针对DSP程序和数据存储区单粒子效应引起的程序执行流程紊乱问题,提出了基于缩短关键变量生存周期的三倍冗余设计、程序模块跳转区间监测和状态脉冲监测等方法,在提高DSP单粒子效应故障检测与容错性能的同时,减少了存储资源的消耗;
(4)针对非宇航级FPGA和DSP在空间仪器工程中的应用问题,提出了星载信号处理平台的金字塔形体系结构,研究了FPGA与DSP的高效动态重构技术,使FPGA和DSP的单粒子效应可靠度分别从0.63078和0.95336提高到0.99045和0.99901(工作时间为24小时,重构间隔为0.5小时),为非宇航级器件在空间仪器中的应用提供了一个解决方案。
实验结果显示:FPGA单粒子效应故障检测与加固设计方法能够在资源使用增加15%、速度性能降低10%的情况下,实现99.2%的单粒子效应检错概率和99.6%的单粒子效应容错概率;DSP单粒子效应故障检测与加固设计方法能够在程序存储量增加18%、执行时间增加15%的条件下,实现97.4%的单粒子效应检错概率和86.0%的单粒子效应容错概率;结合金字塔形结构与高效动态重构技术,星载信号处理平台中FPGA和DSP的单粒子效应综合检错概率和综合容错概率分别达到了98.9%和96.1%。
本文提出的设计方案与相关研究结论已经在多个型号的卫星信号处理平台中得到了应用。
Satellite technology plays a growing important role in national economy and revolution in military affairs, which is characteristic of informationization. And with the development of technology, satellite platform or payload relies deeply on very large scale integrated circuit (VLSIC), such as field programmable gate array (FPGA) and digital signal processor (DSP). As the key problem in signal processing platform degign, FPGA and DSP's single event effect (SEE) has been widely concerned ever since its first application in space electronic instrument. With the growth of integrated circuit's scale, high energy particles affect more severely on digital devices. Thus SEE error detection and mitigation techniques should be payed more attention in space electronic instrument design.
The research is based on the design of spaceborne TT-C (telemetry, tracking and command) and communication signal processing platform, and aims at improving FPGA and DSP's anti-SEE ability in space environment. Problems such as FPGA and DSP's analytical SEE error model and error characteristic, SEE error detection and mitigation techniques, fault injection-based verification method of SEE hardened design are studied in the thesis. And the main content can be summarized as follow.
(1) Based on FPGA and DSP's SEE error characteristic, the thesis proposes a novel analytical SEE error model for FPGA and DSP, and then studies the concomitant characteristic of SEE error, which is a new characteristic in error coupling and propagation. According to the fault injection problem of location-inaccessible errors of FPGA and DSP, a modified SEE fault model is proposed on the basis of SEE error's concomitant characteristic, which can improve the fault coverage and accessible depth of SEE fault injection model. The modified SEE error model gives a new point of view of SEE study for very large scale integration (VLSI) circuit.
(2) Based on SEE error's concomitant characteristic, a novel indirect error detection method is proposed from the aspect of FPGA's place and routing strategy,which is named logic probe (LP) and aimed to decrease the losses in resource and performance. Configuration memory's single event upset (SEU) can induce FPGA's multi-block error (SEU-MBE). The thesis analyzes the condition by which SEU-MBE happens and gives two solutions to SEU-MBE, Area Constrain Method (ACM) and Incremental Routing Algorithm (IRA). The proposed approaches show a remarkable increase of SEE immunity for FPGA's routing resource.
(3) According to program run flow's disturbance which is induced by the SEU of DSP's PM (program memory) or DM (data memory), the thesis proposes a life-shorten triple modular redundance (LS-TMR) method, a basic block jumping bound monitoring method (JBMM) and a state pulse monitoring method, which can reduce the upset rate of DSP's key variables and the memory consumption of error detection design.
(4) On the basis of SEE error detection and mitigation techniques of FPGA and DSP, a pyramid-like monitoring architecture for spaceborne signal processing platform (SSPP) is proposed. The pyramid-like monitoring architecture together with the high efficiency dynamic reconfiguration technique provide a possibility of applying non-radiation hardened FPGA or DSP in space electronic instrument. With the monitoring architecture, FPGA and DSP's anti-SEE reliability increase from 0.63078 and 0.95336 to 0.99045 and 0.99901, when the work period is 24 hours and reconfiguration interval is 0.5 hour.
Experimental results show that FPGA's error detection rate is 99.2% and error tolerance rate is 99.6% under the condition of 15% resource increase and 10% speed decrease. Also for DSP, error detection rate is 97.4% and error tolerance rate is 86.0% under the condition of 18% PM increase and 15% run time increase. With the pyramid-like monitoring architecture and the high efficiency dynamic reconfiguration technique, overall error detection and tolerance rate of FPGA and DSP in SSPP can reach to 98.9% and 96.1%.
Most of the techniques and conclusions proposed in the thesis have been applied in several satellite spaceborne signal processing platform.
本文以星载测控/通信信号处理平台的研制为背景,以提高FPGA和DSP的抗单粒子效应能力为研究目标,研究了FPGA和DSP的单粒子效应故障分析模型与故障特性、单粒子效应故障检测与加固设计方法和基于单粒子效应故障特性的故障注入验证技术。主要研究内容如下:
(1)根据FPGA和DSP单粒子效应故障的特点,建立了单粒子效应故障分析模型,提出了单粒子效应故障在FPGA和DSP中的伴随特性,为FPGA和DSP的单粒子效应研究提供了一个新的途径;针对FPGA和DSP位置不可访问故障的注入问题,以伴随特性为依据,研究了FPGA和DSP位置不可访问故障的模型修正方法和注入过程,提高了单粒子效应故障注入的故障覆盖度和访问深度;
(2)针对FPGA单粒子效应故障的检测与加固设计问题,根据单粒子效应故障的伴随特性,从布局布线的角度提出了基于“逻辑探针”的FPGA单粒子效应故障间接检测方法,降低了单粒子效应故障检测带来的资源与性能的损失;分析了FPGA配置存储器单粒子翻转引起的多个功能模块同时故障(SEU-MBE)的发生条件,提出了解决SEU-MBE问题的区域约束法和布线修正算法,提高了FPGA布线资源对单粒子效应故障的容错能力;
(3)针对DSP程序和数据存储区单粒子效应引起的程序执行流程紊乱问题,提出了基于缩短关键变量生存周期的三倍冗余设计、程序模块跳转区间监测和状态脉冲监测等方法,在提高DSP单粒子效应故障检测与容错性能的同时,减少了存储资源的消耗;
(4)针对非宇航级FPGA和DSP在空间仪器工程中的应用问题,提出了星载信号处理平台的金字塔形体系结构,研究了FPGA与DSP的高效动态重构技术,使FPGA和DSP的单粒子效应可靠度分别从0.63078和0.95336提高到0.99045和0.99901(工作时间为24小时,重构间隔为0.5小时),为非宇航级器件在空间仪器中的应用提供了一个解决方案。
实验结果显示:FPGA单粒子效应故障检测与加固设计方法能够在资源使用增加15%、速度性能降低10%的情况下,实现99.2%的单粒子效应检错概率和99.6%的单粒子效应容错概率;DSP单粒子效应故障检测与加固设计方法能够在程序存储量增加18%、执行时间增加15%的条件下,实现97.4%的单粒子效应检错概率和86.0%的单粒子效应容错概率;结合金字塔形结构与高效动态重构技术,星载信号处理平台中FPGA和DSP的单粒子效应综合检错概率和综合容错概率分别达到了98.9%和96.1%。
本文提出的设计方案与相关研究结论已经在多个型号的卫星信号处理平台中得到了应用。
Satellite technology plays a growing important role in national economy and revolution in military affairs, which is characteristic of informationization. And with the development of technology, satellite platform or payload relies deeply on very large scale integrated circuit (VLSIC), such as field programmable gate array (FPGA) and digital signal processor (DSP). As the key problem in signal processing platform degign, FPGA and DSP's single event effect (SEE) has been widely concerned ever since its first application in space electronic instrument. With the growth of integrated circuit's scale, high energy particles affect more severely on digital devices. Thus SEE error detection and mitigation techniques should be payed more attention in space electronic instrument design.
The research is based on the design of spaceborne TT-C (telemetry, tracking and command) and communication signal processing platform, and aims at improving FPGA and DSP's anti-SEE ability in space environment. Problems such as FPGA and DSP's analytical SEE error model and error characteristic, SEE error detection and mitigation techniques, fault injection-based verification method of SEE hardened design are studied in the thesis. And the main content can be summarized as follow.
(1) Based on FPGA and DSP's SEE error characteristic, the thesis proposes a novel analytical SEE error model for FPGA and DSP, and then studies the concomitant characteristic of SEE error, which is a new characteristic in error coupling and propagation. According to the fault injection problem of location-inaccessible errors of FPGA and DSP, a modified SEE fault model is proposed on the basis of SEE error's concomitant characteristic, which can improve the fault coverage and accessible depth of SEE fault injection model. The modified SEE error model gives a new point of view of SEE study for very large scale integration (VLSI) circuit.
(2) Based on SEE error's concomitant characteristic, a novel indirect error detection method is proposed from the aspect of FPGA's place and routing strategy,which is named logic probe (LP) and aimed to decrease the losses in resource and performance. Configuration memory's single event upset (SEU) can induce FPGA's multi-block error (SEU-MBE). The thesis analyzes the condition by which SEU-MBE happens and gives two solutions to SEU-MBE, Area Constrain Method (ACM) and Incremental Routing Algorithm (IRA). The proposed approaches show a remarkable increase of SEE immunity for FPGA's routing resource.
(3) According to program run flow's disturbance which is induced by the SEU of DSP's PM (program memory) or DM (data memory), the thesis proposes a life-shorten triple modular redundance (LS-TMR) method, a basic block jumping bound monitoring method (JBMM) and a state pulse monitoring method, which can reduce the upset rate of DSP's key variables and the memory consumption of error detection design.
(4) On the basis of SEE error detection and mitigation techniques of FPGA and DSP, a pyramid-like monitoring architecture for spaceborne signal processing platform (SSPP) is proposed. The pyramid-like monitoring architecture together with the high efficiency dynamic reconfiguration technique provide a possibility of applying non-radiation hardened FPGA or DSP in space electronic instrument. With the monitoring architecture, FPGA and DSP's anti-SEE reliability increase from 0.63078 and 0.95336 to 0.99045 and 0.99901, when the work period is 24 hours and reconfiguration interval is 0.5 hour.
Experimental results show that FPGA's error detection rate is 99.2% and error tolerance rate is 99.6% under the condition of 15% resource increase and 10% speed decrease. Also for DSP, error detection rate is 97.4% and error tolerance rate is 86.0% under the condition of 18% PM increase and 15% run time increase. With the pyramid-like monitoring architecture and the high efficiency dynamic reconfiguration technique, overall error detection and tolerance rate of FPGA and DSP in SSPP can reach to 98.9% and 96.1%.
Most of the techniques and conclusions proposed in the thesis have been applied in several satellite spaceborne signal processing platform.
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