CAN总线协议控制器的研究与设计
摘要
现场总线技术自70年代诞生至今,由于它在减少系统连线,简化系统安装、维护和管理,降低系统运行成本,增强系统稳定性等方面的优越性,引起人们的广泛注意,得到大范围的应用,引导了自动控制领域的一场革命。
CAN (Controller Area Network)总线是重要的现场总线之一,它遵从OSI模型,主要工作在数据链路层和物理层。CAN总线是一种全数字,多主机的异步串行现场总线,以其高性能、高可靠性以及灵活的设计正日益受到人们的重视。他有着高效的报文过滤机制,错误检测机制,高速的远距离传输,以及便利的应用层接口等良好性能。CAN总线目前已经在汽车工业、航空工业、工业控制等领域中得到了广泛应用,并正向更多的领域发展。
CAN总线控制器是CAN总线通讯协议的实现,将各个控制节点连接到总线的重要环节。本文设计了一个独立的CAN通讯协议控制模块,该模块完全符合CAN通讯协议2.0版,接口采用8051方式,控制简单。该控制器设计通过软件仿真以及FPGA测试,验证了其协议兼容性以及工作的稳定性。在实际应用中可以将其作为通讯模块通过FPGA实现,或者作为外设嵌入到SOC片上系统,实现灵活的CAN总线接口方案,极大方便了各种设备的总线接入。
From birth in 70s’to now, because of the advantages in reducing the bus line, simplifying the system setting, maintenance, and management, reducing the operating expense, and the improvement in stability, the technology of field bus is widely concerned. The widely application of it leads a revolution in automation.
CAN (Controller Area Network) bus is one of the most important field bus nowadays. It abides by the OSI system, mainly works in data link layer and physical layer. CAN bus is a fully digital, serial, asynchronous, multi-master communication protocol. As the preeminent performance, excellent stability, CAN bus is increasingly taken into account today. It has an effectively message filtering mechanism, error detecting system, and the ability of communication in the distance and high speed, and the convenient interface to application layer. Today, CAN bus is widely used in automotive, aviation industrial, and industrial control.
CAN bus protocol is implementation by the CAN bus controller, which is the interface of the controller to the CAN bus. The paper designed a standalone CAN bus controller module in HDL. This module is fully accordance to the 2.0 version of CAN bus communication protocol. It has the interface in 8051 style, which can be easily interface to 8 bits MCU. By simulation and verification on FPGA, the compatibility to the protocol and stability of the design is confirmed. As for application, the module can be instanced to the FPGA alone to work as a standalone CAN bus controller, or can be embedded to the SOC(system on chip), as the peripheral equipment of CPU. It provides a method of connecting the equipment to the CAN bus.
CAN (Controller Area Network)总线是重要的现场总线之一,它遵从OSI模型,主要工作在数据链路层和物理层。CAN总线是一种全数字,多主机的异步串行现场总线,以其高性能、高可靠性以及灵活的设计正日益受到人们的重视。他有着高效的报文过滤机制,错误检测机制,高速的远距离传输,以及便利的应用层接口等良好性能。CAN总线目前已经在汽车工业、航空工业、工业控制等领域中得到了广泛应用,并正向更多的领域发展。
CAN总线控制器是CAN总线通讯协议的实现,将各个控制节点连接到总线的重要环节。本文设计了一个独立的CAN通讯协议控制模块,该模块完全符合CAN通讯协议2.0版,接口采用8051方式,控制简单。该控制器设计通过软件仿真以及FPGA测试,验证了其协议兼容性以及工作的稳定性。在实际应用中可以将其作为通讯模块通过FPGA实现,或者作为外设嵌入到SOC片上系统,实现灵活的CAN总线接口方案,极大方便了各种设备的总线接入。
From birth in 70s’to now, because of the advantages in reducing the bus line, simplifying the system setting, maintenance, and management, reducing the operating expense, and the improvement in stability, the technology of field bus is widely concerned. The widely application of it leads a revolution in automation.
CAN (Controller Area Network) bus is one of the most important field bus nowadays. It abides by the OSI system, mainly works in data link layer and physical layer. CAN bus is a fully digital, serial, asynchronous, multi-master communication protocol. As the preeminent performance, excellent stability, CAN bus is increasingly taken into account today. It has an effectively message filtering mechanism, error detecting system, and the ability of communication in the distance and high speed, and the convenient interface to application layer. Today, CAN bus is widely used in automotive, aviation industrial, and industrial control.
CAN bus protocol is implementation by the CAN bus controller, which is the interface of the controller to the CAN bus. The paper designed a standalone CAN bus controller module in HDL. This module is fully accordance to the 2.0 version of CAN bus communication protocol. It has the interface in 8051 style, which can be easily interface to 8 bits MCU. By simulation and verification on FPGA, the compatibility to the protocol and stability of the design is confirmed. As for application, the module can be instanced to the FPGA alone to work as a standalone CAN bus controller, or can be embedded to the SOC(system on chip), as the peripheral equipment of CPU. It provides a method of connecting the equipment to the CAN bus.
引文
[1] CAN SPECIFICATION 1991. PHILIPS Semiconductors 公司.
[2] 现场总线的特点与发展 [工矿自动化] 吕岗, 谭得健, 马方清
[3] 现场总线技术及发展趋势 [上海海事大学学报] 崔知进
[4] CAN 总线及 Device Net 现场总线[控制工程] CHEN ZhiFeng
[5] 现场总线技术在控制系统中的应用研究 [信息技术与信息化] 赵义强,王继祥,郭向亮,任兰杰.
[6] CAN bus termination circuits and CAN bus auto-termination methods RO Leyva - US Patent 6,587,968, 2003
[7] 现场总线 CAN 原理与应用技术,北京:北京航空航天大学出版社,2003,饶运涛等
[8] Controller Area Network: Basics, Protocols, Chips and Applications K Etschberger - 2001 - IXXAT Automation.
[9] Finite-state analysis of the CAN bus protocol M van Osch, SA Smolka - High Assurance Systems Engineering, 2001
[10] CAN 总线通信协议的分析和实现,计算机工程,2002,2 蒋建文.
[11] CAN Specification 2.0 protocol and implementations. Szylowski.Craig P.(Intel Corp).
[12] Rapid prototyping of a CAN-bus controller. Krischbaum A,Renner F M,Wilmes A, et al.
[13] Texas Instruments.3.3V CAN Transceivers.2002.
[14] Philips Semiconductors, Philips SJA1000 Stand-alone CAN controller Data Sheet, 2000, http://www.semiconductors.philips.com.
[15] LPC2000 系列的 CAN 总线验收滤波器应用 [单片机与嵌入式系统应用] 曹均平, 王长林.
[16] A cost-effective CAN MCU-solution. Embacher M. Electron Prod Des.1996,17(4):42～47.
[17] Calculating Controller Area Network (CAN) Message Response Times K Tindell, A Burns, AJ Wellings - Control Engineering Practice, 1995
[18] CAN 通信中位定时的容差分析研究[测控技术] 王志萍, 张东来.
[19] CAN 总线系统位定时参数的选择 [青岛科技大学学报(自然科学版)] 张彦军, 刘靖宇.
[20] The Configuration of the CAN Bit Timing http://www.can.bosch.com
[21] CAN 总线通讯速率设定 The Configuration of Bit Rate on the CAN Bus [机械制造与自动化] 温小南, 朱春雷.
[22] CAN 总线中位定时的设定方法 [河北师范大学学报(自然科学版)] 张健.
[23] Rapid prototyping of a communication controller for the CAN bus. A Winter, D Bittruf, Y Tanurhan, KD Muller-Glaser
[24] 定时控制电器的可编程逻辑器件的实现 [西南科技大学学报] 刘桂华, 马建国, 于春梅.
[25] Philips Semiconductors, Determination of Bit Timing Parameters for the CAN Controller SJA1000 AN97046 http://www.semiconductors.philips.com 1997.
[26] 高速同步总线的时序设计 [系统工程与电子技术] 王砚方, 刘树彬, 安琪, 张庆民.
[27] 一种全数字位同步检测算法 [电讯技术] 林华杰, 史浩山.
[28] CAN 协议的错误处理及位定时 [汽车电器 Auto Electric Parts] 周泉.
[29] CAN 总线时间触发机制的实现 [中国工程科学 ] 吕伟杰, 刘鲁源, 王毅新.
[30] 时间触发的 CAN 协议 [兵工自动化] 牛德青, 岳曾敬.
[31] CAN 总线中循环冗余校验码的原理及其电路实现 [电子技术应用] 石龙海, 李明, 李书瑞.
[32] 循环冗余校验码算法的分析及 VHDL 语言实现 [计算机与数字工程] 夏泽中, 柴庆芬.
[33] CRC 检错探究 [科技创业月刊] 谭明新, 李瑞, 余英, 刘海峰.
[34] 循环冗余校验在 1-Wire 器件中的设计与实现 [太原城市职业技术学院学报] 魏苑琦, 黄智
[35] 循环冗余校验方法研究 [微处理机] 王彩荣, 李晓毅, 黄玉基.
[36] CRC 循环冗余校验码并行算法的 FPGA 实现 [有线电视技术] 石林艳, 罗汉文.
[37] Verilog HDL 数字电路的设计 [中国测试技术 China Measurement Technology] 邓云祥, 孟劲松, 苏燕辰.
[38] EDA 技术中的硬件描述语言[厦门理工学院学报] 庄静竹.
[39] The Verilog (r) Hardware Description Language. DE Thomas, PR Moorby - 2002
[40] 用 Verilog HDL 进行 FPGA 设计的一些基本方法[微计算机信息] 袁本荣, 刘万春, 贾云得, 朱玉文.
[41] Verilog HDL 设计实例及其仿真与综合[电子工程师] 应建华, 邹雪城, 陈朝阳, 王长宏.
[42] State Machine Design Techniques for Verilog and VHDL. S Golson - Synopsys Journal of High-Level Design, 1994
[43] 基于 Verilog HDL 的可综合有限状态机设计 [电子工程师] 魏芳, 刘志军, 王立华.
[44] Finite state machine trace analysis program. SS Palnitkar, PSH Kuang - Verilog HDL Conference, 1994
[45] FPGA 同步设计技术[无线通信技术] 李向涛, 仵国锋.
[46] FPGA 同步设计及实现 [重庆邮电大学学报(自然科学版)] 黄晓革.
[47] 数字同步电路的 FPGA 集成设计[长沙电力学院学报(自然科学版)] 李迎九, 汪鲁才.
[48] 基于 FPGA 的数字复接系统帧同步器设计与实现[国外电子元器件] 张景悦, 王明磊, 王莹.
[49] 基于 FPGA 的非对称同步 FIFO 设计[电子设计应用] 张明, 王礼平.
[50] 同步异步通信转换的 CPLD/FPGA 设计[微型电脑应用] 田小芳, 熊超, 陆起涌.
[51] FPGA/CPLD 同步设计若干问题浅析[自动化与仪器仪表] 彭俊峰, 宋家友, 崔建华.
[52] 可编程器件设计中跨时钟域的同步设计问题[华东师范大学学报(自然科学版)] 雷剑虹, 金之诚, 沈建国.
[53] 专用同步串行通信接口电路的 FPGA 实现[工业控制计算机] 宋晓明, 谢维达.
[54] Hardware simulation and design verification system and method. WC Steinmetz Jr - US Patent 5,600,579, 1997
[2] 现场总线的特点与发展 [工矿自动化] 吕岗, 谭得健, 马方清
[3] 现场总线技术及发展趋势 [上海海事大学学报] 崔知进
[4] CAN 总线及 Device Net 现场总线[控制工程] CHEN ZhiFeng
[5] 现场总线技术在控制系统中的应用研究 [信息技术与信息化] 赵义强,王继祥,郭向亮,任兰杰.
[6] CAN bus termination circuits and CAN bus auto-termination methods RO Leyva - US Patent 6,587,968, 2003
[7] 现场总线 CAN 原理与应用技术,北京:北京航空航天大学出版社,2003,饶运涛等
[8] Controller Area Network: Basics, Protocols, Chips and Applications K Etschberger - 2001 - IXXAT Automation.
[9] Finite-state analysis of the CAN bus protocol M van Osch, SA Smolka - High Assurance Systems Engineering, 2001
[10] CAN 总线通信协议的分析和实现,计算机工程,2002,2 蒋建文.
[11] CAN Specification 2.0 protocol and implementations. Szylowski.Craig P.(Intel Corp).
[12] Rapid prototyping of a CAN-bus controller. Krischbaum A,Renner F M,Wilmes A, et al.
[13] Texas Instruments.3.3V CAN Transceivers.2002.
[14] Philips Semiconductors, Philips SJA1000 Stand-alone CAN controller Data Sheet, 2000, http://www.semiconductors.philips.com.
[15] LPC2000 系列的 CAN 总线验收滤波器应用 [单片机与嵌入式系统应用] 曹均平, 王长林.
[16] A cost-effective CAN MCU-solution. Embacher M. Electron Prod Des.1996,17(4):42～47.
[17] Calculating Controller Area Network (CAN) Message Response Times K Tindell, A Burns, AJ Wellings - Control Engineering Practice, 1995
[18] CAN 通信中位定时的容差分析研究[测控技术] 王志萍, 张东来.
[19] CAN 总线系统位定时参数的选择 [青岛科技大学学报(自然科学版)] 张彦军, 刘靖宇.
[20] The Configuration of the CAN Bit Timing http://www.can.bosch.com
[21] CAN 总线通讯速率设定 The Configuration of Bit Rate on the CAN Bus [机械制造与自动化] 温小南, 朱春雷.
[22] CAN 总线中位定时的设定方法 [河北师范大学学报(自然科学版)] 张健.
[23] Rapid prototyping of a communication controller for the CAN bus. A Winter, D Bittruf, Y Tanurhan, KD Muller-Glaser
[24] 定时控制电器的可编程逻辑器件的实现 [西南科技大学学报] 刘桂华, 马建国, 于春梅.
[25] Philips Semiconductors, Determination of Bit Timing Parameters for the CAN Controller SJA1000 AN97046 http://www.semiconductors.philips.com 1997.
[26] 高速同步总线的时序设计 [系统工程与电子技术] 王砚方, 刘树彬, 安琪, 张庆民.
[27] 一种全数字位同步检测算法 [电讯技术] 林华杰, 史浩山.
[28] CAN 协议的错误处理及位定时 [汽车电器 Auto Electric Parts] 周泉.
[29] CAN 总线时间触发机制的实现 [中国工程科学 ] 吕伟杰, 刘鲁源, 王毅新.
[30] 时间触发的 CAN 协议 [兵工自动化] 牛德青, 岳曾敬.
[31] CAN 总线中循环冗余校验码的原理及其电路实现 [电子技术应用] 石龙海, 李明, 李书瑞.
[32] 循环冗余校验码算法的分析及 VHDL 语言实现 [计算机与数字工程] 夏泽中, 柴庆芬.
[33] CRC 检错探究 [科技创业月刊] 谭明新, 李瑞, 余英, 刘海峰.
[34] 循环冗余校验在 1-Wire 器件中的设计与实现 [太原城市职业技术学院学报] 魏苑琦, 黄智
[35] 循环冗余校验方法研究 [微处理机] 王彩荣, 李晓毅, 黄玉基.
[36] CRC 循环冗余校验码并行算法的 FPGA 实现 [有线电视技术] 石林艳, 罗汉文.
[37] Verilog HDL 数字电路的设计 [中国测试技术 China Measurement Technology] 邓云祥, 孟劲松, 苏燕辰.
[38] EDA 技术中的硬件描述语言[厦门理工学院学报] 庄静竹.
[39] The Verilog (r) Hardware Description Language. DE Thomas, PR Moorby - 2002
[40] 用 Verilog HDL 进行 FPGA 设计的一些基本方法[微计算机信息] 袁本荣, 刘万春, 贾云得, 朱玉文.
[41] Verilog HDL 设计实例及其仿真与综合[电子工程师] 应建华, 邹雪城, 陈朝阳, 王长宏.
[42] State Machine Design Techniques for Verilog and VHDL. S Golson - Synopsys Journal of High-Level Design, 1994
[43] 基于 Verilog HDL 的可综合有限状态机设计 [电子工程师] 魏芳, 刘志军, 王立华.
[44] Finite state machine trace analysis program. SS Palnitkar, PSH Kuang - Verilog HDL Conference, 1994
[45] FPGA 同步设计技术[无线通信技术] 李向涛, 仵国锋.
[46] FPGA 同步设计及实现 [重庆邮电大学学报(自然科学版)] 黄晓革.
[47] 数字同步电路的 FPGA 集成设计[长沙电力学院学报(自然科学版)] 李迎九, 汪鲁才.
[48] 基于 FPGA 的数字复接系统帧同步器设计与实现[国外电子元器件] 张景悦, 王明磊, 王莹.
[49] 基于 FPGA 的非对称同步 FIFO 设计[电子设计应用] 张明, 王礼平.
[50] 同步异步通信转换的 CPLD/FPGA 设计[微型电脑应用] 田小芳, 熊超, 陆起涌.
[51] FPGA/CPLD 同步设计若干问题浅析[自动化与仪器仪表] 彭俊峰, 宋家友, 崔建华.
[52] 可编程器件设计中跨时钟域的同步设计问题[华东师范大学学报(自然科学版)] 雷剑虹, 金之诚, 沈建国.
[53] 专用同步串行通信接口电路的 FPGA 实现[工业控制计算机] 宋晓明, 谢维达.
[54] Hardware simulation and design verification system and method. WC Steinmetz Jr - US Patent 5,600,579, 1997