基于VMM的图像处理子系统验证平台的研究与设计
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摘要
功能验证已经成为当今超大规模专用集成电路和系统级芯片项目开发的瓶颈。传统的定向测试验证方法已经不能满足对高复杂度设计进行完备验证的要求。为提高验证生产率,一系列先进的功能验证方法和验证语言得到了发展。在此基础上,验证方法学为模块和系统级验证提供了完整的解决方案,使验证平台能够具备更高的自动化程度和可复用性,从而提高了验证效率。
本文研究了图像处理子系统的功能验证,该系统是课题组开发的多制式视频显示后处理芯片中的核心算法单元,用于在相同帧频下实现多种VESA视频制式之间的转换。本文以VMM验证方法学为指导,为图像处理子系统开发验证计划,确定需要覆盖检查的功能点。在验证平台的设计上,采用VMM验证方法学推荐的分层式验证平台结构,使用SystemVerilog语言自行开发验证组件,完成验证平台的搭建。本文研究的图像处理子系统验证平台能够生成36种VESA视频信号,支持对待测设计的输出时序和图像处理质量进行分析和评估。验证平台集成了约束随机化验证、功能覆盖率驱动验证、事务级验证和断言验证等先进的验证方法,同时,通过使用蓝图模式和回调技术,支持多种测试案例的生成,增强了验证环境的稳定性,提高了验证组件的可复用性。本文还研究和实现了一种动态约束修正技术,使验证过程中功能覆盖率的提升能够受用户控制,提高了验证平台的可控制性。
仿真验证实践证明,本文研究的验证平台能够根据用户配置,执行随机验证和定向测试等多种测试案例,具有较高的自动化程度,能够有效提高验证效率。
Functional verification has become the bottleneck of projects that developing Very Large Scale ASIC and System-On-Chip. Directed test, which is the traditional verification method, can not meet the requirement that verifying a complex design fully. For the purpose of obtaining higher verification productivity, a series of advanced methods and languages have been developed. Based on the above progress, the verification methodology offers a complete solution for Module-Level and System-Level verification, which improves the verification efficiency by making testbench more automatic and reusable.
The functional verification for Image Processing Subsystem is studied in this thesis. This system, which is the core algorithm unit of a Multi-standard Video Post Processing Chip, is used to implement the conversion among multiple VESA video formats with the same frame frequency. In this thesis, the Verification Methodology Manual (VMM) is adopted as the main principle for developing verification plan that describes the function points to be covered. The testbench is built according to the layered structure which is recommended by VMM, and all the components are self-designed. The testbench can generate 36 kinds of VESA video formats, and supports the checking of the correctness of DUT’s output timing and the evaluating of the image processing quality of DUT. Several advanced technologies are integrated into the testbench, such as constrained random test, coverage-driven verification, transaction-level verification and assertion, while Blueprint and Callback are also used for supporting the executing of more test cases, which enhances the stability of the verification environment and improves the reusability. A dynamic constraint modifying technology is also studied, which enables users to control the coverage’s increase.
Simulation result shows that this testbench can support multiple test cases including directed test and random test according to user’s configuration, and its high-level automation is also proved, which will improve the verification efficiency effectively.
本文研究了图像处理子系统的功能验证,该系统是课题组开发的多制式视频显示后处理芯片中的核心算法单元,用于在相同帧频下实现多种VESA视频制式之间的转换。本文以VMM验证方法学为指导,为图像处理子系统开发验证计划,确定需要覆盖检查的功能点。在验证平台的设计上,采用VMM验证方法学推荐的分层式验证平台结构,使用SystemVerilog语言自行开发验证组件,完成验证平台的搭建。本文研究的图像处理子系统验证平台能够生成36种VESA视频信号,支持对待测设计的输出时序和图像处理质量进行分析和评估。验证平台集成了约束随机化验证、功能覆盖率驱动验证、事务级验证和断言验证等先进的验证方法,同时,通过使用蓝图模式和回调技术,支持多种测试案例的生成,增强了验证环境的稳定性,提高了验证组件的可复用性。本文还研究和实现了一种动态约束修正技术,使验证过程中功能覆盖率的提升能够受用户控制,提高了验证平台的可控制性。
仿真验证实践证明,本文研究的验证平台能够根据用户配置,执行随机验证和定向测试等多种测试案例,具有较高的自动化程度,能够有效提高验证效率。
Functional verification has become the bottleneck of projects that developing Very Large Scale ASIC and System-On-Chip. Directed test, which is the traditional verification method, can not meet the requirement that verifying a complex design fully. For the purpose of obtaining higher verification productivity, a series of advanced methods and languages have been developed. Based on the above progress, the verification methodology offers a complete solution for Module-Level and System-Level verification, which improves the verification efficiency by making testbench more automatic and reusable.
The functional verification for Image Processing Subsystem is studied in this thesis. This system, which is the core algorithm unit of a Multi-standard Video Post Processing Chip, is used to implement the conversion among multiple VESA video formats with the same frame frequency. In this thesis, the Verification Methodology Manual (VMM) is adopted as the main principle for developing verification plan that describes the function points to be covered. The testbench is built according to the layered structure which is recommended by VMM, and all the components are self-designed. The testbench can generate 36 kinds of VESA video formats, and supports the checking of the correctness of DUT’s output timing and the evaluating of the image processing quality of DUT. Several advanced technologies are integrated into the testbench, such as constrained random test, coverage-driven verification, transaction-level verification and assertion, while Blueprint and Callback are also used for supporting the executing of more test cases, which enhances the stability of the verification environment and improves the reusability. A dynamic constraint modifying technology is also studied, which enables users to control the coverage’s increase.
Simulation result shows that this testbench can support multiple test cases including directed test and random test according to user’s configuration, and its high-level automation is also proved, which will improve the verification efficiency effectively.
引文
[1]Chen Wenwei, Zhang Jinyi, Li Jiao et al,Study On a Mixed Verification Strategy for IP-Based SoC Design, IEEE, Proceedings of Conference on High Density Microsystem Design and Packaging and Component Failure Analysis 2005, NJ USA:IEEE Computer Society, 2005, 1-4
[2]Janick Bergeron, Eduard Cerny, Alan Hunter et al, Verification Methodology Manual for SystemVerilog, NewYork: Springer Press, 2006. 2-11
[3]Chris Spear, SystemVerilog for Verification, NewYork: Springer Press, 2008. 6-10
[4]Shujun Deng, Zhiqiu Kong, Jinian Bian et al, Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints, IEEE, Proceedings of the ASP-DAC 2009, NJ USA: IEEE, 2009, 769-774
[5]许彤,吕涛,基于覆盖率模型的AMBA接口随机验证方法,计算机应用研究,2008,25(7):2078-2080, 2137
[6]韩霞,杨洪斌,吴悦,面向SOC的事务级验证研究,计算机技术与发展,2007,17(3):33-36
[7]JinShan Yu, Tun Li, QingPing Tan, The Use of UML Sequence Diagram for System-on-Chip System Level Transaction-based Functional Verification, IEEE, Proceedings of the World Congress om Intelligent Control and Automation,NJ USA: IEEE, 2006, 6173-6177
[8]孟庆,何乐年,沈海斌等,基于事务的SOC验证策略,半导体技术,2002,27(6):29-32
[9] Daniel Gro?e, Ulrich Kühne, Rolf Drechsler,Analyzing Functional Coverage in Bounded Model Checking, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(7): 1305-1315
[10] Sébastien Regimbal,Jean-Fran?ois Lemire,Yvon Savaria et al,Automating Functional Coverage Analysis Based on an Executable Specification, IEEE, Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications 2003, NJ USA: IEEE, 2003, 228-234
[11]Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou et al, A novel approach for functional coverage measurement in HDL, IEEE, Proceeds of the 2000 IEEE International Symposium on Circuits and Systems, NJ USA: IEEE, 2000, 217-220
[12] Ivan Kastelan, Zoran Krajacevic, Synthesizable SystemVerilog Assertions as a Methodology for SoC Verification, IEEE, Proceedings of Eastern European Conference on the Engineering of Computer Based Systems 2009, NJ USA: IEEE, 2009, 120-127
[13] Nicola Bombieri,Franco Fummi,Graziano Pravadelli et al,Hybird,Incremental Assertion-Based Verification for TLM Design Flow, IEEE Design and Test of Computers, 2007, 24(2): 140-152
[14]李洋洋,吴武臣,王龙伟等,基于断言的验证方法在UART模块中的应用研究,微电子学与计算机,2010,27(1):151-153,157
[15]江龙,马琪,基于事务的功能验证方法及其在设计验证中的运用,计算机与现代化,2008,10期:110-112
[16]Srikanth Vijayaraghavan, Meyyappan Ramanathan, SystemVerilog Assertion应用指南(陈俊杰等译),北京:清华大学出版社,2006. 5-6
[17]丁三川,基于SVA的视频信号处理芯片功能验证:[硕士学位论文],天津:天津大学,2007
[18]夏宇闻,Verilog数字系统设计教程,北京:北京航空航天大学出版社,2003.1-4
[19]Design Automation Standards Committee of the IEEE Computer Society, IEEE Std 1364-1995, IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, NewYork: IEEE, 1995
[20]Design Automation Standards Committee of the IEEE Computer Society, IEEE Std 1364-2001, IEEE Standard Verilog Hardware Description Language, NewYork: IEEE, 2001
[21]Stuart Sutherland,Simon Davidmann,Peter Flake,SystemVerilog硬件设计及建模(于敦山等译),北京:科学出版社,2007.1-5
[22] Design Automation Standards Committee of the IEEE Computer Society and IEEE Standrads Association Corporate Advisory Group, IEEE Std 1800-2005, IEEE Standard for SystemVerilog-Unified Hardware Design, Specification and Verification Language, NewYork:IEEE, 2005
[23]Han Ke, Deng Zhongliang, Shu Qiong, Verification of AMBA Bus Model Using SystemVerilog, IEEE, Proceedings of the 8th International Conference on Electronic Measurement and Instruments 2007, NJ USA: IEEE, 2007, 1776-1780
[24]吕欣欣,刘淑芬,基于Synopsys VMM方法的FPGA验证技术,计算机应用,2009,29(9):2527-2529, 2533
[25]黄思远,邵智勇,于承兴等,VMM中功能覆盖率收敛技术,现代电子技术,2010,4期:16-18, 31
[26]Janick Bergeron, Eduard Cerny, Alan Hunter et al, Verification Methodology Manual for SystemVerilog, NewYork: Springer Press, 2006.104-127
[27]李宝魁,姚素英、张涛,视频格式转换芯片中的去隔行系统设计,电视技术,2005,11期:35-37, 40
[28]刘政林,刘菊,邹雪城等,一种新型运动自适应去隔行算法,微处理机,2008,29(6):116-118,121
[29]王南飞,姚素英,陆尧等,视频格式转换芯片中帧频提升算法及硬件实现,电子测量技术,2007,30(8):14-16, 62
[30]朱恩津,梁惠来,张涛,视频格式转换算法研究,电视技术,2006,1期:19-20,24
[31]Video Electronics Standards Association, VESA Monitor Timing Standard Ver1.0, Rev.1.0, CA: VESA, 2004
[2]Janick Bergeron, Eduard Cerny, Alan Hunter et al, Verification Methodology Manual for SystemVerilog, NewYork: Springer Press, 2006. 2-11
[3]Chris Spear, SystemVerilog for Verification, NewYork: Springer Press, 2008. 6-10
[4]Shujun Deng, Zhiqiu Kong, Jinian Bian et al, Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints, IEEE, Proceedings of the ASP-DAC 2009, NJ USA: IEEE, 2009, 769-774
[5]许彤,吕涛,基于覆盖率模型的AMBA接口随机验证方法,计算机应用研究,2008,25(7):2078-2080, 2137
[6]韩霞,杨洪斌,吴悦,面向SOC的事务级验证研究,计算机技术与发展,2007,17(3):33-36
[7]JinShan Yu, Tun Li, QingPing Tan, The Use of UML Sequence Diagram for System-on-Chip System Level Transaction-based Functional Verification, IEEE, Proceedings of the World Congress om Intelligent Control and Automation,NJ USA: IEEE, 2006, 6173-6177
[8]孟庆,何乐年,沈海斌等,基于事务的SOC验证策略,半导体技术,2002,27(6):29-32
[9] Daniel Gro?e, Ulrich Kühne, Rolf Drechsler,Analyzing Functional Coverage in Bounded Model Checking, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(7): 1305-1315
[10] Sébastien Regimbal,Jean-Fran?ois Lemire,Yvon Savaria et al,Automating Functional Coverage Analysis Based on an Executable Specification, IEEE, Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications 2003, NJ USA: IEEE, 2003, 228-234
[11]Chien-Nan Jimmy Liu, Chen-Yi Chang, Jing-Yang Jou et al, A novel approach for functional coverage measurement in HDL, IEEE, Proceeds of the 2000 IEEE International Symposium on Circuits and Systems, NJ USA: IEEE, 2000, 217-220
[12] Ivan Kastelan, Zoran Krajacevic, Synthesizable SystemVerilog Assertions as a Methodology for SoC Verification, IEEE, Proceedings of Eastern European Conference on the Engineering of Computer Based Systems 2009, NJ USA: IEEE, 2009, 120-127
[13] Nicola Bombieri,Franco Fummi,Graziano Pravadelli et al,Hybird,Incremental Assertion-Based Verification for TLM Design Flow, IEEE Design and Test of Computers, 2007, 24(2): 140-152
[14]李洋洋,吴武臣,王龙伟等,基于断言的验证方法在UART模块中的应用研究,微电子学与计算机,2010,27(1):151-153,157
[15]江龙,马琪,基于事务的功能验证方法及其在设计验证中的运用,计算机与现代化,2008,10期:110-112
[16]Srikanth Vijayaraghavan, Meyyappan Ramanathan, SystemVerilog Assertion应用指南(陈俊杰等译),北京:清华大学出版社,2006. 5-6
[17]丁三川,基于SVA的视频信号处理芯片功能验证:[硕士学位论文],天津:天津大学,2007
[18]夏宇闻,Verilog数字系统设计教程,北京:北京航空航天大学出版社,2003.1-4
[19]Design Automation Standards Committee of the IEEE Computer Society, IEEE Std 1364-1995, IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, NewYork: IEEE, 1995
[20]Design Automation Standards Committee of the IEEE Computer Society, IEEE Std 1364-2001, IEEE Standard Verilog Hardware Description Language, NewYork: IEEE, 2001
[21]Stuart Sutherland,Simon Davidmann,Peter Flake,SystemVerilog硬件设计及建模(于敦山等译),北京:科学出版社,2007.1-5
[22] Design Automation Standards Committee of the IEEE Computer Society and IEEE Standrads Association Corporate Advisory Group, IEEE Std 1800-2005, IEEE Standard for SystemVerilog-Unified Hardware Design, Specification and Verification Language, NewYork:IEEE, 2005
[23]Han Ke, Deng Zhongliang, Shu Qiong, Verification of AMBA Bus Model Using SystemVerilog, IEEE, Proceedings of the 8th International Conference on Electronic Measurement and Instruments 2007, NJ USA: IEEE, 2007, 1776-1780
[24]吕欣欣,刘淑芬,基于Synopsys VMM方法的FPGA验证技术,计算机应用,2009,29(9):2527-2529, 2533
[25]黄思远,邵智勇,于承兴等,VMM中功能覆盖率收敛技术,现代电子技术,2010,4期:16-18, 31
[26]Janick Bergeron, Eduard Cerny, Alan Hunter et al, Verification Methodology Manual for SystemVerilog, NewYork: Springer Press, 2006.104-127
[27]李宝魁,姚素英、张涛,视频格式转换芯片中的去隔行系统设计,电视技术,2005,11期:35-37, 40
[28]刘政林,刘菊,邹雪城等,一种新型运动自适应去隔行算法,微处理机,2008,29(6):116-118,121
[29]王南飞,姚素英,陆尧等,视频格式转换芯片中帧频提升算法及硬件实现,电子测量技术,2007,30(8):14-16, 62
[30]朱恩津,梁惠来,张涛,视频格式转换算法研究,电视技术,2006,1期:19-20,24
[31]Video Electronics Standards Association, VESA Monitor Timing Standard Ver1.0, Rev.1.0, CA: VESA, 2004