时间继电器智能测试仪研究
摘要
在电子设计领域,随着计算机技术、大规模集成电路技术、EDA(ElectronicsDesign Automation)技术的发展和可编程逻辑器件的广泛应用,传统的自下而上的数字电路设计方法、工具、器件已远远落后于当今技术的发展。基于EDA技术和硬件描述语言(VHDL)的自上而下的设计技术正在承担起越来越多的数字系统设计任务。本课题的时间继电器智能测试仪的设计就是采用自上向下的设计方法,用单片机作为系统的主要控制部件,实现对整个电路的测试信号控制、数据运算处理、键盘扫描和控制液晶显示器(LCD)的显示输出等。以一块现场可编程逻辑器件FPGA(Field Programmable Gate Array)芯片(ACEX 1K30),完成测时间继电器/测频、基准频率分频、时序逻辑控制、计数、输出等功能。在QuartusⅡ平台上,用VHDL语言编程完成了FPGA的软件设计、编译、调试、仿真和下载。当选择测时间继电器时,在AT89S52单片机控制下给出一个启动信号,由时间继电器信号控制的闸门信号打开,同时时间继电器的信号和时间基准信号分别被送入计数器的输入端开始计数,当闸门信号关闭时计数器都同步停止计数,单片机将FPGA内的12位十进制计数器的计数值读入其内存进行处理后,并将计数结果送LCD显示。通过对本地键盘或远地可程控面板操作,可以分别对测时间继电器/测频率进行控制,同时也可以对计数器的开启、停止计数功能进行控制,也可以对各个计数器进行初始化。该系统除了能够测量时间继电器时间段外,还可以测试信号的频率等。AT89S52单片机内含256字节RAM和8K字节快闪存储器,因此全部控制程序可装入单片机。系统将单片机的控制灵活性及FPGA芯片(ACEX1K30)的现场可编程性相结合,不仅大大缩短了开发研制周期、降低了设计成本,而且使本系统具有结构紧凑、体积小、重量轻、可靠性高,测量时间/频率范围宽、测量精度高等优点。填补了我军某型航空时间继电器智能测试仪的空白,具有较高的经济价值和军事价值。本文详细论述了系统各部分硬件电路组成,单片机和FPGA的软件编程设计以及自上而下的设计方法。
In the electronic field, along with the development of the computer technique, large scale integrate circuit technique and EDA (Electronics Design Automation) technique and aboard application of programmable logic device, traditional design methodology of digital circuit adopting bottom_up, tolls, devices has already dropped behind the development of the popular technique. Design technique adopting top_down are taking on more tasks of digital system design. The smart time relay meter design in this paper which adopts top_down design methodology uses the AT89S52 single chip computer as the main controlling parts. The AT89S52 single chip computer realizes test signal control, keyboard scan and output display of LCD. A FPGA (Field Programmable Gate Array) chip (ACEX 1K30) fulfills measuring time relay/measuring frequency, dividing frequency of time reference, timing logic control, count and output function. Under the flat of Quartus II, FPGA software designing, compiling, debugging, simulation and down are been carried out in VHDL(Very High Speed Integrated Circuit Hardware Description Language) language. A start signal is given under the controlling of AT89S52. when the choice of measuring time relay, strobe signal opens under the controlling of the time relay signal, the time relay signal and the bade time signals were sent to base counter input counting began at the same time, when the gates closed at the counter signals are synchronized to stop counting, the single chip computer would read 12 metric counting data to his memory in FPGA then process the counting data, and the last sent the results of the counting data to LCD display. Through the local keyboard or remote operation panel can be programmed, respectively measuring time relay / measuring frequency control, but also to counter the open, and stop counting functions of control, the various counters can also be initialized. In addition the system not only can test time of the time relay, but also can test the signal frequency. The single chip computer of AT89S52 includes 256 bytes of RAM and 8 K bytes of flash memory, so all controlling program can be downloads to the single chip computer. The system combines the controlling flexibility of single chip computer with programmable performance of FPGA chip (ACEX 1K30), so it can not only greatly shorten developed cycle, reducing the design costs, but also enable the system is compact, small size, weight light, high reliability measurement of time / frequency range wide, high precision advantages. It fills the blank of a certain type time relay of test for the smart instrument in my air force. It has a high economic and military value. This paper discusses in detail the different parts of the system hardware circuit, single chip computer, FPGA design, software programming and top-down design methods and so on.
In the electronic field, along with the development of the computer technique, large scale integrate circuit technique and EDA (Electronics Design Automation) technique and aboard application of programmable logic device, traditional design methodology of digital circuit adopting bottom_up, tolls, devices has already dropped behind the development of the popular technique. Design technique adopting top_down are taking on more tasks of digital system design. The smart time relay meter design in this paper which adopts top_down design methodology uses the AT89S52 single chip computer as the main controlling parts. The AT89S52 single chip computer realizes test signal control, keyboard scan and output display of LCD. A FPGA (Field Programmable Gate Array) chip (ACEX 1K30) fulfills measuring time relay/measuring frequency, dividing frequency of time reference, timing logic control, count and output function. Under the flat of Quartus II, FPGA software designing, compiling, debugging, simulation and down are been carried out in VHDL(Very High Speed Integrated Circuit Hardware Description Language) language. A start signal is given under the controlling of AT89S52. when the choice of measuring time relay, strobe signal opens under the controlling of the time relay signal, the time relay signal and the bade time signals were sent to base counter input counting began at the same time, when the gates closed at the counter signals are synchronized to stop counting, the single chip computer would read 12 metric counting data to his memory in FPGA then process the counting data, and the last sent the results of the counting data to LCD display. Through the local keyboard or remote operation panel can be programmed, respectively measuring time relay / measuring frequency control, but also to counter the open, and stop counting functions of control, the various counters can also be initialized. In addition the system not only can test time of the time relay, but also can test the signal frequency. The single chip computer of AT89S52 includes 256 bytes of RAM and 8 K bytes of flash memory, so all controlling program can be downloads to the single chip computer. The system combines the controlling flexibility of single chip computer with programmable performance of FPGA chip (ACEX 1K30), so it can not only greatly shorten developed cycle, reducing the design costs, but also enable the system is compact, small size, weight light, high reliability measurement of time / frequency range wide, high precision advantages. It fills the blank of a certain type time relay of test for the smart instrument in my air force. It has a high economic and military value. This paper discusses in detail the different parts of the system hardware circuit, single chip computer, FPGA design, software programming and top-down design methods and so on.
引文
[1][德]Elmar Schrufer著,殳伟群译,电测技术[M],北京:电子工业出版社,2005.2
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[31]孙华锦,基于VHDL语言的电子设计自动化及其应用[D],西安:西北工业大学,2001.10
[32]刘乐善,欧阳星明,刘学清编著,微型计算机接口技术及应用[M],武汉:华中科技大学出版社,2005.8
[33][英]M ichael J.Pont著,时间触发嵌入式系统设计模式:使用8051系列微控制器开发可靠应用[M],北京:中国电力出版社,2004.6
[34]武卫华,陈德宏,基于EDA技术的数字频率计芯片化的实现,电测与仪表[J],2004年第4期,P52-55
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[36]王建校,杨建国编著,51系列单片机及C51程序设计[M],北京:科学出版社,2002.4
[37]余成波,冯丽辉,潘盛辉编著,虚拟仪器技术与设计[M],重庆:重庆大学出版社,2006.7
[38]雷振山主编,LabVIEW 7 Express实用技术教程[M],北京:中国铁道出版社,2004.4
[39]雷勇主编,虚拟仪器设计与事件[M],北京:电子工业出版社,2005.3
[40]National Instrument Application Note 110 341398A-01[J],January 1998
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[42]黄智伟,王彦,陈琼等编著,FPGA系统设计与实践[M],北京:电子工业出版社,2005.1
[43]Sefan sjoholm,lennart Lindh,VHDL for designer[M]北京:清华大学出版社,2001
[2]沙占友编著,数字化测量技术与应用[M],北京:机械工业出版社,2004.3
[3]林占江等编著,电子测量技术[M],北京:电子工业出版社,2002
[4]古天祥,王厚军,习友宝等编著,电子测量原理[M],北京:机械工业出版社,2004.8
[5]姜维正,频率的精密测量方法应用[J],计算机技术与应用,2006年第4期,P63-65
[6]李宝营,赵永生等,基于单片机的等精度频率计设计[J],微计算机信息,2007年第23卷第9-2期,P152-154
[7]陈晓荣,蔡苹,周红全,基于单片机的频率测量的几种实用方法[J],工业仪表与自动化装置,2003年1月,P40-42
[8]孙杰,潘继飞,高精度时间间隔测量方法综述[J],计算机测量与控制,2007.15(2),P145-148
[9]阎石编著,数字电子技术基础(第四版)[M],北京:高等教育出版社,2001
[10]周立功,夏宇闻等编著,单片机与CPLD综合应用技术[M],北京:北京航空航天大学出版社,2003.8
[11]张永艳,基于复杂可编程逻辑器件及用VHDL语言编程的数字频率计的设计[D],呼和浩特:内蒙古大学,2004.9
[12]张兆莉,蔡永泉,王钰,基于FPGA的数字频率的设计与实现[J],自动化仪表,第27卷第1l1期 2006年11月,P10-13
[13]胡汗才主编,单片机原理及其接口技术[M],北京:清华大学出版社,2001.6
[14]黄智伟主编,FPGA系统设计与实践[M],北京:电子工业出版社,2005
[15]金琳,基于EDA技术的频率计系统设计[D],吉林:吉林大学 2007
[16]张毅刚,彭喜元,姜守达等编著,新编MCS-51单片机应用设计[M],哈尔滨:哈尔滨工业大学出版社,2003.7
[17]刘夫江,基于单片机和CPLD的等精度数字频率计设计[D],济南:山东大学,2007.7
[18]Keil Software CorP.,Keil Software-Cx51编译器用户手册[M],2001(编程)
[19]王道宪,贺名臣,刘伟编著,VHDL设计技术[M],北京:国防工业出版社,2003.8
[20]黄任主编,VHDL入门解惑经典实例经验总结[M],北京:北京航空航天大学出版社,2005.1
[21]James R.Armstrong,F.Gall Gray,VHDL Design Representation and Synthesis Second Edition[M];北京:机械工业出版社,2003.3
[22]李洪伟,袁斯华编著,基于QuartusⅡ的FPGA/CPLD设计[M],北京:电子工业出版社,2006.4
[23]王辉,殷颖,陈婷等编著,MAX+plusⅡ和QuartusⅡ应用与开发技巧[M],北京:机械工业出版社,2007.3
[24]潘松,黄继业等编著,EDA技术与VHDL[M],北京:北京科技出版社,2007.1
[25]黄仁欣主编,EDA技术实用教程[M],北京:清华大学出版社,2006.9
[26][美]Wayne Wolf著,基于FPGA的系统设计[M],北京:机械工业出版社,2006.5
[27]王开军,姜宇柏等编著,面向CPLD/FPGA的VHDL设计[M],北京:机械工业出版社,2007.6
[28]孟祥旭等编著,FPGA应用开发从实践到提高[M],北京:中国电力出版社,2007.4
[29]刘皖,何道君,谭明编著,FPGA设计与应用[M],北京:清华大学出版社,2006.6
[30]杨恒,李爱国等编著,FPGA/CPLD最新实用技术指南[M],北京:清华大学出版社,2005.9
[31]孙华锦,基于VHDL语言的电子设计自动化及其应用[D],西安:西北工业大学,2001.10
[32]刘乐善,欧阳星明,刘学清编著,微型计算机接口技术及应用[M],武汉:华中科技大学出版社,2005.8
[33][英]M ichael J.Pont著,时间触发嵌入式系统设计模式:使用8051系列微控制器开发可靠应用[M],北京:中国电力出版社,2004.6
[34]武卫华,陈德宏,基于EDA技术的数字频率计芯片化的实现,电测与仪表[J],2004年第4期,P52-55
[35]郑步生,吴渭等编著,Multisim 2001电路设计及仿真入门与应用[M],北京:电子工业出版社,2000.2
[36]王建校,杨建国编著,51系列单片机及C51程序设计[M],北京:科学出版社,2002.4
[37]余成波,冯丽辉,潘盛辉编著,虚拟仪器技术与设计[M],重庆:重庆大学出版社,2006.7
[38]雷振山主编,LabVIEW 7 Express实用技术教程[M],北京:中国铁道出版社,2004.4
[39]雷勇主编,虚拟仪器设计与事件[M],北京:电子工业出版社,2005.3
[40]National Instrument Application Note 110 341398A-01[J],January 1998
[41]赵仕俊,网络仪表概念及相关问题的研究[J],总线与网络,2002年第3期,P37-39
[42]黄智伟,王彦,陈琼等编著,FPGA系统设计与实践[M],北京:电子工业出版社,2005.1
[43]Sefan sjoholm,lennart Lindh,VHDL for designer[M]北京:清华大学出版社,2001