嵌入式可重构计算系统的设计技术研究
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摘要
作为一种全新的计算模式,可重构计算已成为当前的研究热点之一。然而,在系统设计支持方面,随着嵌入式可重构计算系统复杂度的不断增加,越来越需要从系统级进行设计,以提高设计效率;而在运行环境支持方面,由于传统操作系统不能适应新的可重构系统应用需求,如何通过操作系统屏蔽底层平台实现细节,向开发人员提供软/硬件统一的编程模型,并有效管理可重构计算资源以提高利用率,也是可重构计算需要解决的主要问题之一。
     针对上述问题,本文对嵌入式可重构计算系统的设计技术进行了探讨,主要研究内容包括:
     1.结合可重构计算特点,以UML和SystemC为系统级设计语言,提出模型驱动的系统级设计方法。该方法利用UML对系统结构和重构行为进行了描述;设计了面向SystemC的UML Profile扩展;在MDA(模型驱动架构)指导下初步实现了从UML模型到SystemC可执行框架代码的转换,保持了模型和实现的连贯性,有利于嵌入式可重构计算系统的快速开发和验证。
     2.从软、硬件任务不同的语义和实现方式出发,设计了一种基于统一多任务模型的可重构操作系统框架。以逐层抽象的方式,使操作系统具备硬件任务和可重构计算资源管理能力;通过硬件桩任务实现任务间通信与同步,简化了硬件任务的设计实现,并完全兼容现有的软件任务间通信机制。该设计使操作系统能够有效管理硬件任务及可重构计算资源,为可重构计算平台提供良好的运行环境支持。
     3.面向数据流驱动应用,提出了与Pthread兼容的软/硬件统一多线程编程模型SHUMDR。通过硬件线程接口设计、操作系统内核扩展,实现了支持动态可重构的操作系统原型,并提供了一个轻量级的统一线程库。实验测试结果表明,SHUMDR的管理开销和空间资源占用率较小,通过配置位流缓冲和配置Cache可明显改善硬件线程创建时间较长的状况,线程间通信与同步机制简单有效。该模型在探索编程灵活性的同时兼顾了硬件线程的实现效率,能够较好地支持可重构应用的开发。
     4.针对可重构计算平台上的负载可分应用,结合SHUMDR对其性能进行分析与预测。根据底层平台结构和应用的特点,采用不同的负载分配方式,重点讨论包含多个可重构处理单元(Reconfigurable Processing Unit,RPU)计算平台上的负载调度问题。分析结果表明:当通信与配置不完全重叠时,存在最大可用RPU数和优化的RPU数,可得出优化的调度方案及应用处理时间。
As a novel computing paradigm, reconfigurable computing has become a hotspotof current computer architecture research. However, in respect of the design-timesupport, it is needed to start the embedded reconfigurable system design fromsystem-level to cope with the increasing design complexity. While in respect of therun-time support, as traditional operating system can not meet the requirements ofnewly emerging reconfigurable computing systems, one of the key problems to besolved is how to make the operating system manage the reconfigurable computingresources, and provide a unified software/hardware programming model forapplication developers.
     This paper focuses on the problems mentioned above and explores the designtechnology of embedded reconfigurable computing system. It mainly consists of thefollowing four parts of contribution:
     Firstly, with considering the features of reconfigurable computing, this papercombines the capability of UML with SystemC and presents a model driven designmethodology at system-level. It makes use of UML to describe the embeddedreconfigurable system from the system structure and reconfiguration behavior aspect.Within the scope of Model Driven Architecture, A UML Profile for SystemC is givento implement the transformation from UML model to SystemC executable codeskeleton. The design methodology could derive implementation from specificationdirectly while contribute to rapid system prototyping and initial function verification.
     Secondly, based on the essential differences between software-tasks andhardware-tasks, this paper presents an operating system framework for reconfigurablecomputing using unified multi-task model. The operating system could managehardware tasks and reconfigurable computing resources through hierarchicalabstraction. A hardware stub task is combined to each hardware task to deal withinter-task communications. This simplifies hardware task design, and makes theoperating system compatible with current software programming models andinter-task communication mechanisms. This operating system framework couldmanage the hardware tasks and reconfigurable computing resources effectively, andprovide a run time support for reconfigurable computing platforms.
     Thirdly, for data stream driven applications, this paper proposes a Pthreadcompatible Unified Software/Hardware multi-thread programming Model supporting Dynamic Reconfiguration(SHUMDR). Through hardware thread interface design andoperating system kernel extension, we implement an operating system prototype andprovide a light weight unified thread programming library. The experimental resultsindicate that both the overhead time and resource utilization of SHUMDR are at lowlevel, the time for hardware thread creation is largely decreased through configurationbitstream buffer and configuration cache, the inter-thread communication mechanismis simple and effective. SHUMDR could exploit programmable flexibility whileeffectively maintain hardware tasks' performance, and give support for thedevelopment of reconfigurable applications.
     Finally, for Divisible Load Application(DLA) design on reconfigurablecomputing platforms, this paper gives a performance analysis and forecast throughSHUMDR. Using different way of load allocation according to the characteristics ofthe platform and the DLA, The problem of divisible load scheduling is mainlydiscussed for a reconfigurable computing platform including multiple ReconfigurableProcessing Units(RPUs). It is proved that there exist maximum RPU number andoptimal RPU number when configuration does not completely overlap withcommunication. An optimal solution for the load scheduling and the processing timeis derived for DLA design and implementation.
引文
[1] Compton K. Reconfigurable Computing: A Survey of Systems and Software[J]. ACM Computing Surveys, 2002, 34(2): 171-210.
    [2] Makimoto. The hot decade of field programmable technologies[C]. IEEE International Conference on Field-Programmable Technology, 2002: 3-6.
    [3] Kiran Bondalapati, Viktor K. Prasanna. Reconfigurable Computing Systems[J]. Proceedings of the IEEE. 2002, 90(7): 1201-1217.
    [4] J. Villasenor, W. H. Mangione-Smith. Configurable Computing[J]. Scientific American, 1997, (11): 23-27.
    [5] J. M. Arnold. The Splash 2 software environment[C]. IEEE Workshop on FPGAs for Custom Computing Machines, 1993: 88-93.
    [6] J. M. Arnold, D. A. Buell, D. T. Hoang, D. V. Pryor, N. Shirazi, M. R. Thistle. The Splash 2 processor and applications[C]. IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1993: 482-485.
    [7] Gerald Estrin. Reconfigurable Computer Origins: The UCLA Fixed-Plus-Variable (F+V) Structure Computer[J]. IEEE Annals of the History of Computing, 2002, 24(4): 3-9.
    [8] Dehon A, Wawrzynek J. Reconfigurable Computing: What, Why, and Implications for Design Automation[C]. Proc. 36th ACM/IEEE Conf. on Design Automation, ACM Press, 1999: 610-615.
    [9] Donthi S, Haggard R. L. A survey of dynamically reconfigurable FPGA devices[C]. Proceedings of the 35th Southeastern Symposium on System Theory, 2003:422-426.
    [10] A. DeHon. Reconfigurable architectures for general purpose computing[D]. Cambridge: Massachusetts Inst. of Technol, 1996.
    [11] S. M. Scalera, J. R. Vazquez. The design and implementation of a context switching FPGA[C]. The 6th Annual IEEE Symposium on FPGAs for Custom Computing Machines, 1998: 78-85.
    [12] J. R. Hauser and J. Wawrzynek. Garp: a MIPS processor with a reconfigurable coprocessor[C]. The 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, 1997: 12-21.
    [13] Chameleon Systems [EB/OL]. http://www.chameleonsvstems.com/.
    [14] W.A. Najjar, W. Bohm, B. A. Draper, et al. High-level language abstraction for reconfigurable computing[J]. Computer, 2003, 36(8): 63-69.
    [15] D. Chang, M. Marek-Sadowska. Partitioning sequential circuits on dynamically reconfigurable FPGAs[J]. IEEE Trans. Comput., 1999, 48(6): 565-578.
    [16] SpecC Methodology [EB/OL]. http://www.ics.uci.edu/-specc/index.html.
    [17] P. Alexander, C. Kong. Rosetta: semantic support for model-centered systems-level design[J]. Computer, 2001, 34(11): 64-70.
    [18] System Verilog [EB/OL]. http://www.systemverilog.org.
    [19] The Open SystemC Initiative [EB/OL]. http://www.systeme.org/.
    [20] A. Pelkonen, K. Masselos, M. Cupak. System-level modeling of dynamically reconfigurable hardware with SystemC[C]. Proceedings of the International Symposium on Parallel and Distributed Processing, 2003: 22-26.
    [21] Bernd Steinbach, Dominik Fr(o|¨)hlich and Thomas Beierlein. Hardware/Soft-ware Codesign of Reconfigurable Architectures Using UML[M]. UML for SOC Design, Springer US, 2006:89-117.
    [22] Andrews D, Niehaus D, Jidin R, et al. Programming models for hybrid FPGA-CPU computational components: a missing link[J]. IEEE Micro, 2004, 24(4): 42-53.
    [23] Walder H, Platzner M. Reconfigurable hardware operating systems: from design concepts to realizations[C]. Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Architectures, 2003: 284-287.
    [24] Vuletic M, Pozzi L, Ienne P. Seamless hardware-software integration in reconfigurable computing systems[J]. IEEE Design & Test of Computers, 2005, 22(2): 102-113.
    [25] 周博,王石记,邱卫东,等.SHUM-UCOS:基于统一多任务模型可重构系统的实时操作系统[J].计算机学报,2006,29(2):208-218.
    [26] A. DeHon. DPGA-coupled microprocessors: commodity ICs for the early 21st Century[C]. IEEE Workshop on FPGAs for Custom Computing Machines, 1994: 31-39.
    [27] M. Hariyama, S. Ogata and M. Kameyama. A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates[J]. IEICE Transactions on Electronics, 2006, E89-C(11):1655-1661.
    [28] Fernando Gehm Moraes and Daniel Mesquita. Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs[C]. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'03). 2003: 1122-1123.
    [29] D. V. Pryor, M. R. Thistle and N. Shirazi. Text searching on Splash 2[C]. IEEE Workshop on FPGAs for Custom Computing Machines, 1993:172-177.
    [30] M. Rencher and B. L. Hutchings. Automated target recognition on SPLASH 2[C]. The 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, 1997: 192-200.
    [31] D. T. Hoang. Searching genetic databases on Splash 2[C]. Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, 1993: 185-191.
    [32] E. Waingold, M. Taylor, D. Srikrishna, et al. Baring it all to software: Raw machines[J]. Computer, 1997, 30(9): 86-93.
    [33] M. B. Taylor, J. Kim, J. Miller, et al. The Raw microprocessor: a computational fabric for software circuits and general-purpose programs[J]. IEEE Micro, 2003, 22(2): 25-35.
    [34] E. Waingold, M. Taylor. Baring it all to Software: The Raw Machine[R]. 1997.
    [35] B. S. Goda, J. F. McDonald, S. R. Carlough, et al. SiGe HBT BiCMOS FPGAs for fast reconfigurable computing[C]. IEE Proceedings on Computers and Digital Techniques, 2000, 147(3): 189-194.
    [36] C. A. Moritz, D. Yeung and A. Agarwal. Exploring optimal cost-performance designs for Raw microprocessors[C]. Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, 1998: 12-27.
    [37] C. A. Moritz, Y. Donald and A. Agarwal. SimpleFit: a framework for analyzing design trade-offs in Raw architectures[J]. IEEE Transactions on Parallel and Distributed Systems, 2001, 12(7): 730-742.
    [38] M. B. Taylor, J. Psota, A. Saraf, et al. Evaluation of the Raw microprocessor: an exposed-wire-delay architecture for ILP and streams[C]. Proceedings of 31st Annual International Symposium on Computer Architecture, 2004: 2-13.
    [39] S. C. Goldstein, H. Schmit, M. Budiu, et al. PipeRench: a reconfigurable architecture and compiler[J]. Computer, 2000, 33(4): 70-77.
    [40] S. C. Goldstein, H. Schmit, M. Moe, et al. PipeRench: a coprocessor for streaming multimedia acceleration[C]. Proceedings of the 26th International Symposium on Computer Architecture, 1999: 28-39.
    [41] H. Kagotani and H. Schmit. Asynchronous PipeRench: architecture and performance evaluations[C]. The 11th Annual IEEE Symposium on Field- Programmable Custom Computing Machines, 2003: 121-129.
    [42] H. Schmit, D. Whelihan, A. Tsai, M. Moe, B. Levine and R. Reed Taylor. PipeRench: A virtualized programmable datapath in 0.18 micron technology[C]. Proceedings of the IEEE Custom Integrated Circuits Conference, 2002: 63-66.
    [43] C. Yuan, P. Pillai, H. Schmit and J. P. Shen. PipeRench implementation of the Instruction Path Coprocessor[C]. The 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000: 147-158.
    [44] I. Chameleon Systems. CS2000 Advance Product Specification[EB/OL]. Chameleon Systems, 2000.
    [45] T. J. Callahan, J. R. Hauser, J. Wawrzynek. The Garp architecture and C compiler[J]. Computer, 2000, 33(4): 62-69.
    [46] J. R. Hauser, J. Wawrzynek. Garp: a MIPS processor with a reconfigurable coprocessor[C]. The 5th Annual IEEE Symposium on FPGAs for Custom Computing Machines, 1997: 12-21.
    [47] T.J. Todman, GA. Constantinides, S.J.E. Wilton, et al. Reconfigurable computing: architectures and design methods[C]. IEE Proceedings on Computers and Digital Techniques, 2005,152(2): 193-207.
    [48] Xilinx Inc., Virtex Ⅱ Datasheet [EB/OL]. http://www.xilinx.com/.
    [49] Xilinx Inc. Microblaze Processor Reference Guide[M], Xilinx Documentation, May 2005.
    [50] Elena Perez-Ramo, Javier Resano, Daniel Mozos. Reducing the reconfiguration overhead: a survey of techniques[C]. The 2007 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'07), 2007: 191-194.
    [51] R. Hartenstein. A decade of reconfigurable computing: A visionary retrospective[C]. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'01), 2001: 642-649.
    [52] S. Hauck, Li Zhiyuan, E. Schwabe. Configuration compression for the Xilinx XC6200 FPGA[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999, 18(8): 1107-1113.
    [53] Z. Li, S. Hauck. Configuration Compression for Virtex FPGAs[C]. The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01), 2001: 147-159.
    [54] I. Kennedy. Exploiting Redundancy to Speedup Reconfiguration of an FPGA[C]. Field-Programmable Logic and Applications (FPL'03), 2003: 262-271.
    [55] Pan Ju Hwa, T. Mitra, Wong Weng-Fai. Configuration bitstream compression for dynamically reconfigurable FPGAs[C]. IEEE/ACM International Conference on Computer Aided Design (ICCAD'04), 2004: 766-773.
    [56] Andreas Dandalis and Viktor K. Prasanna. Configuration Compression for FPGA-Based Embedded Systems[J]. IEEE Transactions on Very Large Scale Integration Systems, 2005, 13(12): 1394-1398.
    [57] F. Mehdipour, M. Zamani, H. Ahmadifar et al. Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework[C]. 20th Int. Symp. Parallel and Distributed Processing, 2006: 1-8.
    [58] R. Maestre, F. J. Kurdahi and N. Bagherzadeh, et al. Kernel Scheduling in Reconfigurable Computing[C]. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'99), 1999: 90-95.
    [59] K. M. Gajjala Puma and D. Bhatia. Temporal partitioning and scheduling data flow graphs for reconfigurable computers[J]. IEEE Transactions on Computers, 1999, 48(6): 579-590.
    [60] Y. Qu, J. Soininen, J. Nurmi. A Parallel Configuration Model for Reducing the Run-Time Reconfiguration Overhead[C]. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'06), 2006: 965-969.
    [61] M. Sanchez-Elez, H. Du, N. Tabrizi, Y. Long, N, et al. Algorithm Optimizations and Mapping Scheme for Interactive Ray Tracing on a Reconfigurable Architecture[J]. Computer & Graphics, 2003, 27(1): 701-713.
    [62] 梁樑,周学功,王颖,彭澄廉.采用预配置策略的可重构混合任务调度算法[J].计算机辅助设计与图形学学报,2007,19(5):635-641.
    [63] Z. Li, S. Hauck. Configuration prefetching techniques for partial reconfigurable coprocessor with relocation and defragmentation[C]. IEEE ACM International Symposium on Field-Programmable Gate Arrays, 2002: 187-195.
    [64] Z. Li, K. Compton, S. Hauck, et al. Configuration Cache Management Techniques for FPGAs[C]. The 8th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'00), 2000: 22-36.
    [65] J. Resano, D. Mozos, D Verkest and F Catthoor. A Reconfiguration Manager for Dynamically Reconfigurable Hardware[J]. IEEE Design & Test, 2005, 22(5): 452-460.
    [66] S. Trimberger, D. Carberry, A. Johnson and J Wong. A time multiplexed FPGA[C]. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'97), 1997: 22-29.
    [67] D. I. Lehn, K. Puttegowda, J. H. Park, et al. Evaluation of Rapid Context Switching on a CSRC Device[C]. International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'02), 2002: 209-215.
    [68] 曾繁泰等.EDA工程方法学[M].北京:清华大学出版社,2003.
    [69] W. Mueller, A. Rosti, S. Bocchio, et al. UML for ESL Design-Basic Principles, Tools, and Applications[C]. IEEE/ACM International Conference on Computer-Aided Design (ICCAD'06), 2006: 73-80.
    [70] Jishnu Mukerji, Joaquin Miller. MDA Guide (Version 1.0.1) [EB/OL]. http://www.omg.org/docs/omg/03-06-01.pdf.
    [71] Object Management Group. Meta Object Facility Specification (Version 1.4) [M]. OMG document formal/02-04-03, 2002.
    [72] Object Management Group. XML Metadata Interchange Specification (Version 2.0)[M]. OMG document formal/05-05-01, 2005.
    [73] Object Management Group. Object Constraint Language Specification (Version 2.0)[M]. OMG document formal/06-05-01, 2006.
    [74] Object Management Group. Unified Modeling Language: Infrastructure (Version 2.0)[M]. OMG document formal/05-07-05, 2005.
    [75] Q. Zhu, A. Matsuda and M. Shoji. An Object-Oriented Design Process for System-on-Chip using UML[C]. The 15th International Symposium on System Synthesis (ISSS'02), 2002: 249-254.
    [76] S. Bocchio E. Riccobene, A. Rosti, P. Scandurra, A SoC Design Flow Based on UML 2.0 and SystemC [EB/OL]. http://jerry.c-lab.de/uml-soc/.
    [77] Object Management Group. UML Profile for System on a Chip (Version 1.0.1) [EB/OL]. http://www.omg.org/docs/formal/06-08-01.pdf.
    [78] E. Riccobene, P. Scandurra, A. Rosti and S. Bocchio. A SoC design methodology involving a UML 2.0 profile for SystemC[C]. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE'05), 2005: 704-709.
    [79] IBM Inc. IBM Rational Rose Realtime [EB/OL]. http://www-01.ibm.com/software/cn/rational/.
    [80] IBM Inc. Telelogic Rhapsody [EB/OL]. http://www.telelogic.com/.
    [81] K. D. Nguyen, Z. Sun, P.S. Thiagarajan, W. F. Wong. Model driven SoC Design Via Executable UML to SystemC[C]. 25th IEEE International Real-Time Systems Symposium (RTSS'04), 2004: 459-468.
    [82] Object Management Group. Unified Modeling Language: Superstructure (Version 2.0)[M]. OMG document formal/05-07-04, 2005.
    [83] Thorsten Grotker, Stan Liao, Grant Martin and Stuart Swan. System Design with SystemC[M]. Springer US, 2002.
    [84] L. Cai, D. Gajski. Transaction level modeling: an overview[C]. First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'03), 2003: 19-24.
    [85] C. Steiger, H. Walder, M. Platzner. Online Scheduling and Placement of Real-time Tasks to Partially Reconfigurable Devices[C]. Proceedings of the 24th IEEE International Real-Time Systems Symposium (RTSS'03), 2003: 224-235.
    [86] Xilinx Inc. Virtex-4 Configuration Guide [EB/OL], http://www.xilinx.com.
    [87] Xilinx Inc. OPB HWICAP (v1 .00.b)[M], Xilinx Document DS280, 2005.
    [88] W3C Organization. Extensible Stylesheet Language Transformations [EB/OL]. http://www.w3 .org/TR/xslt.
    [89] G R. Wigley. An Operating System for Reconfigurable Computing[D]. Adelaide: The Unversity of South Australia, 2005.
    [90] P. Pande, C. Grecu, M. Jones, A. Ivanov and R. Saleh. Performance Evaluation and Design Trade-offs for Network-on-Chip Interconnect Architectures[J], IEEE Transactions on Computers, 2005, 54(8): 1025-1040.
    [91] Xilinx Inc. PowerPC Processor Reference Guide[M]. Xilinx document UG011, 2007.
    [92] A. S. Zeineddini, K. Gaj. Secure partial reconfiguration of FPGAs[C]. 2005 IEEE International Conference on Field-Programmable Technology (FPT'05), 2005: 155-162.
    [93] Chang-Seok Choi, Hanho Lee. An reconfigurable FIR filter design on a partial reconfiguration platform[C]. Proceedings of the 1st IEEE International Conference on Communications and Electronics, 2006: 352-355.
    [94] A. Lagger, A. Upegui, E. Sanchez, I. Gonzalez. Self-Reconfigurable Pervasive Platform for Cryptographic Application[C]. Intemational Conference on Field Programmable Logic and Applications (FPL'06), 2006: 1-4.
    [95] ISO/IEC 9945, POSIX standard[S]. The ISO POSIX Working Group, 2002.
    [96] E. Lubbers, M. Platzner. A portable abstraction layer for hardware threads[C]. International Conference on Field Programmable Logic and Applications (FPL'08), 2008: 17-22.
    [97] 周学海,罗赛,王峰,等.一种数据驱动的可重构计算统一编程模型[J].电子学报,2007,35(11):2123-2128.
    [98] Xilinx Inc. Two Flows for Partial Reconfiguration: Module Based or Difference Based [EB/OL]. http://www.xilinx.com/bvdocs/appnotes/xapp290.pdf.
    [99] Xilinx Inc. Xilkernel 3.0[M]. 2006.
    [100] Xilinx Inc., Early access partial reconfiguration user guide, xilinx User Guide UG208, Version 1.1, March 6, 2006 [EB/OL]. http://www.xilinx.com/.
    [101] J. Sohn, T. G. Robertazzi. Optimal divisible job load sharing for bus networks[J]. IEEE Transactions on Aerospace and Electronic Systems, 1996, 32(1): 34-40.
    [102] S. Bataineh, Hsiung Te-Yu, T. G Robertazzi. Closed form solutions for bus and tree networks of processors load sharing a divisible job[J]. IEEE Transactions on Computers, 1994, 43(10): 1184-1196.
    [103]Maciej Drozdowski, Pawel Wolniewicz. Experiments with Scheduling Divisible Tasks in Clusters of Workstations[C]. Proceedings of the 6th International Euro-Par Conference on Parallel Processing, 2000:311-319.
    [104]K. N. Vikram, V. Vasudevan. Mapping Data-Parallel Tasks onto Partially Reconfigurable Hybrid Processor Architecture[J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006, 14(9): 1010-1023.
    [105]K. N. Vikram, V. Vasudevan. Scheduling Divisible Loads on Partially Reconfigurable Hardware[C]. The 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06), 2006: 289-290.
    [106]C. Claus, F. H. Muller, J. Zeppenfeld, W. Stechele. A new framework to accelerate Virtex-Ⅱ Pro dynamic partial self-reconfiguration[C]. IEEE International Parallel and Distributed Processing Symposium (IPDPS'07), 2007: 1-7.
    [107]T. G. Robertazzi. Ten Reasons to Use Divisible Load Theory[J]. IEEE Computer, 2003, 36(5): 63-68.

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