飞思卡尔i.MX27应用处理器图像处理性能的改进
摘要
本文首先介绍了视频编解码技术近些年来的发展和国际上两大标准机构:国际电信联盟(ITU)和国际标准化组织(ISO)定义的视频编解码标准,特别是本文将涉及到的目前最新的H.264和MPEG4标准。然后,本文简要介绍了飞思卡尔i.MX27应用处理器及其主要的功能模块。在利用开发板,对i.MX27应用处理器v1.0版本进行芯片测试的过程中,我们发现了这款处理器在图像处理性能上的不足,即在播放VGA图像时,并没有达到每秒30帧的设计能力;并且在液晶屏幕上,如果同时使用图形窗口(Graphic Window)和背景(Back Ground)时,屏幕出现了underrun的现象。为了找出根本原因,确定存在硬件设计问题的地方,我们将开发板上的测试过程,在软件设计环境中再现。利用软件工具的测试和分析,我们找到了系统结构中的瓶颈,即在图像编解码通路上,系统存在着两处的具有带宽受限制的模块:图像后处理器(Post Processor)和LCD控制器(LCD Controller)。随后,本文针对这两处系统瓶颈,提出了解决方案:扩展图像后处理器的数据总线,拆分LCDC的图形窗口与背景窗口的数据通道。最后通过再次重复之前的测试方法和测试程序,对提出的解决方案进行测试和验证。测试结果表明,本文所提出的解决方案消除了系统性能上的带宽瓶颈,从而提高了整个图像编解码通路的性能,达到了对图像处理性能每秒30帧的要求。
This paper introduces the background of video encoding, decoding and the standards of International Telecommunication Union (ITU) and International Organization for Standardization (ISO), especially for the H.264 and MPEG4 standards. And then, this paper introduces the Freescale i.MX27 application processor and its functional modules inside. When validating the version 1.0 of i.MX27 silicon on the evaluation board, we found out the VGA video with 30 frames per second can not work well. After simulating and analyzing in the design environments, we found out the bottle necks. The post processor and LCD controller have bandwidth issues. This paper also provides the solutions, expanding the 32-bit data bus of post processor and separating the graphic window and background of LCD controller. Finally, the video performance is improved to 30 frames per second by the solutions,which are tested and proven to work efficiently.
This paper introduces the background of video encoding, decoding and the standards of International Telecommunication Union (ITU) and International Organization for Standardization (ISO), especially for the H.264 and MPEG4 standards. And then, this paper introduces the Freescale i.MX27 application processor and its functional modules inside. When validating the version 1.0 of i.MX27 silicon on the evaluation board, we found out the VGA video with 30 frames per second can not work well. After simulating and analyzing in the design environments, we found out the bottle necks. The post processor and LCD controller have bandwidth issues. This paper also provides the solutions, expanding the 32-bit data bus of post processor and separating the graphic window and background of LCD controller. Finally, the video performance is improved to 30 frames per second by the solutions,which are tested and proven to work efficiently.
引文
【1】 i.MX27 reference manual, Freescale, June 2007
【2】 i.MX27 architecture specification, Freescale, Nov, 2006
【3】 C90LP ARM11 Platform Block Guide, Freescale, July, 2005
【4】 G. Sullivan 与 T. Wiegand,“视频压缩 —— 从概念到 H.264/AVC 标准”,《IEEE 学报》93 卷第 1 期,2005 年 1 月。
【5】 ISO/IEC 14496-10:2003,《信息技术 —— 音频/视频对象的编码 —— 第 10 部分:高级视频编码》。
【6】 ITU-T 与 ISO/IEC 联合视频小组:《H.264/AVC 保真度范围扩展修订草案》,Doc. JVT-L047,2004 年 9 月。
【7】 Y. Wang, S.-F. Chang, “Motion Estimation and Mode Decision for Low-Complexity H.264 Decoder”, Columbia University ADVENT Technical Report #211-2005-5, 2005
【8】 T. Wiegand, G.J. Sullivan, G. Bjontegaard, A.Luthra, “Overview ofthe H.264/AVC Video Coding Standard,“ IEEE Trans. Circuits Syst. Video Technol., vol13, pp.560-576
【9】 Panama User manual V2.38, Freescale, Feb 2006.
【10】 Functional Specification for System C 2.0, Version 2.0-P. Oct. 2001.
【11】 W.Rernaklus, On-chip bus structure for custom core logic designs, Proc. of the Wescou, Anaheim, California, 1998
【12】 D. Wingard, A. Kurosawa, Integration architecture for system on-a-chip design, Proc, of the IEEE Custom Integrated Circuits Conference, Santa Clara, California, 1998
【13】 Martin G. Design methodologies for system level IP[C]. In: Design,Automation and Test in Europe,1998,Proceedings,1998 Page(s):286～289
【14】 Lahiri K,Raghunathan A,Dey S. Fast performance analysis of bus-based system-on-chip communication architectures[C]. In Computer-Aided Design,1999. Digest of Technical Papers. 1999 IEEE/ ACM International Conference on,1999 Page(s):566～572
【15】 Sassatelli G,Cambon G,Galy J,Torres L. dynamically reconfigurable architecture for embedded systems. In:Rapid System Prototyping[C],12th International Workshop on,2001. ,2001,Page(s):32～37
【16】Chauhan P,Clarke E.M,Lu Y,Wang D. Verifying IP-core based system-on-chip designs[C]. In:ASIC/ SOC conference,1999. Proceedings. Twelfth Annual IEEE International,1999,Page(s):27～31
【17】ARM9JF-S? and ARM9J-S? Technical Reference Manual, Revision: r0p2, ARM Limited. 2003.
【18】AMBA? Specification, Rev 2.0, ARM Limited, 1999.
【19】AMBA? AXI Protocol Specification, v1.0, ARM Limited, 2004.
【20】Stephen H. Hall, High-Speed Digital System Design - A Handbook of Interconnect Theory and Design Practices, John Wiley & Sons, Inc. 2000.
【2】 i.MX27 architecture specification, Freescale, Nov, 2006
【3】 C90LP ARM11 Platform Block Guide, Freescale, July, 2005
【4】 G. Sullivan 与 T. Wiegand,“视频压缩 —— 从概念到 H.264/AVC 标准”,《IEEE 学报》93 卷第 1 期,2005 年 1 月。
【5】 ISO/IEC 14496-10:2003,《信息技术 —— 音频/视频对象的编码 —— 第 10 部分:高级视频编码》。
【6】 ITU-T 与 ISO/IEC 联合视频小组:《H.264/AVC 保真度范围扩展修订草案》,Doc. JVT-L047,2004 年 9 月。
【7】 Y. Wang, S.-F. Chang, “Motion Estimation and Mode Decision for Low-Complexity H.264 Decoder”, Columbia University ADVENT Technical Report #211-2005-5, 2005
【8】 T. Wiegand, G.J. Sullivan, G. Bjontegaard, A.Luthra, “Overview ofthe H.264/AVC Video Coding Standard,“ IEEE Trans. Circuits Syst. Video Technol., vol13, pp.560-576
【9】 Panama User manual V2.38, Freescale, Feb 2006.
【10】 Functional Specification for System C 2.0, Version 2.0-P. Oct. 2001.
【11】 W.Rernaklus, On-chip bus structure for custom core logic designs, Proc. of the Wescou, Anaheim, California, 1998
【12】 D. Wingard, A. Kurosawa, Integration architecture for system on-a-chip design, Proc, of the IEEE Custom Integrated Circuits Conference, Santa Clara, California, 1998
【13】 Martin G. Design methodologies for system level IP[C]. In: Design,Automation and Test in Europe,1998,Proceedings,1998 Page(s):286～289
【14】 Lahiri K,Raghunathan A,Dey S. Fast performance analysis of bus-based system-on-chip communication architectures[C]. In Computer-Aided Design,1999. Digest of Technical Papers. 1999 IEEE/ ACM International Conference on,1999 Page(s):566～572
【15】 Sassatelli G,Cambon G,Galy J,Torres L. dynamically reconfigurable architecture for embedded systems. In:Rapid System Prototyping[C],12th International Workshop on,2001. ,2001,Page(s):32～37
【16】Chauhan P,Clarke E.M,Lu Y,Wang D. Verifying IP-core based system-on-chip designs[C]. In:ASIC/ SOC conference,1999. Proceedings. Twelfth Annual IEEE International,1999,Page(s):27～31
【17】ARM9JF-S? and ARM9J-S? Technical Reference Manual, Revision: r0p2, ARM Limited. 2003.
【18】AMBA? Specification, Rev 2.0, ARM Limited, 1999.
【19】AMBA? AXI Protocol Specification, v1.0, ARM Limited, 2004.
【20】Stephen H. Hall, High-Speed Digital System Design - A Handbook of Interconnect Theory and Design Practices, John Wiley & Sons, Inc. 2000.