雷电定位系统中基于CPLD的数据处理与功能实现
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摘要
雷电信号监测定位技术作为雷电防护技术的重要组成部分,以探测、确定落雷点位置为基本任务,在雷电防护、雷电预警和预报方面有重要的应用价值,是服务于全社会、急需发展的一项新技术。
     本文依托于雷电监测定位系统,探讨了雷电定位系统中基于CPLD的功能设计与实现。结合具体的科研课题,设计和实现了基于TOA(Time of Arrival)到达时间法的高精度雷电信号定位系统中的CPLD相关功能部分。
     本文在数据采集分析等问题上提出了新的方案并在实际系统中实现,对方案进行了验证,并给出了结论。此系统创新性的设计了结合低频和高频雷电信号于一体的采集系统,对两路数据进行分别的数据处理,并使用CPLD进行了实际实现。
     本文还给出了基于GPS芯片和CPLD,对系统压控晶振时钟进行校准的实现方法,有效解决了由于长时间使用,晶振自身特性变化,造成的频率偏移现象。为达到高精度的时间校准,利用GPS信号的高精度和高同步性,由CPLD计算系统时钟相对GPS秒脉冲信号的频率偏移,驱动后续D/A,为压控时钟晶振提供调整电压,以达到调节晶振频率的作用。本文设计的CPLD芯片的算法,采用两级脉冲计数及CPLD硬件延时方法,以达到CPLD资源占用和功能实现的平衡。
Lightning monitor and location technology, which is an important part of lightning proof technology, mainly detect lightning parameters and measure the location of lightning. It is very useful in lightning proof, lightning forecast and lightning early-warning. So it is a new technology that urgent needs to be developed.
     This paper based on lightning monitor system, studies design and realization of lightning location system based on CPLD. Combine to actual scientific research, the design of the high precise lightning location system base on TOA (Time of Arrival) is introduced.
     Following, data processing and transfer are particularly studied. This paper raise a new blue print in data processing and realize it, then give some conclusion from elementary experiment. It provides a novel data collecting system which can process the lighting signal in both low and high frequency band. And the data collection system has been realized based on CPLD.
     This paper introduces the method of clock calibration to VCXO in system,based on GPS and CPLD. It can solve the problem of frequency offset because of Crystal worse behavior in Long-term use.
     In order to achieve high-precision clock calibration, to use of high-precision synchronization of GPS signals, CPLD computing system clock frequency offset relative GPS signal, send to ARM to drive D/A. This process provides adjust voltage for the voltage-controlled crystal oscillator to achieve regulate the crystal frequency. The algorithm of CPLD chip designed in this paper, using two pulse-counting and CPLD hardware delay means to achieve the balance between CPLD resource consumption and function.
引文
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