1000BASE-T千兆以太网收发器数字信号处理算法研究与VLSI设计
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摘要
IEEE802.3ab 1000BASE-T gigabit Ethernet(GbE)是IEEE802.3u fast Ethernet之后的新一代基于双绞线信道的高速以太网标准。1000BASE-T的主要目标是在与100BASE-TX快速以太网相同的5类非屏蔽平衡双绞布线上实现10倍于快速以太网的传输速率,误比特率不超过10-10。通过对基于快速以太网的现有应用以及网络管理等等,甚至包括布线系统在内的用户资源全面兼容,1000BASE-T能够从现有快速以太网平滑无缝的升级,同时将升级成本降到最低,并且全面继承以太网的简单廉价高可靠性易于管理的优点。因此1000BASE-T GbE以其高带宽低成本的显著优势,正在日渐成为主流以太网标准。可以预见,1000BASE-T GbE必然具有广阔的应用与市场前景。
与应用上的优势形成对照的,是其在技术上对收发器设计提出的挑战。由于1000BASE-T GbE所使用的传输媒介是为上一代以太网标准设计的,为了在同样的媒介上提供10倍的传输速率,1000BASE-T使用4对双绞线进行全双工传输,并采用多电平调制技术以提高频带利用率。但全双工双向传输带来严重的回波与串扰问题,为消除双向传输之间的干扰,使用混合电路以及回波抵消技术。而为补偿多电平调制技术带来的信噪比损失,又采用远较100BASE-TX更为复杂的编码算法。更高的高吞吐率与更复杂的算法实现给收发器的设计带来很大的困难,物理层的基带信号处理模块,尤其是联合解码均衡器的实现成为一个难点。
如何在实际的双绞线信道中消除信道的非理想特性,并充分利用1000BASE-T的编码算法带来的编码增益是使1000BASE-T收发器达到设计指标的重要问题。一些常用的解码算法已被证明无法充分利用1000BASE-T编码技术所提供的编码增益。而高性能的算法却又有巨大的硬件开销,或者被认为难以达到1000BASE-T的吞吐率要求。同时希望解码算法能够具有尽可能低的硬件复杂度以降低收发器成本,在移动设备上的应用又希望解码器的功耗尽可能的低。我们认为,在这些方面现有的研究尚大有改进的余地。鉴于此,本文对如何在1000BASE-T实际面对的信道环境中进行高性能、低复杂度以及低功耗的解码进行深入的研究,并提出了有效的解决方案。
论文的研究内容,主要包括以下几个方面:
(1)为了解决线对延迟差、线对交换与极性错误所造成的4维符号破坏问题,对1000BASE-T的编码技术进行深入研究。利用其编码特性提出了在可能存在线对顺序与极性错误前提下PCS训练方法,从而为完成解码铺平了道路。
(2)为了确定适用于1000BASE-T应用高吞吐率要求的联合均衡解码算法,对于联合解码均衡算法进行了研究。通过仿真确认各算法在1000BASE-T信道环境下的性能表现。并研究各算法的关键参数对其复杂度与性能的影响,确定适用于1000BASE-T的联合解码均衡算法。提出一种基于预滤波M算法的联合解码均衡技术,在低复杂度下即具有相对于常用的PDFD更高的性能。
(3)为了解决M算法的高关键路径延迟问题,提出超前计算MA4解码器。通过优化的超前计算结构、低扇出解码器结构以及为M算法优化的低复杂度排序网络结构,在保持M算法的低复杂度优势同时将其关键路径延迟缩短至与PDFD相当。并通过符号压缩技术进一步降低M算法解码器的硬件复杂度。通过这些手段,14tap MA4解码器在1Gbps的吞吐率下,依然能够保持其相对于14tap PDFD的性能优势。同时,其硬件复杂度却不及后者的2/3。
(4)为了进一步降低预滤波PDFD的硬件复杂度与功耗,提出一种适合于1000BASE-T的混合结构幸存记忆单元(SMU)结构。并对其在不同的面积/功耗/解码延迟约束下适用的混合结构SMU进行分析。证明其相比于传统的寄存器交换结构SMU,在面积功耗方面的优势。对于1tap预滤波PDFD的应用表明,应用混合结构SMU的1tap PDFD可以降低19%的硬件复杂度与1/2以上的功耗。
(5)为了解决不同设计约束下联合均衡解码技术的选择问题,在现有以及所提出的各种技术基础上,对各种面积/性能条件下适用的预滤波联合解码均衡器进行分析。并提出低复杂度约束/高性能约束情况下适用的联合解码均衡器结构。通过仿真与物理设计,确认其适合于1000BASE-T收发器,相比于现有的联合解码均衡技术,在硬件复杂度/性能方面的综合优势。
(6)为了解决联合解码均衡技术在以太网帧间效率降低的问题,提出了可以适用于各类预滤波联合解码均衡器的双模式联合解码均衡技术。仿真与物理设计表明,在不损失性能并且硬件复杂度增加很小的情况下,将联合解码均衡技术在网络空闲时功耗降低到1/3以下。
IEEE802.3ab 1000BASE-T gigabit Ethernet (GbE), a successor to IEEE802.3u fast Ethernet(FE), is a new generation of high speed Ethernet standard based on twisted-pair channel. The main purpose of 1000BASE-T is to achieve 10 times the transmission rate as that of the fast Ethernet on the same Category-5 unshielded balanced twisted-pair utilized in 100BASE-TX fast Ethernet, while the bit-error rate is not more than 10-10. Through the application and network management available now and the full compatibility of user resources including the cabling system, 1000BASE-T can be upgraded seamlessly from fast Ethernet while the upgrade cost is cut down to minimum and good features such as simple and cheap structure, high reliability and easy management are inherited. 1000BASE-T GbE is gradually becoming the mainstream Ethernet standard due to its notable advantages of high bandwidth and low cost. It can be predicted that 1000BASE-T GbE will have broad application and market prospects.
However, the tremendous technical challenge in the transceiver design is a stark contrast to the great advantages in application. As 1000BASE-T GbE transmission medium is used in the design of the previous generation of Ethernet standards, four pairs of UTP for full-duplex transmissions and multi-level modulation technique for bandwidth efficiency improvement are employed in 1000BASE-T in order to provide 10 times the transmission rate. But full-duplex bi-directional transmissions pose a serious echo and cross-talk problems. Hybrid circuits and echo cancellation technology are used to eliminate the interference between bi-directional transmissions. To make compensation for the SNR loss caused by the multi-level modulation technique, a much more complex coding algorithm is realized compared to the one in 100BASE-TX. Higher throughput and more complex algorithms bring a lot of difficulties to the design of the transceiver. The baseband signal processing module in the physical layer, in particular the joint TCM decoder and equalizer is one of the main difficulties.
To fully meet the specification of the transceiver, the major issues are how to eliminate the non-ideal characteristics in the actual UTP channel and how to take full advantage of the coding gain of the algorithms in 1000BASE-T. A few commonly used decoding algorithms have been proven to be unable to do the job and the tremendous hardware overhead comes together with the high performance algorithm, or has been considered too difficult to achieve the required throughput. In the mean time, the decoding algorithm is expected to be implemented with low hardware complexity to reduce the transceiver cost as well as with low power consumption in the application of mobile equipment. We believe that there is still much room for improvement of the existing research in these areas. In view of this, we present in this paper an in-depth study on the design of high performance, low complexity and low power consumption decoder in the actual 1000BASE-T channel environment, and propose effective solutions.
The following is the main research aspects of the paper:
(1) To deal with the problem of damaged 4D symbols caused by delays, exchange or wrong polarity between twisted-pairs, we deeply studied the coding technology used in 1000BASE-T, exploited the coding characteristics and propose PCS training methods with the premise of possible error polarity or order in twisted-pairs. Thus paving the way for the completion of decoding.
(2) To determine the best joint equalizer and decoding algorithm for 1000BASE-T, we analyzed several joint equalizer and decoding algorithms that meet the demand of 1000BASE-T high-throughput application on the basis of elaborate research. We simulated those algorithms to verify their performance in the 1000BASE-T channel environment. The key parameters are taken into consideration and their impact on complexity and performance is compared. Pre-filtered M-Algorithm is proposed, which reduces greatly the complexity of hardware and performs much better than commonly used PDFD.
(3) To solve the high critical path latency problem of MA decoder, we propose a MA4 decoder with look-ahead technology. Optimal look-ahead structure, low fan-out decoder structure and low complexity sorting network optimized for M-Algorithm are employed to reduce the critical path delay to almost the same as that of PDFD while maintaining the advantages of low complexity. Symbol compression technique further reduces the M-Algorithm decoder hardware complexity. By these means, the 14-tap MA4 decoder still has the performance advantages over 14-tap PDFD under 1 Gbps throughput. Meanwhile, the hardware complexity is two-thirds below compared to that of the latter.
(4) To further reduce the pre-filter PDFD hardware complexity and power consumption, a hybrid structure SMU is proposed and analyzed in different constraints such as area, power and decoding delay. We prove that hybrid structure SMU has more area and power consumption advantages over the traditional register exchange architecture SMU. The application in 1tap pre-filtered PDFD indicates that the utilization of the hybrid structure SMU can reduce 19 percent of hardware complexity and half the power consumption.
(5) To select felicitous joint TCM decoder and equalizer in different design constraints, the pre-filtered joint equalizer and decoder applicable to various sizes and performance conditions is analyzed on the basis of the existing and proposed techniques. The structures adjusted to low or high complexity constraints are proposed. Through simulation and physical design, we make sure they are suitable for 1000BASE-T transceiver and have integrated hardware complexity or performance advantages over existing ones.
(6) To increase efficiency of joint TCM decoder and equalizer when IDLE symbol is transmitting in 1000BASE-T Ethernet, we make use of 1000BASE-T coding properties and propose a dual-mode technique which can be applied to all types of pre-filtered joint equalizer and decoder. Simulation and physical design show that the power consumption is reduced to one-third below when network is idle with no loss of performance and a small increase in the complexity of hardware.
与应用上的优势形成对照的,是其在技术上对收发器设计提出的挑战。由于1000BASE-T GbE所使用的传输媒介是为上一代以太网标准设计的,为了在同样的媒介上提供10倍的传输速率,1000BASE-T使用4对双绞线进行全双工传输,并采用多电平调制技术以提高频带利用率。但全双工双向传输带来严重的回波与串扰问题,为消除双向传输之间的干扰,使用混合电路以及回波抵消技术。而为补偿多电平调制技术带来的信噪比损失,又采用远较100BASE-TX更为复杂的编码算法。更高的高吞吐率与更复杂的算法实现给收发器的设计带来很大的困难,物理层的基带信号处理模块,尤其是联合解码均衡器的实现成为一个难点。
如何在实际的双绞线信道中消除信道的非理想特性,并充分利用1000BASE-T的编码算法带来的编码增益是使1000BASE-T收发器达到设计指标的重要问题。一些常用的解码算法已被证明无法充分利用1000BASE-T编码技术所提供的编码增益。而高性能的算法却又有巨大的硬件开销,或者被认为难以达到1000BASE-T的吞吐率要求。同时希望解码算法能够具有尽可能低的硬件复杂度以降低收发器成本,在移动设备上的应用又希望解码器的功耗尽可能的低。我们认为,在这些方面现有的研究尚大有改进的余地。鉴于此,本文对如何在1000BASE-T实际面对的信道环境中进行高性能、低复杂度以及低功耗的解码进行深入的研究,并提出了有效的解决方案。
论文的研究内容,主要包括以下几个方面:
(1)为了解决线对延迟差、线对交换与极性错误所造成的4维符号破坏问题,对1000BASE-T的编码技术进行深入研究。利用其编码特性提出了在可能存在线对顺序与极性错误前提下PCS训练方法,从而为完成解码铺平了道路。
(2)为了确定适用于1000BASE-T应用高吞吐率要求的联合均衡解码算法,对于联合解码均衡算法进行了研究。通过仿真确认各算法在1000BASE-T信道环境下的性能表现。并研究各算法的关键参数对其复杂度与性能的影响,确定适用于1000BASE-T的联合解码均衡算法。提出一种基于预滤波M算法的联合解码均衡技术,在低复杂度下即具有相对于常用的PDFD更高的性能。
(3)为了解决M算法的高关键路径延迟问题,提出超前计算MA4解码器。通过优化的超前计算结构、低扇出解码器结构以及为M算法优化的低复杂度排序网络结构,在保持M算法的低复杂度优势同时将其关键路径延迟缩短至与PDFD相当。并通过符号压缩技术进一步降低M算法解码器的硬件复杂度。通过这些手段,14tap MA4解码器在1Gbps的吞吐率下,依然能够保持其相对于14tap PDFD的性能优势。同时,其硬件复杂度却不及后者的2/3。
(4)为了进一步降低预滤波PDFD的硬件复杂度与功耗,提出一种适合于1000BASE-T的混合结构幸存记忆单元(SMU)结构。并对其在不同的面积/功耗/解码延迟约束下适用的混合结构SMU进行分析。证明其相比于传统的寄存器交换结构SMU,在面积功耗方面的优势。对于1tap预滤波PDFD的应用表明,应用混合结构SMU的1tap PDFD可以降低19%的硬件复杂度与1/2以上的功耗。
(5)为了解决不同设计约束下联合均衡解码技术的选择问题,在现有以及所提出的各种技术基础上,对各种面积/性能条件下适用的预滤波联合解码均衡器进行分析。并提出低复杂度约束/高性能约束情况下适用的联合解码均衡器结构。通过仿真与物理设计,确认其适合于1000BASE-T收发器,相比于现有的联合解码均衡技术,在硬件复杂度/性能方面的综合优势。
(6)为了解决联合解码均衡技术在以太网帧间效率降低的问题,提出了可以适用于各类预滤波联合解码均衡器的双模式联合解码均衡技术。仿真与物理设计表明,在不损失性能并且硬件复杂度增加很小的情况下,将联合解码均衡技术在网络空闲时功耗降低到1/3以下。
IEEE802.3ab 1000BASE-T gigabit Ethernet (GbE), a successor to IEEE802.3u fast Ethernet(FE), is a new generation of high speed Ethernet standard based on twisted-pair channel. The main purpose of 1000BASE-T is to achieve 10 times the transmission rate as that of the fast Ethernet on the same Category-5 unshielded balanced twisted-pair utilized in 100BASE-TX fast Ethernet, while the bit-error rate is not more than 10-10. Through the application and network management available now and the full compatibility of user resources including the cabling system, 1000BASE-T can be upgraded seamlessly from fast Ethernet while the upgrade cost is cut down to minimum and good features such as simple and cheap structure, high reliability and easy management are inherited. 1000BASE-T GbE is gradually becoming the mainstream Ethernet standard due to its notable advantages of high bandwidth and low cost. It can be predicted that 1000BASE-T GbE will have broad application and market prospects.
However, the tremendous technical challenge in the transceiver design is a stark contrast to the great advantages in application. As 1000BASE-T GbE transmission medium is used in the design of the previous generation of Ethernet standards, four pairs of UTP for full-duplex transmissions and multi-level modulation technique for bandwidth efficiency improvement are employed in 1000BASE-T in order to provide 10 times the transmission rate. But full-duplex bi-directional transmissions pose a serious echo and cross-talk problems. Hybrid circuits and echo cancellation technology are used to eliminate the interference between bi-directional transmissions. To make compensation for the SNR loss caused by the multi-level modulation technique, a much more complex coding algorithm is realized compared to the one in 100BASE-TX. Higher throughput and more complex algorithms bring a lot of difficulties to the design of the transceiver. The baseband signal processing module in the physical layer, in particular the joint TCM decoder and equalizer is one of the main difficulties.
To fully meet the specification of the transceiver, the major issues are how to eliminate the non-ideal characteristics in the actual UTP channel and how to take full advantage of the coding gain of the algorithms in 1000BASE-T. A few commonly used decoding algorithms have been proven to be unable to do the job and the tremendous hardware overhead comes together with the high performance algorithm, or has been considered too difficult to achieve the required throughput. In the mean time, the decoding algorithm is expected to be implemented with low hardware complexity to reduce the transceiver cost as well as with low power consumption in the application of mobile equipment. We believe that there is still much room for improvement of the existing research in these areas. In view of this, we present in this paper an in-depth study on the design of high performance, low complexity and low power consumption decoder in the actual 1000BASE-T channel environment, and propose effective solutions.
The following is the main research aspects of the paper:
(1) To deal with the problem of damaged 4D symbols caused by delays, exchange or wrong polarity between twisted-pairs, we deeply studied the coding technology used in 1000BASE-T, exploited the coding characteristics and propose PCS training methods with the premise of possible error polarity or order in twisted-pairs. Thus paving the way for the completion of decoding.
(2) To determine the best joint equalizer and decoding algorithm for 1000BASE-T, we analyzed several joint equalizer and decoding algorithms that meet the demand of 1000BASE-T high-throughput application on the basis of elaborate research. We simulated those algorithms to verify their performance in the 1000BASE-T channel environment. The key parameters are taken into consideration and their impact on complexity and performance is compared. Pre-filtered M-Algorithm is proposed, which reduces greatly the complexity of hardware and performs much better than commonly used PDFD.
(3) To solve the high critical path latency problem of MA decoder, we propose a MA4 decoder with look-ahead technology. Optimal look-ahead structure, low fan-out decoder structure and low complexity sorting network optimized for M-Algorithm are employed to reduce the critical path delay to almost the same as that of PDFD while maintaining the advantages of low complexity. Symbol compression technique further reduces the M-Algorithm decoder hardware complexity. By these means, the 14-tap MA4 decoder still has the performance advantages over 14-tap PDFD under 1 Gbps throughput. Meanwhile, the hardware complexity is two-thirds below compared to that of the latter.
(4) To further reduce the pre-filter PDFD hardware complexity and power consumption, a hybrid structure SMU is proposed and analyzed in different constraints such as area, power and decoding delay. We prove that hybrid structure SMU has more area and power consumption advantages over the traditional register exchange architecture SMU. The application in 1tap pre-filtered PDFD indicates that the utilization of the hybrid structure SMU can reduce 19 percent of hardware complexity and half the power consumption.
(5) To select felicitous joint TCM decoder and equalizer in different design constraints, the pre-filtered joint equalizer and decoder applicable to various sizes and performance conditions is analyzed on the basis of the existing and proposed techniques. The structures adjusted to low or high complexity constraints are proposed. Through simulation and physical design, we make sure they are suitable for 1000BASE-T transceiver and have integrated hardware complexity or performance advantages over existing ones.
(6) To increase efficiency of joint TCM decoder and equalizer when IDLE symbol is transmitting in 1000BASE-T Ethernet, we make use of 1000BASE-T coding properties and propose a dual-mode technique which can be applied to all types of pre-filtered joint equalizer and decoder. Simulation and physical design show that the power consumption is reduced to one-third below when network is idle with no loss of performance and a small increase in the complexity of hardware.
引文
[1] IEEE standards for local area networks: supplements to carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications. ANSI/IEEE Std 802.3a,b,c, and e-1988, 1987.
[2] IEEE Standards for Local and Metropolitan Area Networks: Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications Media Access Control (MAC) Parameters, Physical Layer, Medium Attachment Units, and Repeater for 100 Mb/s Operation, Type 100BASE-T (Clauses 21-30). IEEE Std 802.3u-1995 (Supplement to ISO/IEC 8802-3: 1993; ANSI/IEEE Std 802.3, 1993 Edition), 1995: p. 0_1-398.
[3] Frazier H., The 802.3z Gigabit Ethernet Standard. Network, IEEE, 1998. 12(3): p. 6-7.
[4] Gray P. and Betz A. Performance evaluation of copper-based Gigabit Ethernet interfaces in Local Computer Networks, 2002. Proceedings. LCN 2002. 27th Annual IEEE Conference on.
[5] Finkler S. and Sidhu D. Performance analysis of IEEE 802.3z Gigabit Ethernet Standard in Global Telecommunications Conference, 1999. GLOBECOM '99.
[6] Daoud R.M., et al. Performance of Fast and Gigabit Ethernet in networked control systems in Circuits and Systems, 2003. MWSCAS '03. Proceedings of the 46th IEEE International Midwest Symposium on.
[7] Loeb M.L., et al., Gigabit Ethernet PCI adapter performance. Network, IEEE, 2001. 15(2): p. 42-47.
[8] Information technology - telecommunications and information exchange between systems - local and metropolitan area networks - specific requirements. Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and physical layer specifications - physical layer parameters and specifications for 1000 Mb/s operation over 4-pair of category 5 balanced copper cabling, type 1000BASE-T. IEEE Std 802.3ab-1999, 1999.
[9] Molle M., Kelkunte M., and Kadambi J., Frame bursting: a technique for scaling CSMA/CD to gigabit speeds. Network, IEEE, 1997. 11(4): p. 6-15.
[10] Molle M., Kalkunte M., and Kadambi J. Scaling CSMA/CD to 1 Gb/s with frame bursting in Local Computer Networks, 1997. Proceedings., 22nd Annual Conference on.
[11] IEEE Standards for Local and Metropolitan Area Networks: Supplements to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications - Specification for 802.3 Full Duplex Operation and Physical Layer Specification for 100 Mb/s Operation on Two Pairs of Category 3 or Better Balanced Twisted Pair Cable (100BASE-T2). IEEE Std 802.3x-1997 and IEEE Std 802.3y-1997 (Supplement to ISO/IEC 8802-3: 1996; ANSI/IEEE Std 802.3, 1996 Edition), 1997: p. 0_1-324.
[12] Hatamian M., et al. Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers in Custom Integrated Circuits Conference, 1998., Proceedings of the IEEE 1998.
[13] Runsheng H., Nazari N., and Sutardja S. A DSP based receiver for 1000BASE-T PHY in Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International.
[14] Roo P., et al. A CMOS transceiver analog front-end for gigabit ethernet over CAT-5 cables in Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International.
[15] Gigabit Ethernet in Circuits and Systems, 2001. Tutorial Guide: ISCAS 2001. The IEEE International Symposium on.
[16] Tan T.C., Gigabit Ethernet and structured cabling. Electronics & Communication Engineering Journal, 2000. 12(4): p. 156-166.
[17] Azadet K. Gigabit Ethernet over unshielded twisted pair cables in VLSI Technology, Systems, and Applications, 1999. International Symposium on.
[18] Frazier H. and Johnson H., Gigabit Ethernet: from 100 to 1,000 Mbps. Internet Computing, IEEE, 1999. 3(1): p. 24-31.
[19] 邹定凯, 千兆以太网 MAC 层芯片设计与测试, in 电子信息与电气工程学院. 2006, 上海交通大学: 上海.
[20] 高继业, 千兆以太网 MAC 层 IC 设计, in 电子信息与电气工程学院. 2006, 上海交通大学: 上海.
[21] 802.3: A tutorial presentation.
[22] Azadet K. and Haratsch E. DSP implementation issues in 1000BASE-T Gigabit Ethernet in VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on.
[23] Intel LXT1000 Gigabit Ethernet Transceiver Datasheet. 2001.
[24] Sher-Li C. and Hassoun M. Implementation, verification and synthesis of the Gigabit Ethernet 1000BASE-T physical coding sublayer in Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on.
[25] 王佳梁, et al., 千兆位以太网物理编码子层编码算法与实现 . 计算机工程, 2005. 31(11): p. 115-116,159.
[26] Forney G.D., Jr. and Eyuboglu M.V., Combined equalization and coding using precoding. Communications Magazine, IEEE, 1991. 29(12): p. 25-34.
[27] Eyuboglu M.V. and Forney G.D., Jr., Trellis precoding: combined coding, precoding and shaping for intersymbol interference channels. Information Theory, IEEE Transactions on, 1992. 38(2): p. 301-314.
[28] Yin H. Timing recovery methods for gigabit Ethernet in VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on.
[29] Tai-Cheng L. and Razavi B., A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. Solid-State Circuits, IEEE Journal of, 2001. 36(3): p. 366-373.
[30] Sung Min P. and Hoi-Jun Y., 1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications. Solid-State Circuits, IEEE Journal of, 2004. 39(1): p. 112-121.
[31] Jingyu H. and Spencer R.R., The design of analog front ends for 1000BASE-T receivers. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], 2003. 50(10): p. 675-684.
[32] Jingyu H. and Spencer R.R. Filter design for 1000BASE-T analog front ends in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on.
[33] Jingyu H. and Spencer R.R. Simulated performance of 1000BASE-T receiver with different analog front end designs in Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on.
[34] Tao B., et al. A gain control baseline circuit of the analog front-end circuit for the 1000base-T Ethernet transceiver in ASIC, 2003. Proceedings. 5th International Conference on.
[35] Baek J.H., et al. Efficient digital baseline wander algorithm and its architecture for fast Ethernet in Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on.
[36] Mehrmanesh S., et al. A compact low power mixed-signal equalizer for gigabit Ethernet applications inCircuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on.
[37] Mahant-Shetti S.S., Hosur S., and Gatherer A. The log-log LMS algorithm in Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on.
[38] Hinrichs H. Attenuation of a Resistive Bridge vs a Hybrid Transformer in MINUTES FOR IEEE802.3ab INTERM MEETING. DALLAS, TX.
[39] Azadet K. and Nicole C.J., Low-power equalizer architectures for high speed modems. Communications Magazine, IEEE, 1998. 36(10): p. 118-126.
[40] Jones D.L., Learning characteristics of transpose-form LMS adaptive filters. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], 1992. 39(10): p. 745-749.
[41] Perry R., Bull D.R., and Nix A., Pipelined DFE architectures using delayed coefficient adaptation. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], 1998. 45(7): p. 868-873.
[42] Widrow B. and Kamenetsky M. On the statistical efficiency of the LMS family of adaptive algorithms in Neural Networks, 2003. Proceedings of the International Joint Conference on.
[43] Franks L., Carrier and Bit Synchronization in Data Communication--A Tutorial Review. Communications, IEEE Transactions on [legacy, pre - 1988], 1980. 28(8): p. 1107-1121.
[44] Mueller K. and Muller M., Timing Recovery in Digital Synchronous Data Receivers. Communications, IEEE Transactions on [legacy, pre - 1988], 1976. 24(5): p. 516-531.
[45] Jennings A. and Clarke B., Data-Sequence Selective Timing Recovery for PAM Systems. Communications, IEEE Transactions on [legacy, pre - 1988], 1985. 33(7): p. 729-731.
[46] Armstrong J., Symbol synchronization using baud-rate sampling and data-sequence-dependent signal processing. Communications, IEEE Transactions on, 1991. 39(1): p. 127-132.
[47] Bergmans J.W.M. and HoWai W.-L., A class of data-aided timing-recovery schemes. Communications, IEEE Transactions on, 1995. 43(234): p. 1819-1827.
[48] Bergmans J.W.M., Efficiency of data-aided timing recovery techniques. Information Theory, IEEE Transactions on, 1995. 41(5): p. 1397-1408.
[49] Haar S., et al. Equalizer-based symbol-rate timing recovery for digital subscriber line systems in Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE.
[50] Larsson P. A 2-1600 MHz 1.2-2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction in Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International.
[51] Spagna F. Phase locked loop using delay compensation techniques in Computers and Communications, 2000. Proceedings. ISCC 2000. Fifth IEEE Symposium on. Antibes-Juan les Pins.
[52] Rao S. Timing Jitter Specifications for 1000BASE-T in IEEE 802.3ab TASK FORCE PLENARY MEETING. Hyatt Regency La Jolla, CA.
[53] 王佳梁, 千兆以太网 1000BASE-T 收发器物理编码子层系统及芯片设计, in 电子信息学院. 2005, 上海交通大学: 上海.
[54] 夏琦, 千兆以太网 1000Base-T 收发器物理层数字电路设计, in 电子信息与电气工程学院. 2006, 上海交通大学: 上海.
[55] Haratsch E.F. High-speed VLSI implementation of reduced complexity sequence estimation algorithms withapplication to Gigabit Ethernet 1000Base-T in VLSI Technology, Systems, and Applications, 1999. International Symposium on.
[56] Karatsch E.F. and Azadet K., A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet. Solid-State Circuits, IEEE Journal of, 2001. 36(3): p. 374-384.
[57] Haratsch E.F. and Azadet K. A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet in Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000.
[58] Hsiu-Ping L., et al. 1000BASE-T Gigabit Ethernet baseband DSP IC design in Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on.
[59] Haratsch E.F. and Azadet K. A pipelined 14-tap parallel decision-feedback decoder for 1000BASE-T Gigabit Ethernet in VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on.
[60] Ungerboeck G., Trellis-coded modulation with redundant signal sets Part I: Introduction. Communications Magazine, IEEE, 1987. 25(2): p. 5-11.
[61] Ungerboeck G., Trellis-coded modulation with redundant signal sets Part II: State of the art. Communications Magazine, IEEE, 1987. 25(2): p. 12-21.
[62] Ungerboeck G., Channel coding with multilevel/phase signals. Information Theory, IEEE Transactions on, 1982. 28(1): p. 55-67.
[63] Proakis J.G., Digital Communications Fourth Edition. 2001.
[64] Forney G.D., Jr., The viterbi algorithm. Proceedings of the IEEE, 1973. 61(3): p. 268-278.
[65] Viterbi A.J., A personal history of the Viterbi algorithm. Signal Processing Magazine, IEEE, 2006. 23(4): p. 120-142.
[66] Hafeez A. and Stark W.E., Decision feedback sequence estimation for unwhitened ISI channels with applications to multiuser detection. Selected Areas in Communications, IEEE Journal on, 1998. 16(9): p. 1785-1795.
[67] Magarini M., Spalvieri A., and Tartara G. Comparison between two methods for delayed decision feedback sequence estimation in Personal, Indoor and Mobile Radio Communications, 2000. PIMRC 2000. The 11th IEEE International Symposium on.
[68] Magarini M., Spalvieri A., and Tartara G. Performance evaluation of the mean-square prefiltered delayed decision feedback sequence detector in Personal, Indoor and Mobile Radio Communications, 2001 12th IEEE International Symposium on.
[69] Won L. and Hill F., A Maximum-Likelihood Sequence Estimator with Decision-Feedback Equalization. Communications, IEEE Transactions on [legacy, pre - 1988], 1977. 25(9): p. 971-979.
[70] Falconer D.D. and Magee F.R., Adaptive channel memory truncation for maximum-likelihood sequence estimation. Bell Syst. Tech. J., 1973. 52: p. 1541–1562.
[71] Siegel P.H. and Wolk J.K., Modulation and coding for information storage. Communications Magazine, IEEE, 1991. 29(12): p. 68-86.
[72] Proakis J.G., Equalization techniques for high-density magnetic recording. Signal Processing Magazine, IEEE, 1998. 15(4): p. 73-82.
[73] Seshadri N. and Anderson J.B., Decoding of severely filtered modulation codes using the (M, L) algorithm. Selected Areas in Communications, IEEE Journal on, 1989. 7(6): p. 1006-1016.
[74] Bergmans J.W.M., Rajput S.A., and Van DeLaar F.A.M., On the Use of Decision Feedback for Simplifying theViterbi Detector. Philips J. Research, 1987. 42(4): p. 399-428.
[75] Duel-Hallen A. and Heegard C., Delayed decision-feedback sequence estimation. Communications, IEEE Transactions on, 1989. 37(5): p. 428-436.
[76] Eyuboglu M.V. and Qureshi S.U.H., Reduced-state sequence estimation for coded modulation of intersymbol interference channels. Selected Areas in Communications, IEEE Journal on, 1989. 7(6): p. 989-995.
[77] Heller J.A., Feedback Decoding of Convolutional Codes, in Advances in Communication Systems, A.J. Viterbi, Editor. 1975, Academic Press, Inc.: New York.
[78] Finamore W.A., Pimentel C.J.L., and Anderson J.B. M-algorithm decoding of convolutional code combined with CPM in Telecommunications Symposium, 1990. ITS '90 Symposium Record., SBT/IEEE International.
[79] Fettweis G. and Meyr H. A 100 Mbit/s Viterbi decoder chip: novel architecture and its realization in Communications, 1990. ICC 90, Including Supercomm Technical Sessions. SUPERCOMM/ICC '90. Conference Record., IEEE International Conference on.
[80] Fettweis G. and Meyr H., High-rate Viterbi processor: a systolic array solution. Selected Areas in Communications, IEEE Journal on, 1990. 8(8): p. 1520-1534.
[81] Black P.J. and Meng T.H., A 140-Mb/s, 32-state, radix-4 Viterbi decoder. Solid-State Circuits, IEEE Journal of, 1992. 27(12): p. 1877-1885.
[82] Yeung A.K. and Rabaey J.M. A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder in Solid-State Circuits Conference, 1995. Digest of Technical Papers. 42nd ISSCC, 1995 IEEE International.
[83] Dawid H., Fettweis G., and Meyr H., A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 1996. 4(1): p. 17-31.
[84] Black P.J. and Meng T.H.Y., A 1-Gb/s, four-state, sliding block Viterbi decoder. Solid-State Circuits, IEEE Journal of, 1997. 32(6): p. 797-805.
[85] 吴新华, et al., 一种新结构的判决反馈时序估计电路. 复旦学报(自然科学版), 2005. 44(6): p. 983-988.
[86] Hiasat A.A. and Abdel-Aty-Zohdy H.S., Combinational logic approach for implementing an improved approximate squaring function. Solid-State Circuits, IEEE Journal of, 1999. 34(2): p. 236-240.
[87] Hekstra A.P., An alternative to metric rescaling in Viterbi decoders. Communications, IEEE Transactions on, 1989. 37(11): p. 1220-1222.
[88] Shung C.B., et al. VLSI architectures for metric normalization in the Viterbi algorithm in Communications, 1990. ICC 90, Including Supercomm Technical Sessions. SUPERCOMM/ICC '90. Conference Record., IEEE International Conference on.
[89] Batcher K.E. Sorting networks and their applications in SJCC: AFIPS press.
[90] Olariu S., Pinotti M.C., and Zheng S.Q., How to sort N items using a sorting network of fixed I/O size. Parallel and Distributed Systems, IEEE Transactions on, 1999. 10(5): p. 487-499.
[91] Zheng S.Q. Algorithms for sorting arbitrary input using a fixed-size parallel sorting device in Parallel Processing, 1996., Proceedings of the 1996 International Conference on.
[92] Young H.C. and Swami A.N. The parameterized Round-Robin partitioned algorithm for parallel external sort in Parallel Processing Symposium, 1995. Proceedings., 9th International.
[93] Yanjun Z. and Zheng S.Q. Design and analysis of a systolic sorting architecture in Parallel and Distributed Processing, 1995. Proceedings. Seventh IEEE Symposium on.
[94] Yanjun Z. and Zheng S.J. A simple and efficient VLSI sorting architecture in Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on.
[95] Shirazi B. and Song Y.D. A parallel exchange sort algorithm in Computers and Communications, 1989. Conference Proceedings., Eighth Annual International Phoenix Conference on.
[96] Preparata F.P., New Parallel-Sorting Schemes. Computers, IEEE Transactions on, 1978. C-27(7): p. 669-673.
[97] Natvig L. Logarithmic time cost optimal parallel sorting is not yet fast in practice in Supercomputing '90. Proceedings of.
[98] McMillin B.M. and Ni L.M., Reliable distributed sorting through the application-oriented fault tolerance paradigm. Parallel and Distributed Systems, IEEE Transactions on, 1992. 3(4): p. 411-420.
[99] Leighton T. and Plaxton C.G. A (fairly) simple circuit that (usually) sorts in Foundations of Computer Science, 1990. Proceedings., 31st Annual Symposium on.
[100] Ju-Wook J. and Kichul K. A fast parallel sorting algorithm on the k-dimensional reconfigurable mesh in Algorithms and Architectures for Parallel Processing, 1997. ICAPP 97. 1997 3rd International Conference on.
[101] Jaja J.F., Kwan Woo R., and Vishkin U. Sorting strings and constructing digital search trees in parallel in Parallel Processing Symposium, 1994. Proceedings., Eighth International.
[102] Dey S. and Srimani P.K. An O(logn) VLSI implementation of a parallel sorting algorithm in Computers and Communications, 1988. Conference Proceedings., Seventh Annual International Phoenix Conference on.
[103] Brent R.P. and Tridgell A. A fast, storage-efficient parallel sorting algorithm in Application-Specific Array Processors, 1993. Proceedings., International Conference on.
[104] Black P.J. and Meng T.H.Y. Hybrid survivor path architectures for Viterbi decoders in Acoustics, Speech, and Signal Processing, 1993. ICASSP-93., 1993 IEEE International Conference on.
[105] Coggins D.J., et al. A Comparison of Path Memory Techniques for VLSI Viterbi Decoders in Conference on Very Large Scale Integration. Munich.
[106] Cypher R. and Shung C.B. Generalized trace back techniques for survivor memory management in the Viterbi algorithm in Global Telecommunications Conference, 1990, and Exhibition. 'Communications: Connecting the Future', GLOBECOM '90., IEEE.
[107] Truong T.K., et al., A VLSI design for a trace-back Viterbi decoder. Communications, IEEE Transactions on, 1992. 40(3): p. 616-624.
[108] Rader C., Memory Management in a Viterbi Decoder. Communications, IEEE Transactions on [legacy, pre - 1988], 1981. 29(9): p. 1399-1401.
[109] Ming-Bo L., New path history management circuits for Viterbi decoders. Communications, IEEE Transactions on, 2000. 48(10): p. 1605-1608.
[110] Boutillon E. and Demassieux N. High speed low power architecture for memory management in a Viterbi decoder in Circuits and Systems, 1996. ISCAS '96., 'Connecting the World'., 1996 IEEE International Symposium on.
[111] Boutillon E. and Gonzalez L. Trace back techniques adapted to the surviving memory management in the M algorithm in Acoustics, Speech, and Signal Processing, 2000. ICASSP '00. Proceedings. 2000 IEEE International Conference on.
[112] IEEE Standard for Information technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications. IEEE Std 802.3an-2006 (Amendment to IEEE Std 802.3-2005), 2006: p. 0_1-167.
[2] IEEE Standards for Local and Metropolitan Area Networks: Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications Media Access Control (MAC) Parameters, Physical Layer, Medium Attachment Units, and Repeater for 100 Mb/s Operation, Type 100BASE-T (Clauses 21-30). IEEE Std 802.3u-1995 (Supplement to ISO/IEC 8802-3: 1993; ANSI/IEEE Std 802.3, 1993 Edition), 1995: p. 0_1-398.
[3] Frazier H., The 802.3z Gigabit Ethernet Standard. Network, IEEE, 1998. 12(3): p. 6-7.
[4] Gray P. and Betz A. Performance evaluation of copper-based Gigabit Ethernet interfaces in Local Computer Networks, 2002. Proceedings. LCN 2002. 27th Annual IEEE Conference on.
[5] Finkler S. and Sidhu D. Performance analysis of IEEE 802.3z Gigabit Ethernet Standard in Global Telecommunications Conference, 1999. GLOBECOM '99.
[6] Daoud R.M., et al. Performance of Fast and Gigabit Ethernet in networked control systems in Circuits and Systems, 2003. MWSCAS '03. Proceedings of the 46th IEEE International Midwest Symposium on.
[7] Loeb M.L., et al., Gigabit Ethernet PCI adapter performance. Network, IEEE, 2001. 15(2): p. 42-47.
[8] Information technology - telecommunications and information exchange between systems - local and metropolitan area networks - specific requirements. Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) access method and physical layer specifications - physical layer parameters and specifications for 1000 Mb/s operation over 4-pair of category 5 balanced copper cabling, type 1000BASE-T. IEEE Std 802.3ab-1999, 1999.
[9] Molle M., Kelkunte M., and Kadambi J., Frame bursting: a technique for scaling CSMA/CD to gigabit speeds. Network, IEEE, 1997. 11(4): p. 6-15.
[10] Molle M., Kalkunte M., and Kadambi J. Scaling CSMA/CD to 1 Gb/s with frame bursting in Local Computer Networks, 1997. Proceedings., 22nd Annual Conference on.
[11] IEEE Standards for Local and Metropolitan Area Networks: Supplements to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications - Specification for 802.3 Full Duplex Operation and Physical Layer Specification for 100 Mb/s Operation on Two Pairs of Category 3 or Better Balanced Twisted Pair Cable (100BASE-T2). IEEE Std 802.3x-1997 and IEEE Std 802.3y-1997 (Supplement to ISO/IEC 8802-3: 1996; ANSI/IEEE Std 802.3, 1996 Edition), 1997: p. 0_1-324.
[12] Hatamian M., et al. Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers in Custom Integrated Circuits Conference, 1998., Proceedings of the IEEE 1998.
[13] Runsheng H., Nazari N., and Sutardja S. A DSP based receiver for 1000BASE-T PHY in Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International.
[14] Roo P., et al. A CMOS transceiver analog front-end for gigabit ethernet over CAT-5 cables in Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International.
[15] Gigabit Ethernet in Circuits and Systems, 2001. Tutorial Guide: ISCAS 2001. The IEEE International Symposium on.
[16] Tan T.C., Gigabit Ethernet and structured cabling. Electronics & Communication Engineering Journal, 2000. 12(4): p. 156-166.
[17] Azadet K. Gigabit Ethernet over unshielded twisted pair cables in VLSI Technology, Systems, and Applications, 1999. International Symposium on.
[18] Frazier H. and Johnson H., Gigabit Ethernet: from 100 to 1,000 Mbps. Internet Computing, IEEE, 1999. 3(1): p. 24-31.
[19] 邹定凯, 千兆以太网 MAC 层芯片设计与测试, in 电子信息与电气工程学院. 2006, 上海交通大学: 上海.
[20] 高继业, 千兆以太网 MAC 层 IC 设计, in 电子信息与电气工程学院. 2006, 上海交通大学: 上海.
[21] 802.3: A tutorial presentation.
[22] Azadet K. and Haratsch E. DSP implementation issues in 1000BASE-T Gigabit Ethernet in VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on.
[23] Intel LXT1000 Gigabit Ethernet Transceiver Datasheet. 2001.
[24] Sher-Li C. and Hassoun M. Implementation, verification and synthesis of the Gigabit Ethernet 1000BASE-T physical coding sublayer in Circuits and Systems, 2001. MWSCAS 2001. Proceedings of the 44th IEEE 2001 Midwest Symposium on.
[25] 王佳梁, et al., 千兆位以太网物理编码子层编码算法与实现 . 计算机工程, 2005. 31(11): p. 115-116,159.
[26] Forney G.D., Jr. and Eyuboglu M.V., Combined equalization and coding using precoding. Communications Magazine, IEEE, 1991. 29(12): p. 25-34.
[27] Eyuboglu M.V. and Forney G.D., Jr., Trellis precoding: combined coding, precoding and shaping for intersymbol interference channels. Information Theory, IEEE Transactions on, 1992. 38(2): p. 301-314.
[28] Yin H. Timing recovery methods for gigabit Ethernet in VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). 2005 IEEE VLSI-TSA International Symposium on.
[29] Tai-Cheng L. and Razavi B., A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. Solid-State Circuits, IEEE Journal of, 2001. 36(3): p. 366-373.
[30] Sung Min P. and Hoi-Jun Y., 1.25-Gb/s regulated cascode CMOS transimpedance amplifier for Gigabit Ethernet applications. Solid-State Circuits, IEEE Journal of, 2004. 39(1): p. 112-121.
[31] Jingyu H. and Spencer R.R., The design of analog front ends for 1000BASE-T receivers. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], 2003. 50(10): p. 675-684.
[32] Jingyu H. and Spencer R.R. Filter design for 1000BASE-T analog front ends in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on.
[33] Jingyu H. and Spencer R.R. Simulated performance of 1000BASE-T receiver with different analog front end designs in Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on.
[34] Tao B., et al. A gain control baseline circuit of the analog front-end circuit for the 1000base-T Ethernet transceiver in ASIC, 2003. Proceedings. 5th International Conference on.
[35] Baek J.H., et al. Efficient digital baseline wander algorithm and its architecture for fast Ethernet in Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on.
[36] Mehrmanesh S., et al. A compact low power mixed-signal equalizer for gigabit Ethernet applications inCircuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on.
[37] Mahant-Shetti S.S., Hosur S., and Gatherer A. The log-log LMS algorithm in Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on.
[38] Hinrichs H. Attenuation of a Resistive Bridge vs a Hybrid Transformer in MINUTES FOR IEEE802.3ab INTERM MEETING. DALLAS, TX.
[39] Azadet K. and Nicole C.J., Low-power equalizer architectures for high speed modems. Communications Magazine, IEEE, 1998. 36(10): p. 118-126.
[40] Jones D.L., Learning characteristics of transpose-form LMS adaptive filters. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], 1992. 39(10): p. 745-749.
[41] Perry R., Bull D.R., and Nix A., Pipelined DFE architectures using delayed coefficient adaptation. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on [see also Circuits and Systems II: Express Briefs, IEEE Transactions on], 1998. 45(7): p. 868-873.
[42] Widrow B. and Kamenetsky M. On the statistical efficiency of the LMS family of adaptive algorithms in Neural Networks, 2003. Proceedings of the International Joint Conference on.
[43] Franks L., Carrier and Bit Synchronization in Data Communication--A Tutorial Review. Communications, IEEE Transactions on [legacy, pre - 1988], 1980. 28(8): p. 1107-1121.
[44] Mueller K. and Muller M., Timing Recovery in Digital Synchronous Data Receivers. Communications, IEEE Transactions on [legacy, pre - 1988], 1976. 24(5): p. 516-531.
[45] Jennings A. and Clarke B., Data-Sequence Selective Timing Recovery for PAM Systems. Communications, IEEE Transactions on [legacy, pre - 1988], 1985. 33(7): p. 729-731.
[46] Armstrong J., Symbol synchronization using baud-rate sampling and data-sequence-dependent signal processing. Communications, IEEE Transactions on, 1991. 39(1): p. 127-132.
[47] Bergmans J.W.M. and HoWai W.-L., A class of data-aided timing-recovery schemes. Communications, IEEE Transactions on, 1995. 43(234): p. 1819-1827.
[48] Bergmans J.W.M., Efficiency of data-aided timing recovery techniques. Information Theory, IEEE Transactions on, 1995. 41(5): p. 1397-1408.
[49] Haar S., et al. Equalizer-based symbol-rate timing recovery for digital subscriber line systems in Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE.
[50] Larsson P. A 2-1600 MHz 1.2-2.5 V CMOS clock-recovery PLL with feedback phase-selection and averaging phase-interpolation for jitter reduction in Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999 IEEE International.
[51] Spagna F. Phase locked loop using delay compensation techniques in Computers and Communications, 2000. Proceedings. ISCC 2000. Fifth IEEE Symposium on. Antibes-Juan les Pins.
[52] Rao S. Timing Jitter Specifications for 1000BASE-T in IEEE 802.3ab TASK FORCE PLENARY MEETING. Hyatt Regency La Jolla, CA.
[53] 王佳梁, 千兆以太网 1000BASE-T 收发器物理编码子层系统及芯片设计, in 电子信息学院. 2005, 上海交通大学: 上海.
[54] 夏琦, 千兆以太网 1000Base-T 收发器物理层数字电路设计, in 电子信息与电气工程学院. 2006, 上海交通大学: 上海.
[55] Haratsch E.F. High-speed VLSI implementation of reduced complexity sequence estimation algorithms withapplication to Gigabit Ethernet 1000Base-T in VLSI Technology, Systems, and Applications, 1999. International Symposium on.
[56] Karatsch E.F. and Azadet K., A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet. Solid-State Circuits, IEEE Journal of, 2001. 36(3): p. 374-384.
[57] Haratsch E.F. and Azadet K. A low complexity joint equalizer and decoder for 1000Base-T Gigabit Ethernet in Custom Integrated Circuits Conference, 2000. CICC. Proceedings of the IEEE 2000.
[58] Hsiu-Ping L., et al. 1000BASE-T Gigabit Ethernet baseband DSP IC design in Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on.
[59] Haratsch E.F. and Azadet K. A pipelined 14-tap parallel decision-feedback decoder for 1000BASE-T Gigabit Ethernet in VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on.
[60] Ungerboeck G., Trellis-coded modulation with redundant signal sets Part I: Introduction. Communications Magazine, IEEE, 1987. 25(2): p. 5-11.
[61] Ungerboeck G., Trellis-coded modulation with redundant signal sets Part II: State of the art. Communications Magazine, IEEE, 1987. 25(2): p. 12-21.
[62] Ungerboeck G., Channel coding with multilevel/phase signals. Information Theory, IEEE Transactions on, 1982. 28(1): p. 55-67.
[63] Proakis J.G., Digital Communications Fourth Edition. 2001.
[64] Forney G.D., Jr., The viterbi algorithm. Proceedings of the IEEE, 1973. 61(3): p. 268-278.
[65] Viterbi A.J., A personal history of the Viterbi algorithm. Signal Processing Magazine, IEEE, 2006. 23(4): p. 120-142.
[66] Hafeez A. and Stark W.E., Decision feedback sequence estimation for unwhitened ISI channels with applications to multiuser detection. Selected Areas in Communications, IEEE Journal on, 1998. 16(9): p. 1785-1795.
[67] Magarini M., Spalvieri A., and Tartara G. Comparison between two methods for delayed decision feedback sequence estimation in Personal, Indoor and Mobile Radio Communications, 2000. PIMRC 2000. The 11th IEEE International Symposium on.
[68] Magarini M., Spalvieri A., and Tartara G. Performance evaluation of the mean-square prefiltered delayed decision feedback sequence detector in Personal, Indoor and Mobile Radio Communications, 2001 12th IEEE International Symposium on.
[69] Won L. and Hill F., A Maximum-Likelihood Sequence Estimator with Decision-Feedback Equalization. Communications, IEEE Transactions on [legacy, pre - 1988], 1977. 25(9): p. 971-979.
[70] Falconer D.D. and Magee F.R., Adaptive channel memory truncation for maximum-likelihood sequence estimation. Bell Syst. Tech. J., 1973. 52: p. 1541–1562.
[71] Siegel P.H. and Wolk J.K., Modulation and coding for information storage. Communications Magazine, IEEE, 1991. 29(12): p. 68-86.
[72] Proakis J.G., Equalization techniques for high-density magnetic recording. Signal Processing Magazine, IEEE, 1998. 15(4): p. 73-82.
[73] Seshadri N. and Anderson J.B., Decoding of severely filtered modulation codes using the (M, L) algorithm. Selected Areas in Communications, IEEE Journal on, 1989. 7(6): p. 1006-1016.
[74] Bergmans J.W.M., Rajput S.A., and Van DeLaar F.A.M., On the Use of Decision Feedback for Simplifying theViterbi Detector. Philips J. Research, 1987. 42(4): p. 399-428.
[75] Duel-Hallen A. and Heegard C., Delayed decision-feedback sequence estimation. Communications, IEEE Transactions on, 1989. 37(5): p. 428-436.
[76] Eyuboglu M.V. and Qureshi S.U.H., Reduced-state sequence estimation for coded modulation of intersymbol interference channels. Selected Areas in Communications, IEEE Journal on, 1989. 7(6): p. 989-995.
[77] Heller J.A., Feedback Decoding of Convolutional Codes, in Advances in Communication Systems, A.J. Viterbi, Editor. 1975, Academic Press, Inc.: New York.
[78] Finamore W.A., Pimentel C.J.L., and Anderson J.B. M-algorithm decoding of convolutional code combined with CPM in Telecommunications Symposium, 1990. ITS '90 Symposium Record., SBT/IEEE International.
[79] Fettweis G. and Meyr H. A 100 Mbit/s Viterbi decoder chip: novel architecture and its realization in Communications, 1990. ICC 90, Including Supercomm Technical Sessions. SUPERCOMM/ICC '90. Conference Record., IEEE International Conference on.
[80] Fettweis G. and Meyr H., High-rate Viterbi processor: a systolic array solution. Selected Areas in Communications, IEEE Journal on, 1990. 8(8): p. 1520-1534.
[81] Black P.J. and Meng T.H., A 140-Mb/s, 32-state, radix-4 Viterbi decoder. Solid-State Circuits, IEEE Journal of, 1992. 27(12): p. 1877-1885.
[82] Yeung A.K. and Rabaey J.M. A 210 Mb/s radix-4 bit-level pipelined Viterbi decoder in Solid-State Circuits Conference, 1995. Digest of Technical Papers. 42nd ISSCC, 1995 IEEE International.
[83] Dawid H., Fettweis G., and Meyr H., A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 1996. 4(1): p. 17-31.
[84] Black P.J. and Meng T.H.Y., A 1-Gb/s, four-state, sliding block Viterbi decoder. Solid-State Circuits, IEEE Journal of, 1997. 32(6): p. 797-805.
[85] 吴新华, et al., 一种新结构的判决反馈时序估计电路. 复旦学报(自然科学版), 2005. 44(6): p. 983-988.
[86] Hiasat A.A. and Abdel-Aty-Zohdy H.S., Combinational logic approach for implementing an improved approximate squaring function. Solid-State Circuits, IEEE Journal of, 1999. 34(2): p. 236-240.
[87] Hekstra A.P., An alternative to metric rescaling in Viterbi decoders. Communications, IEEE Transactions on, 1989. 37(11): p. 1220-1222.
[88] Shung C.B., et al. VLSI architectures for metric normalization in the Viterbi algorithm in Communications, 1990. ICC 90, Including Supercomm Technical Sessions. SUPERCOMM/ICC '90. Conference Record., IEEE International Conference on.
[89] Batcher K.E. Sorting networks and their applications in SJCC: AFIPS press.
[90] Olariu S., Pinotti M.C., and Zheng S.Q., How to sort N items using a sorting network of fixed I/O size. Parallel and Distributed Systems, IEEE Transactions on, 1999. 10(5): p. 487-499.
[91] Zheng S.Q. Algorithms for sorting arbitrary input using a fixed-size parallel sorting device in Parallel Processing, 1996., Proceedings of the 1996 International Conference on.
[92] Young H.C. and Swami A.N. The parameterized Round-Robin partitioned algorithm for parallel external sort in Parallel Processing Symposium, 1995. Proceedings., 9th International.
[93] Yanjun Z. and Zheng S.Q. Design and analysis of a systolic sorting architecture in Parallel and Distributed Processing, 1995. Proceedings. Seventh IEEE Symposium on.
[94] Yanjun Z. and Zheng S.J. A simple and efficient VLSI sorting architecture in Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on.
[95] Shirazi B. and Song Y.D. A parallel exchange sort algorithm in Computers and Communications, 1989. Conference Proceedings., Eighth Annual International Phoenix Conference on.
[96] Preparata F.P., New Parallel-Sorting Schemes. Computers, IEEE Transactions on, 1978. C-27(7): p. 669-673.
[97] Natvig L. Logarithmic time cost optimal parallel sorting is not yet fast in practice in Supercomputing '90. Proceedings of.
[98] McMillin B.M. and Ni L.M., Reliable distributed sorting through the application-oriented fault tolerance paradigm. Parallel and Distributed Systems, IEEE Transactions on, 1992. 3(4): p. 411-420.
[99] Leighton T. and Plaxton C.G. A (fairly) simple circuit that (usually) sorts in Foundations of Computer Science, 1990. Proceedings., 31st Annual Symposium on.
[100] Ju-Wook J. and Kichul K. A fast parallel sorting algorithm on the k-dimensional reconfigurable mesh in Algorithms and Architectures for Parallel Processing, 1997. ICAPP 97. 1997 3rd International Conference on.
[101] Jaja J.F., Kwan Woo R., and Vishkin U. Sorting strings and constructing digital search trees in parallel in Parallel Processing Symposium, 1994. Proceedings., Eighth International.
[102] Dey S. and Srimani P.K. An O(logn) VLSI implementation of a parallel sorting algorithm in Computers and Communications, 1988. Conference Proceedings., Seventh Annual International Phoenix Conference on.
[103] Brent R.P. and Tridgell A. A fast, storage-efficient parallel sorting algorithm in Application-Specific Array Processors, 1993. Proceedings., International Conference on.
[104] Black P.J. and Meng T.H.Y. Hybrid survivor path architectures for Viterbi decoders in Acoustics, Speech, and Signal Processing, 1993. ICASSP-93., 1993 IEEE International Conference on.
[105] Coggins D.J., et al. A Comparison of Path Memory Techniques for VLSI Viterbi Decoders in Conference on Very Large Scale Integration. Munich.
[106] Cypher R. and Shung C.B. Generalized trace back techniques for survivor memory management in the Viterbi algorithm in Global Telecommunications Conference, 1990, and Exhibition. 'Communications: Connecting the Future', GLOBECOM '90., IEEE.
[107] Truong T.K., et al., A VLSI design for a trace-back Viterbi decoder. Communications, IEEE Transactions on, 1992. 40(3): p. 616-624.
[108] Rader C., Memory Management in a Viterbi Decoder. Communications, IEEE Transactions on [legacy, pre - 1988], 1981. 29(9): p. 1399-1401.
[109] Ming-Bo L., New path history management circuits for Viterbi decoders. Communications, IEEE Transactions on, 2000. 48(10): p. 1605-1608.
[110] Boutillon E. and Demassieux N. High speed low power architecture for memory management in a Viterbi decoder in Circuits and Systems, 1996. ISCAS '96., 'Connecting the World'., 1996 IEEE International Symposium on.
[111] Boutillon E. and Gonzalez L. Trace back techniques adapted to the surviving memory management in the M algorithm in Acoustics, Speech, and Signal Processing, 2000. ICASSP '00. Proceedings. 2000 IEEE International Conference on.
[112] IEEE Standard for Information technology-Telecommunications and information exchange between systems-Local and metropolitan area networks-Specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications. IEEE Std 802.3an-2006 (Amendment to IEEE Std 802.3-2005), 2006: p. 0_1-167.