基于DCT域的图像数字盲水印算法设计及硬件实现
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摘要
近年来,半导体技术不断发展,CMOS图像传感器以其集成度高、成本低、功耗低、设计简单等优点,在卫星遥感、视觉监控、工业检测、军事侦察、医疗诊断等许多领域取得了越来越广泛的应用。随着集成电路工艺尺寸的缩小,越来越多的图像处理功能被集成到CMOS图像传感器上,这使得数字水印技术作为图像处理功能的一部分与CMOS图像传感器的结合成为可能。本文提出了一种用于图像和视频版权保护的基于DCT域的数字盲水印算法,并对该算法进行了硬件实现。
     在分析了CMOS图像传感器的发展趋势及数字水印技术的发展历史和现状的基础上,本文阐述了将水印算法硬件实现并与CMOS图像传感器结合的可行性与必要性。本文详细介绍了数字水印技术的基本原理、特征和分类,分析了基于DCT域的水印算法的原理、优势和评价标准,并提出了一种盲水印算法。该算法基于DCT,通过对DCT域中中频系数的修改来嵌入水印,以达到保护图像和视频版权的目的。采用了CMOS图像传感器的固定模式噪声作为水印置乱的密钥,将水印与CMOS图像传感器绑定,具有更高的安全性。经验证,该算法具有较好的不可感知性和鲁棒性,嵌入水印后载体图像质量不会受到很大影响,经过一般攻击后仍能提取出水印信息。
     然后,对FDCT、IDCT和本文提出的水印嵌入算法进行了硬件实现。FDCT和IDCT采用行列分解法,一维变换采用W.H.Chen快速算法,运算量大大减少。采用多级流水结构,能够满足数据实时性处理的要求。将水印嵌入模块嵌入到FDCT电路中,充分利用FDCT电路数据转置输出的时间,减少了数据的延迟时间,使FDCT电路的输出数据即为嵌入水印后的频域系数。对电路进行了功能仿真和逻辑综合,并在由CMOS图像传感器、硬件开发板和上位机软件组成的硬件验证平台上进行了FPGA验证,经调试能够正常工作,输出的含有水印的图像质量良好,并且能够提取出清晰的水印图像。对电路进行了ASIC后端设计,采用Chartered 0.18μm工艺进行流片。
In recent years, as the continueous development of semiconductor technology, CMOS image sensors are used more and more widely in satellite remote sensing, visual surveillance, industrial inspection, military reconnaissance and medical diagnostics etc. because of their high integration, low cost, low power dissipation and simplification of design. With the shrinking size of integrated circuit technology, more and more image processing functions are integrated into CMOS image sensor, which makes it possible that digital watermarking technology combines with CMOS image sensor. In this paper, a watermarking algorithm in DCT domain for copyright protection of images and video is proposed and implemented.
     Based on analyzing development trend of CMOS image sensor and history of digital watermarking technology, this dissertation discusses the feasibility and necessity of combining digital watermarking technology with CMOS image sensor. This paper describes the basic principles of digital watermarking technology and the advantages of watermarking algorithm in DCT domain and proposes a blind watermarking algorithm which embeds watermark by modifying DCT coefficients. Fixed pattern noise of CMOS image sensor is used as key to scramble watermark in order to reach greater security. Verification show that the algorithm has good performance.
     Then FDCT, IDCT and proposed watermarking algorithm are implemented in hardware. Computation is greatly reduced by using the RCM structure and W.H.Chen fast algorithm. Multi-level pipeline structure is used to meet real-time data processing requirements. Watermark embedding module is embedded in FDCT circuit to reduce data latency. The circuit was simulated, logic synthesised, and verified on hardware verification platform. After debugging it can work properly that the watermarked image has a good quality and clear watermark can be extracted. The ASIC backend design is fabricated with Chartered 0.18μm CMOS process.
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