叠层芯片封装可靠性分析与结构参数优化
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摘要
随着电子封装微型化、多功能化的发展,三维封装已成为封装技术的发展方向,叠层CSP封装具有封装密度高、信号延迟短、互连性能好等特性,是实现三维封装的重要技术。目前,国外对叠层芯片封装技术研究比较成熟,已开发出八层芯片的层叠封装,但国内大多是以单个芯片封装为研究对象,对叠层CSP封装可靠性的研究却很少。本文采用ANSYS有限元分析方法模拟三层芯片叠层封装工艺流程,分析封装失效机理,通过有限元法预测焊点热循环寿命,并在此基础上对叠层封装进行优化设计,以提高叠层封装可靠性。因此,本研究内容具有重要的理论意义和实际应用前景。
本文首先根据封装固化工艺设计三个三维实体模型,通过ANSYS有限元软件模拟分析高温过程三步主要固化工艺,结果表明,在三步主要固化工艺中,最大应力都出现在最底层芯片连接处,底层芯片首先出现开裂和分层现象;比较上述三步固化工艺对叠层CSP封装可靠性的影响,发现第二步固化工艺后,芯片所受应力最大,芯片开裂几率最高,分层现象最明显。
基于统一性Anand本构方程,采用非线性有限元方法分析复合SnPb钎料焊点在热循环条件下的应力应变特性,模拟结果显示:高应力和应变区域集中在内侧焊点的角部,这些高应力区域将是裂纹萌生的可能位置。
基于上述复合SnPb钎料焊点的应力应变分布的分析,以能量法进行热循环寿命评估,在热循环条件(-55℃～125℃)下,63Sn37Pb钎料焊点热疲劳寿命为685周左右;焊点钎料量相同时,随比值R/r减小,焊点热循环寿命增加,并且随焊点间隙增大,焊点热循环寿命变大。
本文采用有限元方法分析SCSP器件的设计参数对封装热应力的影响。模拟结果表明:掺入一定量Cu、Bi或In等金属,无铅材料SnAg系列焊点的可靠性达到SnPb钎料的水平,可以代替含铅材料;芯片所受应力与芯片厚度成反比,底层芯片厚度变化是影响封装体可靠性的主要因素;随着芯片层数增大,芯片所受应力相应增大,当芯片层数超过四层后,随着层数的增加,底层芯片上应力趋于恒定值。
With the increasing of multi-function and mini-sized packaging demand, the 3D packaging is becoming a development direction for packaging technology. As stacked chip scale packaging (SCSP) has many good properties, such as higher packaging density, smaller signal delaying and better interconnection, it is one important technique of realizing 3D packaging. At present, the technology of the stacked CSP has become quite mature at abroad, and the 8-dies stacked package has been developed. But in domestic, most of them were mainly concerned about single chip package, and the reliability of the stacked die package was hardly discussed. In this paper, packaging process for a typical stacked three-chip packaging has been simulated to analyse invalidation mechanism by ANSYS finite element analysis (FEA) method. Thermal fatigue character of the solder ball has been studied, and combining FEA results, the stacked package has been optimized. Therefore, it has an important theoretic significance and practical future to study the reliability of stacked die package.
Firstly, this paper has designed three 3-dimension curing finite element models to simulate and analyze three major curing processes undergoing high temperature change. The results show that during the each curing process maximum stress occurs in the joints of die the bottom layer, and this may result in die crack and delamination in the bottom layer. By comparing the influence of the curing process on the reliability of the stacked package, it is found that die stress is largest after cureII, and the die is subjected to the highest risk of crack failure and delamination issue is mostly occurred.
Based on the unified viscoplastic constitutive Anand equation, nonlinear finite element modeling is used to analyze stress-strain response of 63Sn37Pb solder joint under thermal cycle conditions. The simulation shows that high stress-strain focus in the corner of the inter solder, and crack may begin to grow along the high-stress area.
Based on the above stress-strain analysis of the SnPb solder, thermal cycle life was evaluated by the energy. Under the thermal cycle conditions (-40℃～ 125℃), the thermal cycle life of the SnPb solder is about 685 cycles. When solder volumes are same, the thermal cycle life of the SnPb solder increase with the R/r decreasing and solder distance increasing.
In this paper, finite element method is applied to analyse the influence of the SCSP device design parameter on the stress of the package. The simulation results show that the reliability of the free-lead SnAg solder adulterated some metals such as Cu, Bi or In etc, is nearly identical to that of the SnPb solder, so free-lead solder can replace the SnPb solder. The stress on dies is negatively proportional to the thickness of die. The thickness change in the bottom layer die is the main factor of the effect on the package reliability. With die-layer number increasing, stress on the dies increase, but the stress in the bottom layer die approximates to constant while using more than four layers in a stacked structure.
本文首先根据封装固化工艺设计三个三维实体模型,通过ANSYS有限元软件模拟分析高温过程三步主要固化工艺,结果表明,在三步主要固化工艺中,最大应力都出现在最底层芯片连接处,底层芯片首先出现开裂和分层现象;比较上述三步固化工艺对叠层CSP封装可靠性的影响,发现第二步固化工艺后,芯片所受应力最大,芯片开裂几率最高,分层现象最明显。
基于统一性Anand本构方程,采用非线性有限元方法分析复合SnPb钎料焊点在热循环条件下的应力应变特性,模拟结果显示:高应力和应变区域集中在内侧焊点的角部,这些高应力区域将是裂纹萌生的可能位置。
基于上述复合SnPb钎料焊点的应力应变分布的分析,以能量法进行热循环寿命评估,在热循环条件(-55℃～125℃)下,63Sn37Pb钎料焊点热疲劳寿命为685周左右;焊点钎料量相同时,随比值R/r减小,焊点热循环寿命增加,并且随焊点间隙增大,焊点热循环寿命变大。
本文采用有限元方法分析SCSP器件的设计参数对封装热应力的影响。模拟结果表明:掺入一定量Cu、Bi或In等金属,无铅材料SnAg系列焊点的可靠性达到SnPb钎料的水平,可以代替含铅材料;芯片所受应力与芯片厚度成反比,底层芯片厚度变化是影响封装体可靠性的主要因素;随着芯片层数增大,芯片所受应力相应增大,当芯片层数超过四层后,随着层数的增加,底层芯片上应力趋于恒定值。
With the increasing of multi-function and mini-sized packaging demand, the 3D packaging is becoming a development direction for packaging technology. As stacked chip scale packaging (SCSP) has many good properties, such as higher packaging density, smaller signal delaying and better interconnection, it is one important technique of realizing 3D packaging. At present, the technology of the stacked CSP has become quite mature at abroad, and the 8-dies stacked package has been developed. But in domestic, most of them were mainly concerned about single chip package, and the reliability of the stacked die package was hardly discussed. In this paper, packaging process for a typical stacked three-chip packaging has been simulated to analyse invalidation mechanism by ANSYS finite element analysis (FEA) method. Thermal fatigue character of the solder ball has been studied, and combining FEA results, the stacked package has been optimized. Therefore, it has an important theoretic significance and practical future to study the reliability of stacked die package.
Firstly, this paper has designed three 3-dimension curing finite element models to simulate and analyze three major curing processes undergoing high temperature change. The results show that during the each curing process maximum stress occurs in the joints of die the bottom layer, and this may result in die crack and delamination in the bottom layer. By comparing the influence of the curing process on the reliability of the stacked package, it is found that die stress is largest after cureII, and the die is subjected to the highest risk of crack failure and delamination issue is mostly occurred.
Based on the unified viscoplastic constitutive Anand equation, nonlinear finite element modeling is used to analyze stress-strain response of 63Sn37Pb solder joint under thermal cycle conditions. The simulation shows that high stress-strain focus in the corner of the inter solder, and crack may begin to grow along the high-stress area.
Based on the above stress-strain analysis of the SnPb solder, thermal cycle life was evaluated by the energy. Under the thermal cycle conditions (-40℃～ 125℃), the thermal cycle life of the SnPb solder is about 685 cycles. When solder volumes are same, the thermal cycle life of the SnPb solder increase with the R/r decreasing and solder distance increasing.
In this paper, finite element method is applied to analyse the influence of the SCSP device design parameter on the stress of the package. The simulation results show that the reliability of the free-lead SnAg solder adulterated some metals such as Cu, Bi or In etc, is nearly identical to that of the SnPb solder, so free-lead solder can replace the SnPb solder. The stress on dies is negatively proportional to the thickness of die. The thickness change in the bottom layer die is the main factor of the effect on the package reliability. With die-layer number increasing, stress on the dies increase, but the stress in the bottom layer die approximates to constant while using more than four layers in a stacked structure.
引文
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32 Amagai M. Chip Scale Package (CSP) Solder Joint Reliability and Modeling.Microelectronics Reliability, 2002, (39): 463~477
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2 电子封装技术丛书编委会.集成电路封装试验手册.电子工业出版社,1998:4~16
3 况延香, 朱颂春.微电子封装技术.中国科技大学出版社,2003:2~10
4 田民波.电子封装工程.清华大学出版社,2003:3~15
5 Weiping Li, Chris Scanlan, Akito Yoshida. System-in-Package and 3D Packaging for Mobile Applications. Equipment for Electronic Products Manufacturing, 2004, (114): 0～15
6 于炎康.封装业欲做中国半导体产业之巨人.半导体技术,2004,29(9):8~11
7 李牧.微电子封装技术的发展与展望.电子工艺技术,2001,22(3):15~18
8 况延香,马莒生.迈向新世纪的微电子封装技术,电子工艺技术,2000,21(1):3~10
9 谢劲松,钟家骐,李川.CSP 芯片热应力分析.电子工业专用设备,2005,(123):32~34
10 高尚通,毕克允.现代电子封装技术.半导体情报,1998,35(2):9~13
11 Rao R. Tummala.中国电子学会电子封装专业委员会组织译校.微电子封装手册.电子工业出版社,2001:23~30
12 郭以嵩,俞宏坤.3D 封装技术.集成电路应用,2003, (4):33~38
13 E.Jan Vardaman Presiden.Demand Drivers and Market Trends in Advanced Packaging. 2005 Technology search International Conference, 2005: 3~7
14 Fujitsu. Stacked MCP Structure. Advanced Packaging Services, 2006: 10~12
15 Chong C M, Cheung Y M. Finite Element stress Analysis of thin Die Detachment Process. Proceeding of 5th Int Conf on Electronic Packaging Technology. China: Shanghai, 2003: 44~51
16 Bob Chylak, Ivg Wei Qin. Packaging Challenges and Solutions for Multi-Stack Die Applications. Equipment for Electronic Products Manufacturing, 2004, (110): 35~37
17 Alex Wei. Amkor Advance Technology in 3D Package. CSIA 2004 Packaging Technology & info Exchange Conference, 2004: 8~12
18 赵保经.中国集成电路大全-集成电路封装.国防工业出版社,1996:7
19 史保华,贾新章,张德胜.微电子器件可靠性.西安电子科技大学出版社,1999:5~12
20 J. Suber. Fracture Properties of Molding Compound Materials for IC Plastic Packaging.Microelectronics and Reliability, 1996, 36(3): 46~58
21 Nagaraj B, Mahalingam M. Packaging-to-Board Attach Reliability-Methodology and Case Study on OMPAC Package. Transactions of the ASME, Journal of electronic Package, 1998, (120): 290~295
22 Wu Sx, Chin J, Grigorich T, Wu X. Mui G, Yeh C. Reliability Analysis for Fine Pitch BGA Package. Proceedings of Electronic Components and Technology Conference, 1998: 737~741
23 Tsai.D.Y, Shen.G.S. On-Board Reliability of SOC-BGA Package. SEMICON 2000 Technical Symposium, China, 1999: 2~6
24 王 谦 . 电 子 封 装 中 的 焊 点 及 其 可 靠 性 .Electronic Components & Materials,1999,19(2):24~26
25 Lee Teck Kheng, Teo Yong Chua, Lim Thiam Beng.Reliability Assessment of Transfer Mold CSP. Proceedings of IEEE/CPMP Electronic Packaging Technology Conference,1998:274~278
26 刘常康,周德俭.PBGA 焊点热疲劳寿命的正交试验及回归分析.电子工艺技术,1999 , 20 ( 3 ) :90~93
27 黄春跃,周德检,李春泉.CCGA 焊点热循环加载条件下应力应变有限元分析.桂林电于工业学院学报,2001,21 (3) :22~28
28 Barrett J. Electronic Systems Package Future Reliability Challenges. Microelectronics Reliability, 1998 (38): 1277~1286
29 Cemal Basaran, Rumpa Chandaroy. Using Finite Element Analysis for Simulation of Reliability Tests on Solders Joints in Microelectronic Package. Computer and Structures, 2000: (74)
30 Stone B, Czarnowski J M, Gua jardo J R. High Performance Flip Chip PBGA development. IEEE ECTC, 2001: 997~999
31 Cemal Basaran, Rumpa Chandaroy. Using Finite Element Analysis for Simulation of Reliability Tests on Solder Joints in Microelectronic Package. Computer and Structures, 2000, (74): 459~468
32 Amagai M. Chip Scale Package (CSP) Solder Joint Reliability and Modeling.Microelectronics Reliability, 2002, (39): 463~477
33 Chang-Chun Lee,Hsin-Chih Liu,Ming-Chih Yew,Kuo-Ning Chiang. 3D Structure Design and Reliability Analysis of Wafer Level Package with Bubble-Like Stress Buffer Layer.2004 Inter Society Conference on Thermal Phenomena. 2004: 317~325
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