基于SOPC的汽车制动性能检测系统研究
摘要
目前投入运行的汽车安全性能检测线基本上能够满足制动性能检测的要求,但现有的检测设备和检测手段也存在着不足,如汽车制动性能最重要的考核指标——制动力还存在着采样频率低、处理精度差等问题,同时整个控制系统也不尽完善。因此,设计更加合理、实用的汽车制动性能检测系统已成为一个崭新的课题,对检测手段和检测设备进行创新,意义深远。
文中提出了基于可编程片上系统(SOPC)的汽车制动性能检测系统设计方案,为实现系统功能,选取的可编程逻辑器件(PLD)为现场可编程逻辑门阵列(FPGA)。设计了能模拟汽车道路行驶时制动全过程的制动性能检验台;以FPGA为核心重点设计了制动力采集、转速测量、与上位机的通讯和接口电路以及输出控制电路;基于FPGA的片内逻辑实现重点解决了A/D采集控制器、LCD显示控制器和基于通用异步收发器(UART)的串行通讯配置;为提高数据处理精度设计了基于FPGA硬件的软件滤波措施——复合滤波器并利用曲线拟合理论在上位机对数据作进一步处理。
基于SOPC技术的汽车制动性能检测系统设计方案取得了如下的创新效果:
(1).实现了片上系统,提高了系统集成度和可靠性。以单一FPGA完成整个系统的功能,大大简化了硬件电路设计,利用Nios II 32位软核处理器在FPGA内部对资源进行了配置实现片上编程,大幅提高了制动力的采样频率和精度,这是传统的设计方案无法做到的。
(2).数字滤波采用全硬件来实现,提高了制动力数据的处理精度。利用FPGA内部丰富的逻辑资源加上功能强大的开发环境,在FPGA内部设计了全硬件的数字信号处理器——复合滤波器,有效提高了数据处理精度。
At present, safety test line can basically meet the automobile brake performance test requirements, but there are shortcomings such as the most important indicators of automobile braking performance– braking force, there are still some poor problems in data acquisition and processing include of low sampling frequency and bad precision, and the whole detection control system is imperfect. So, the design of more rational and efficient automobile brake system performance testing has become a new topic. Means of detection and testing equipment to carry out innovative is far-reaching.
In the paper, a kind of automotive braking performance test system has been designed based on a programmable system-on-chip (SOPC), for the realization of system functions, Field-Programmable Gate Array(FPGA)has been chosen as Programmable Logical Device . A kind of braking test Units that can simulate the whole braking process on-road; field-programmable logic device (FPGA) is selected as the core of system, mainly designed braking force sampling, speed measurement, communication and interface circuit with PC, some output control circuit is mentioned.
The logic chip implementation based on FPGA has solved the problems of A/D controller, LCD display controller and serial communications configuration based on Universal Asynchronous Receiver Transmitter (UART). Composite filtering--software filtering measurement in dealing with the braking force based on FPGA hardware has designed, and the theory of curve fitting is used for further processing in PC.
Design of braking performance test system based on SOPC has made such effects:
Firstly, it has implemented SOPC and improved the system integration and reliability. Total control and signal processing can be achieved in single FPGA, Nios II as high-performance 32-bit soft-core microprocessor in FPGA internal configuration of resources, improved the sampling frequency and precision .It is the traditional design could not be achieved.
Secondly, digital filter using all-hardware implementation, greatly improved the data accuracy. Using FPGA logic resources combined with powerful environments it has actualized interior design digital signal processor—composite filter.
文中提出了基于可编程片上系统(SOPC)的汽车制动性能检测系统设计方案,为实现系统功能,选取的可编程逻辑器件(PLD)为现场可编程逻辑门阵列(FPGA)。设计了能模拟汽车道路行驶时制动全过程的制动性能检验台;以FPGA为核心重点设计了制动力采集、转速测量、与上位机的通讯和接口电路以及输出控制电路;基于FPGA的片内逻辑实现重点解决了A/D采集控制器、LCD显示控制器和基于通用异步收发器(UART)的串行通讯配置;为提高数据处理精度设计了基于FPGA硬件的软件滤波措施——复合滤波器并利用曲线拟合理论在上位机对数据作进一步处理。
基于SOPC技术的汽车制动性能检测系统设计方案取得了如下的创新效果:
(1).实现了片上系统,提高了系统集成度和可靠性。以单一FPGA完成整个系统的功能,大大简化了硬件电路设计,利用Nios II 32位软核处理器在FPGA内部对资源进行了配置实现片上编程,大幅提高了制动力的采样频率和精度,这是传统的设计方案无法做到的。
(2).数字滤波采用全硬件来实现,提高了制动力数据的处理精度。利用FPGA内部丰富的逻辑资源加上功能强大的开发环境,在FPGA内部设计了全硬件的数字信号处理器——复合滤波器,有效提高了数据处理精度。
At present, safety test line can basically meet the automobile brake performance test requirements, but there are shortcomings such as the most important indicators of automobile braking performance– braking force, there are still some poor problems in data acquisition and processing include of low sampling frequency and bad precision, and the whole detection control system is imperfect. So, the design of more rational and efficient automobile brake system performance testing has become a new topic. Means of detection and testing equipment to carry out innovative is far-reaching.
In the paper, a kind of automotive braking performance test system has been designed based on a programmable system-on-chip (SOPC), for the realization of system functions, Field-Programmable Gate Array(FPGA)has been chosen as Programmable Logical Device . A kind of braking test Units that can simulate the whole braking process on-road; field-programmable logic device (FPGA) is selected as the core of system, mainly designed braking force sampling, speed measurement, communication and interface circuit with PC, some output control circuit is mentioned.
The logic chip implementation based on FPGA has solved the problems of A/D controller, LCD display controller and serial communications configuration based on Universal Asynchronous Receiver Transmitter (UART). Composite filtering--software filtering measurement in dealing with the braking force based on FPGA hardware has designed, and the theory of curve fitting is used for further processing in PC.
Design of braking performance test system based on SOPC has made such effects:
Firstly, it has implemented SOPC and improved the system integration and reliability. Total control and signal processing can be achieved in single FPGA, Nios II as high-performance 32-bit soft-core microprocessor in FPGA internal configuration of resources, improved the sampling frequency and precision .It is the traditional design could not be achieved.
Secondly, digital filter using all-hardware implementation, greatly improved the data accuracy. Using FPGA logic resources combined with powerful environments it has actualized interior design digital signal processor—composite filter.
引文
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[2] GB17993-2005,《汽车综合性能检测站能力的通用要求》[S]
[3]王聪敏.汽车检测技术现状及发展[J].科技情报开发与经济,2007.17(35)154~155
[4]李业德.基于单片机的汽车制动性能检测仪的设计[J].微计算机信息(嵌入式与SOC),2007.23(7-2)
[5]王昉.汽车制动性能检测方法及其虚拟仪器的研究[J].机电工程,2006.23(6):55~57
[6]王翔,王钦若,谢晨阳.一种汽车制动性能检测仪的研制[J].传感器技术,2004.23(2):42,52,62
[7]贝绍轶,施卫,周荣新.汽车制动性能检测系统的研究与开发[J].仪表技术,2004(6):16~18
[8]陈炳耀.欧洲机动车安全性能检测状况考察[J].汽车运输,2000.5:34~36
[9]张忠波.基于SOPC技术的汽车制动性能检测[D].广东工业大学工学硕士论文,2005
[10]潘松,黄基业.EDA技术实用教程[M].北京:科学出版社,2003
[11] GB7258-2004,《机动车运行安全技术条件》[S]
[12] GB1276-1999,《汽车制动系结构、性能及试验方法》[S]
[13] GB/T13564-2005,《滚筒反力式汽车制动检验台》[S]
[14]余志生.汽车理论[M].北京:机械工业出版社,1995.5
[15]张金柱.汽车制动试验台关键技术研究[D].哈尔滨工程大学工学硕士论文,2004
[16]朱明程.FPGA原理及应用设计[M].北京:电子工业出版社,2001
[17] Xu Ning-yi zhou zu-cheng.Avalon bus and an example of SOPC system Editorial Board of Semicond[C].Science Technology 2003
[18]褚振勇,翁木云.FPGA的设计与应用[M].西安:西安电子科技大学出版社,2002
[19]任爱峰.基于FPGA的嵌入式系统设计[M].陕西:西安电子科技大学出版社,2004
[20]林明权.VHDL数字控制系统设计范例[M].北京:电子工业出版社,2002
[21] Altera. Quartus II User Manual[CP].2003
[22] Altera. Nios II Hardware Development Tutorial[CP].2007
[23]彭澄廉.挑战SOC-基于Nios的SOPC设计与实践[M].北京,清华大学出版社,2004
[24]黄继昌.传感器工作原理及应用实例[M].北京:人民邮电出版社,1998
[25]徐爱钧.智能化测量控制仪表原理与设计[M].北京:北京航空航天大学出版社,2001
[26] ANALOG DEVICE. Loop-Powered 4-20mA Sensor Transmitter AD693 Handbook
[27] ANALOG DEVICE. Low Cost, Miniature Isolation Amplifiers AD202/AD204 Handbook
[28]肖洪涛.汽车安全性能检测系统的研究[D].吉林大学工学硕士论文,2006
[29] ANALOG DEVICE. Simultaneous Sampling Dual 250kSPS 12-Bit ADC AD7862 Handbook
[30]孟志华.利用FPGA实现UART的设计[J].电子工程师,2007,33(4):41,51
[31]黄曙.汽车综合性能自动测控系统研究[D].广东工业大学工学硕士论文,2005
[32]徐安.轿车前后轴制动力平和分布研究[J].汽车工程,2000.22(3):78~80
[33]丁平.汽车制动性能检测系统的设计[J].农业装备与车辆工程,2007(11):21~23
[34]姬忠校,董惠.基于FPGA的智能传感器系统设计[J].计算机测量与控制,2008,16(10):1516~1518
[35] Toshiba. Toshiba Photo Coupler GaAs Ired & Phototransistor TLP521?4
[36]姜伟,王开军,陈汉梅.一种基于FPGA的串行通讯设计[J].工程设计学报,2003,10(2):111~112
[37]刘志群.基于RS-485实现的PC机与单片机多机通信[J].闽江学院学报,2007,28(2):44~46
[38] ANALOG DEVICE.Half-Duplex Coupler Isolated RS-485 Transceiver ADM2483 Handbook[CP].2003
[39] Hall T S, Hamblen J O.System on a Programmable Chip Development Platform in the Classroom [J]. IEEE Transactions on Education, 2004, 47(4): 502-507
[40]江明,张辉,刘向宇.基于FPGA的LCD控制器设计与实现[J].电子元器件应用,2007,9(2):37~38
[41]苏克,杨志义,韩芝俠.基于FPGA的数控LCD控制器的设计与实现[J].科学技术与工程,2007,5(7):38~40
[42] Nios 32– Bit Programmer’s Reference Manual[Z].Altera Cooperation.2003
[43] Nios II嵌入式处理器设计大赛2005年优秀作品精选集[M].陕西:西安电子科技大学出版社,2006
[44] Altera.Nios II Processor Reference Handbook ver6.1 [EB/OL]. (2006-12-01). www.altera.com/literature/hb/Nios2/n2cpu_nii5v1.pdf
[45]叶金华.FPGA嵌入式应用系统开发典型实例[M].北京:中国电力出版社,2005
[46] Sezer,S.Total,C.Xing Yu.A pipelined SOPC architecture for data link layer protocol processing[C].IEEE 2003
[47]范江,吴军辉,徐立鸿.基于Altera Nios的信号高速采集系统[J].计算机测量与控制,2004,12(5):489~491
[48]赵祥模,关可,南春莉.一种新型的汽车制动性能微机检测系统[J].计算机应用研究,2004(8):178-180
[49]沈振乾,孔冰,常海峰.基于Nios II嵌入式软核处理器的LCD控制方法研究[J].天津工业大学学报,2006,25(4):94~96
[50]占荣,康勇.基于Nios嵌入式软核处理器的液晶显示屏控制[J].自动化技术与应用,2005,24(4):52~54
[51]姚胜兴.基于嵌入式系统的彩色液晶显示驱动控制[J].微计算机信息, 2007, 3(1): 57~59
[52]崔坤,张文明,王滨.基于Nios II的UART与PC间的数据通信[J].电子技术,2007.7-8:124~126
[53]刘柳.对汽车制动性能检测误差的探讨[J].计量与测试技术,2007.34(1):37~38
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