基于宏单元异步乘法器的研究与设计
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摘要
异步电路在握手协议中产生各个分控时钟控制信号,以交互式的联系取代了同步电路的全局时钟,使其在速度、功耗、鲁棒性、可重用性等诸多方面较之同步电路具有独特的优势,目前,异步电路设计的研究已经成为国际上的热点。
本文首先研究宏单元的设计流程与库文件的生成方法。由于宏单元能够实现比标准单元复杂的功能,因而可提高设计效率。单元库文件的编写涉及到功耗,时序,电容等各个参数的精确提取。本文以C单元的设计实现为例,在HJTC Logic 0.25μm工艺下,对C单元进行了功能的模拟、仿真、参数提取、数据的整理以及technology library的编译,使之成为该标准单元库的一个宏单元,并能在异步控制电路中得以调用。
采用基于宏单元的异步电路设计方法设计了一款32位异步乘法器。该异步乘法器包括数据部分和控制部分,实现子字并行功能,可同时支持8位、16位以及32位数据运算。在其控制电路部分采用的是冗余四段握手协议(RFLC),这种协议提高了握手协议的效率,但带来的是面积的耗费,最后在基于C单元电路的基础上完成了对该协议的综合。
Asynchronous circuit generated all the control of local clock signals using handshake protocol, replace the global clock signal of its synchronous circuit using interactive link. Compared with the synchronous circuit, the asynchronous circuits have the particular advantages in speed, power, performance, robustness ,reusability and many other aspects. Asynchronous integrated circuit design is becoming the research focus both at home and abroad.
In this paper, it describes and completes the macro cell design flow and library generation methods. As the macro-cell can achieve much more complex than the standard cell features, the method can improve the design efficiency. The technology library involves the power, timing, capacitance extraction accuracy of each parameter and so on. The design and implementation of the C cell, for example, was simulated, parameter extraction, data collation also compiler the technology library in the HJTC Logic 0.25um process which make it one of the standard cell library macro cell. So, it can be convenient used for asynchronous control circuit.
Based on the new asynchronous circuit design method, a 32-bit asynchronous multiplier is designed, which is composed of data part and control part. It can achieve sub-word parallelism, and then, the results can restore the original bit width difference. A redundant four-phase latch control(RFLC) protocol is presented and implemented in the control path. This agreement increases the efficiency of handshake protocol. However, the corresponding cost is the area. It is based on C-element circuit of the agreement to synthesis.
本文首先研究宏单元的设计流程与库文件的生成方法。由于宏单元能够实现比标准单元复杂的功能,因而可提高设计效率。单元库文件的编写涉及到功耗,时序,电容等各个参数的精确提取。本文以C单元的设计实现为例,在HJTC Logic 0.25μm工艺下,对C单元进行了功能的模拟、仿真、参数提取、数据的整理以及technology library的编译,使之成为该标准单元库的一个宏单元,并能在异步控制电路中得以调用。
采用基于宏单元的异步电路设计方法设计了一款32位异步乘法器。该异步乘法器包括数据部分和控制部分,实现子字并行功能,可同时支持8位、16位以及32位数据运算。在其控制电路部分采用的是冗余四段握手协议(RFLC),这种协议提高了握手协议的效率,但带来的是面积的耗费,最后在基于C单元电路的基础上完成了对该协议的综合。
Asynchronous circuit generated all the control of local clock signals using handshake protocol, replace the global clock signal of its synchronous circuit using interactive link. Compared with the synchronous circuit, the asynchronous circuits have the particular advantages in speed, power, performance, robustness ,reusability and many other aspects. Asynchronous integrated circuit design is becoming the research focus both at home and abroad.
In this paper, it describes and completes the macro cell design flow and library generation methods. As the macro-cell can achieve much more complex than the standard cell features, the method can improve the design efficiency. The technology library involves the power, timing, capacitance extraction accuracy of each parameter and so on. The design and implementation of the C cell, for example, was simulated, parameter extraction, data collation also compiler the technology library in the HJTC Logic 0.25um process which make it one of the standard cell library macro cell. So, it can be convenient used for asynchronous control circuit.
Based on the new asynchronous circuit design method, a 32-bit asynchronous multiplier is designed, which is composed of data part and control part. It can achieve sub-word parallelism, and then, the results can restore the original bit width difference. A redundant four-phase latch control(RFLC) protocol is presented and implemented in the control path. This agreement increases the efficiency of handshake protocol. However, the corresponding cost is the area. It is based on C-element circuit of the agreement to synthesis.
引文
[1] David Chinnery, Kurt Keutzer, Closing the Gap Between ASIC and Custom: Tools and Techniques for High Performance ASIC Design [C], Kluwer Academic Publisher, 2002
[2] Jens Sparso and Steven Furber, Principles of Asynchronous Circuit Design -A Systems Perspective. Kluwer Academic Publishers, Boston, Hardbound, ISBNO-7913-7613-7
[3] Scott Hauck, Asynchronous Design Methodologies: An Overview, Proceedings of the IEEE, January, 1995, 83(1),: 69-93
[4] A. J. Martin, M. Nystrom, P. Penzes, C. Wong. Speed and energy performance of an asynchronous MIPS R3000 microprocessor. June 2001, CSTR:2001.012
[5] A. M. Scott, M. E. Schuelein, M. Roncken, J. J. Hwan, J. Bainbridge, J. R. Mawer, D. L. Jackson, A. Bardsley. Asynchronous on-chip communication: explorations on the Intel PXA27x processor peripheral bus. In Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems, 2007: 60-72
[6] C. H. Van Berkel, R. Burgess, J. Kessels, A. Peeters, M. Roncken, and F. Schalij. Asynchronous circuits for low power: a DCC error corrector. IEEE Journal of Design and Test, 1994, 11(2): 22-32
[7] C. D. Nielsen, J. Staunstrup and S. R. Jones. Potential performance advantages of delay-insensitivity. In Proceedings of IFIP workshop on Silicon Architectures for Neural Nets, November, 1990
[8] N. C. Paver, P. Day, C. Farnsworth, D. L. Jackson, W. A. Lien, and J. Liu, A low-power, low-noise configurable self-timed DSP. In Proceedings of IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1998: 32-42
[9] D. A. Huffman. The synthesis of sequential switching circuits. Journal of the Franklin Institute, March/April 1954
[10] C. L. Seitz. Graph representations for logical machines. PhD thesis, MIT, Jan 1971
[11] J. V. Woods, P. Day, S. B. Furber, J. D. Garside, N. C. Paver, S. Temple, AMULET1: An Asynchronous ARM Microprocessor, IEEE Transactions on Computers, April 1997, 46(4): 385-398
[12] S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. woods. A micropipelined ARM. Proceedings of the VⅡBanff Workshop: Asynchronous Hardware Design, August 1993
[13] A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, and T. K. Lee. The Design of an Asynchronous MIPS R3000 Processor. Proceedings of the 17th Conference on Advanced Research in VLSI. Los Alamitos, Calif.: IEEE Computer Society Press, 1997
[14] H. v. Gageldonk et al. An Asynchronous low-power 80c51 Microcontroller, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, Los Alamitors, Calif.: IEEE Computer Society Press, 1999: 96-107
[15] Clinton KellyⅣ, Virantha Ekanyake, Rajit Manohar. SNAP: A sensor Network Asynchronous Processor. Proc. International Symposium on Advanced Research in Asynchronous Circuit and System, Los Alamitos, Calif.: IEEE Computer Society Press, 2003
[16] Virantha Ekanyake, Clinton KellyⅣ, Rajit Manohar. BitSNAP: Dynamic Significance Compression for low-Energy Sensor Network Asynchronous Processor. Proc. International Symposium on Advanced Research in Asynchronous Circuit and System, Los Alamitos, Calif.: IEEE Computer Society Press, 2005
[17] Bisseling H, Eemers H, Kamps M, et al. Designing Delay-Insensitive Circuits[R]. [S. l.]: IVO, Eindhoven University of Technology, 1990
[18] Staunstrup, J. S. Delay-insensitive Multi-ring Structures, the VLSI Journal, 1993,15(3): 313-340
[19] OZDAG R. O, BEEREL PA. High-Speed QDI Asynchronous Pipelines [C]// Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems,2002: 13-22
[20] Muller, D. E, Bartky, W. S. A Theory of Asynchronous Circuits, Proceedings of an International Symposium on the Theory of Switching, 1959: 204-243
[21] Sokolov. D, Bystrov A, Yakovlev A. STG Optimisation in the Direct Mapping of Asynchronous Circuits[C]// DATE’03: Proceedings of the conference on Design, Automation and Test in Europe. Washington, DC, USA: IEEE Computer Society, 2003
[22] D. Sokolov, A. Yakovlev. Clockless circuits and system synthesis. IEEE Proceedings of Computers and Digital Techniques, 2005, 152(3): 298-316
[23] C. A. Petri. Kommunikation mit automaten. PhD Thesis, University of Bonn, 1962
[24] Chu T A. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications: MIT laboratory for Computer Science, 1987
[25]龚锐.异步乘法器关键技术研究与实现.[工学硕士学位论文].保存单位:国防科学技术大学,2005
[26] Stephen B. Furber and Paul Day, Four-Phase Micropipeline Latch Control Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1996, 4(2): 247-253
[27] Synopsys Inc. Library Compiler Reference Manual. USA: Synopsys Inc, 1999
[28] Library User Guide: Volumn1 and Volumn2. USA: Synopsys Inc. 1999,10, 9910
[29] Synopsys Inc. Library Compiler: Modeling Timing and Power [E B/OL]. USA: Synopsys Inc, 2004.06
[30]郭建兴.深亚微米元件特征化趋势与考量,系统晶片,2006
[31]邱怡芳,郭建兴,郑良加.先进门级层次模型评估与研究,系统晶片,2006
[32]黄义定. IC设计中的建库技术研究与实现,电子设计,2005, 11:159-160
[33]高霆,贺祥庆.逻辑参数库中的Power参数的提取,微电子学与计算机,2003年第五期:33-35
[34]彭代珉. 0.18um CMOS军品级标准单元库的设计,[硕士学位论文].保存单位:国防科学技术大学,2007
[35]冯冲. IC设计数据库生成及移植系统,[工学硕士论文].保存单位:东南大学图书馆,2006
[36]卢俊,贾耸,王源,张钢刚.高性能标准单元库设计,航空计算技术,2007,5,37(3): 86-89
[37]高丽江,张晓昱,陈虹,陈弘毅. UMC 0.18um异步电路标准单元库建库技术研究,微电子学,2008,6, 38(3): 350-355
[38] Bhatnagar H. Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler, Physical Compiler & Prime Time [M]. New York: Kluwer Academic Pub, 2001: 75-80
[39]尼尔H. E.维斯特大卫.哈里斯等著.“MOS大规模集成电路设计”[M].机械工业出版社2005,5
[40] R. Brentand, H. Kung A regular layout for parallel adders, IEEE Trans. Computers, 1982,3, C-31(3): 260-264
[41] M.Ercegovac.Digital Systems and Hardware/Firmware Algorithms,Chapter 12. Arithmetic Algorithms and Processors,John Wiley&Sons.1985
[42] G.Bewick.."Fast Multiplication:Algorithms and Implementation". Ph.D.Dissertation E.E.Dept.of Stanford Univ..1994
[43]阮坚.异步控制电路设计与实现关键技术研究,[工学博士学位论文].保存单位:国防科学技术大学,2008
[44]黄丽,罗仲.数字信号处理中的子字并行技术,零八一科技: 43-52。
[45]王蕾.异步嵌入式微处理器设计与分析关键技术研究,[工学博士学位论文].保存单位:国防科学技术大学,2006
[46]李勇.异步数据触发微处理器体系结构关键技术研究与实现,[工学博士学位论文].保存单位:国防科学技术大学,2007
[47]龚锐,王蕾,戴葵,王志英,异步集成电路C标准单元的设计与实现,微电子学与计算机,2005,1
[48] Martin, A. J. Formal program transformations for VLSI circuit synthesis, In Formal Developments of Programs and Proofs, UT Year of Programming Series (1987). Edited by Dijkstra EW, Addison-Wesley(1989), 1989: 59-80
[49] Berkel, K. v. Beware the Isochronic Fork, The VLSI Journal, 1992, 13: 103-128
[50] Tom Burd. Low-Power CMOS Library Design Methodology: Master Thesis. Electrical Engineering and Computer Sciences, University of California at Berkeley, 1995
[51] Virtuoso Layout Migrate User Guide. Version V2005. 12, Cadence Open Book, 2005
[2] Jens Sparso and Steven Furber, Principles of Asynchronous Circuit Design -A Systems Perspective. Kluwer Academic Publishers, Boston, Hardbound, ISBNO-7913-7613-7
[3] Scott Hauck, Asynchronous Design Methodologies: An Overview, Proceedings of the IEEE, January, 1995, 83(1),: 69-93
[4] A. J. Martin, M. Nystrom, P. Penzes, C. Wong. Speed and energy performance of an asynchronous MIPS R3000 microprocessor. June 2001, CSTR:2001.012
[5] A. M. Scott, M. E. Schuelein, M. Roncken, J. J. Hwan, J. Bainbridge, J. R. Mawer, D. L. Jackson, A. Bardsley. Asynchronous on-chip communication: explorations on the Intel PXA27x processor peripheral bus. In Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems, 2007: 60-72
[6] C. H. Van Berkel, R. Burgess, J. Kessels, A. Peeters, M. Roncken, and F. Schalij. Asynchronous circuits for low power: a DCC error corrector. IEEE Journal of Design and Test, 1994, 11(2): 22-32
[7] C. D. Nielsen, J. Staunstrup and S. R. Jones. Potential performance advantages of delay-insensitivity. In Proceedings of IFIP workshop on Silicon Architectures for Neural Nets, November, 1990
[8] N. C. Paver, P. Day, C. Farnsworth, D. L. Jackson, W. A. Lien, and J. Liu, A low-power, low-noise configurable self-timed DSP. In Proceedings of IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1998: 32-42
[9] D. A. Huffman. The synthesis of sequential switching circuits. Journal of the Franklin Institute, March/April 1954
[10] C. L. Seitz. Graph representations for logical machines. PhD thesis, MIT, Jan 1971
[11] J. V. Woods, P. Day, S. B. Furber, J. D. Garside, N. C. Paver, S. Temple, AMULET1: An Asynchronous ARM Microprocessor, IEEE Transactions on Computers, April 1997, 46(4): 385-398
[12] S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. woods. A micropipelined ARM. Proceedings of the VⅡBanff Workshop: Asynchronous Hardware Design, August 1993
[13] A. J. Martin, A. Lines, R. Manohar, M. Nystrom, P. Penzes, R. Southworth, U. Cummings, and T. K. Lee. The Design of an Asynchronous MIPS R3000 Processor. Proceedings of the 17th Conference on Advanced Research in VLSI. Los Alamitos, Calif.: IEEE Computer Society Press, 1997
[14] H. v. Gageldonk et al. An Asynchronous low-power 80c51 Microcontroller, Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, Los Alamitors, Calif.: IEEE Computer Society Press, 1999: 96-107
[15] Clinton KellyⅣ, Virantha Ekanyake, Rajit Manohar. SNAP: A sensor Network Asynchronous Processor. Proc. International Symposium on Advanced Research in Asynchronous Circuit and System, Los Alamitos, Calif.: IEEE Computer Society Press, 2003
[16] Virantha Ekanyake, Clinton KellyⅣ, Rajit Manohar. BitSNAP: Dynamic Significance Compression for low-Energy Sensor Network Asynchronous Processor. Proc. International Symposium on Advanced Research in Asynchronous Circuit and System, Los Alamitos, Calif.: IEEE Computer Society Press, 2005
[17] Bisseling H, Eemers H, Kamps M, et al. Designing Delay-Insensitive Circuits[R]. [S. l.]: IVO, Eindhoven University of Technology, 1990
[18] Staunstrup, J. S. Delay-insensitive Multi-ring Structures, the VLSI Journal, 1993,15(3): 313-340
[19] OZDAG R. O, BEEREL PA. High-Speed QDI Asynchronous Pipelines [C]// Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems,2002: 13-22
[20] Muller, D. E, Bartky, W. S. A Theory of Asynchronous Circuits, Proceedings of an International Symposium on the Theory of Switching, 1959: 204-243
[21] Sokolov. D, Bystrov A, Yakovlev A. STG Optimisation in the Direct Mapping of Asynchronous Circuits[C]// DATE’03: Proceedings of the conference on Design, Automation and Test in Europe. Washington, DC, USA: IEEE Computer Society, 2003
[22] D. Sokolov, A. Yakovlev. Clockless circuits and system synthesis. IEEE Proceedings of Computers and Digital Techniques, 2005, 152(3): 298-316
[23] C. A. Petri. Kommunikation mit automaten. PhD Thesis, University of Bonn, 1962
[24] Chu T A. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications: MIT laboratory for Computer Science, 1987
[25]龚锐.异步乘法器关键技术研究与实现.[工学硕士学位论文].保存单位:国防科学技术大学,2005
[26] Stephen B. Furber and Paul Day, Four-Phase Micropipeline Latch Control Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1996, 4(2): 247-253
[27] Synopsys Inc. Library Compiler Reference Manual. USA: Synopsys Inc, 1999
[28] Library User Guide: Volumn1 and Volumn2. USA: Synopsys Inc. 1999,10, 9910
[29] Synopsys Inc. Library Compiler: Modeling Timing and Power [E B/OL]. USA: Synopsys Inc, 2004.06
[30]郭建兴.深亚微米元件特征化趋势与考量,系统晶片,2006
[31]邱怡芳,郭建兴,郑良加.先进门级层次模型评估与研究,系统晶片,2006
[32]黄义定. IC设计中的建库技术研究与实现,电子设计,2005, 11:159-160
[33]高霆,贺祥庆.逻辑参数库中的Power参数的提取,微电子学与计算机,2003年第五期:33-35
[34]彭代珉. 0.18um CMOS军品级标准单元库的设计,[硕士学位论文].保存单位:国防科学技术大学,2007
[35]冯冲. IC设计数据库生成及移植系统,[工学硕士论文].保存单位:东南大学图书馆,2006
[36]卢俊,贾耸,王源,张钢刚.高性能标准单元库设计,航空计算技术,2007,5,37(3): 86-89
[37]高丽江,张晓昱,陈虹,陈弘毅. UMC 0.18um异步电路标准单元库建库技术研究,微电子学,2008,6, 38(3): 350-355
[38] Bhatnagar H. Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler, Physical Compiler & Prime Time [M]. New York: Kluwer Academic Pub, 2001: 75-80
[39]尼尔H. E.维斯特大卫.哈里斯等著.“MOS大规模集成电路设计”[M].机械工业出版社2005,5
[40] R. Brentand, H. Kung A regular layout for parallel adders, IEEE Trans. Computers, 1982,3, C-31(3): 260-264
[41] M.Ercegovac.Digital Systems and Hardware/Firmware Algorithms,Chapter 12. Arithmetic Algorithms and Processors,John Wiley&Sons.1985
[42] G.Bewick.."Fast Multiplication:Algorithms and Implementation". Ph.D.Dissertation E.E.Dept.of Stanford Univ..1994
[43]阮坚.异步控制电路设计与实现关键技术研究,[工学博士学位论文].保存单位:国防科学技术大学,2008
[44]黄丽,罗仲.数字信号处理中的子字并行技术,零八一科技: 43-52。
[45]王蕾.异步嵌入式微处理器设计与分析关键技术研究,[工学博士学位论文].保存单位:国防科学技术大学,2006
[46]李勇.异步数据触发微处理器体系结构关键技术研究与实现,[工学博士学位论文].保存单位:国防科学技术大学,2007
[47]龚锐,王蕾,戴葵,王志英,异步集成电路C标准单元的设计与实现,微电子学与计算机,2005,1
[48] Martin, A. J. Formal program transformations for VLSI circuit synthesis, In Formal Developments of Programs and Proofs, UT Year of Programming Series (1987). Edited by Dijkstra EW, Addison-Wesley(1989), 1989: 59-80
[49] Berkel, K. v. Beware the Isochronic Fork, The VLSI Journal, 1992, 13: 103-128
[50] Tom Burd. Low-Power CMOS Library Design Methodology: Master Thesis. Electrical Engineering and Computer Sciences, University of California at Berkeley, 1995
[51] Virtuoso Layout Migrate User Guide. Version V2005. 12, Cadence Open Book, 2005