分立电荷俘获型存储器模拟研究
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摘要
随着传统浮栅存储器的尺寸缩小受到限制,急需要发展下一代非挥发存储器,目前对新一代非挥发存储器的研究非常广泛,有铁电存储器,阻变式存储器、纳米晶存储器,电荷陷阱存储器、相变存储器、有机物存储器等。其中分立电荷俘获型存储器的研究非常之多,其中电荷陷阱存储器(CTM:charge trapping memory)又是该领域的研究主流,它凭借其工艺与目j前主流CMOS工艺基本兼容的特性,CTM具有极大的潜力成为下一代非挥发存储器,从而率先占领新的存储器市场。
     传统浮栅存储器flash在小尺寸下存在严重的数据保持缺陷,浮栅阻挡层变薄,带来比较严重的信息泄露危险,因为薄的阻挡层在P/E过程中更容易产生缺陷,从而导致存储电荷一次性泄露。分立电荷俘获型存储器从理论上很好的解决这一问题,它利用电荷存储层中的分立陷阱来存储电荷的,从而将存储的电荷分立化,就算阻挡层中出现缺陷,也只能引起离缺陷最近的极小部分存储电荷的泄露,并不影响其存储信息的状态,从而保证存储器的正常工作。关于分立电荷俘获型存储器研究主要有三个大的方向,异是从结构上对电荷进行分立存储,如目前研究很多的纳米晶存储器;二是直接从存储材料入手,利用存储信息的化合物材料的分立陷阱来实现存储功能;三是将以上两种方法结合起来。
     采用纳米晶作为电荷存储介质,这种利用分立的纳米晶颗粒来实现电荷的分立存储,避免了传统浮栅闪存中因氧化层厚度变薄而引起信息泄漏的问题,在具有较好数据保持能力的情况下,能够相当程度的降低存储器件的操作电压。因而它也是下一代非易失性存储器的有力竞争者之一,引起广大研究者极大的兴趣。尽管分立电荷俘获型纳米晶存储器具有较快的擦/写速度、较低的操作电压等优势,但是尺寸缩小后,纳米晶的数量将会存在很大的限制,因为纳米晶数量越多,颗粒直径越大,存储性能越优越,这无疑是一对矛盾,而且不同器件在同一生产工艺下出来的数量可能都会波动,器件的均匀性也会受到较大影响。因此,我们仍需研究性能更为理想的非易失性存储器。
     与此同时发展起来的电荷陷阱存储器利用的是俘获层中材料本身的缺陷来存储电荷,利用不同材料中的陷阱,甚至通过对材料进行改性来获得更多的缺陷,进一步实现信息电荷的分立存储,它同时还可以实现多位存储,进而可以在相同的面积、技术条件下获得更高的存储密度,目前主流的电荷陷阱存储器结构SONOS至少可以达到22nm的工艺节点。由此可见,电荷陷阱存储器无疑有效的解决了很多问题,比如传统浮栅在小尺寸下的可靠性下降问题,突破了纳米晶存储器尺寸进一步缩小的瓶颈等等。
     综上,本文对分离电荷俘获型存储器展开了一系列的模拟研究,文章首先简单介绍了Flash memory的原理、结构与应用,接着突出介绍分立电荷俘获型存储器的主要结构原理及性能研究情况,第三章主要研究了纳米晶存储器结构对其存储性能的相关影响,第四章着重对CTM存储材料的模拟选取,以及其性能参
     数指标进行了着重的研究,采用新的视角与方法对CTM进一步研究起到了非常重要的借鉴作用,即采用了第一性原理对一些材料进行了深入的计算和分析,试图给CTM材料选取提供一套科学的解决方法,同时对存储材料中有效陷阱的选取也做了一定的模拟研究,从而进一步指导CTM实验的进行,对降低CTM研究成本,缩短其研究周期。最后综合总的研究,对本文的工作进行了总结跟展望。
With the restrict of reducing the size of of traditional floating gate memory, we urgent need to develop the next-generation non-volatile memory. At present, there is a very wide range of research about this new type of non-volatile memory, such as ferroelectric memory, resistive memory, nanocrystal memory, charge trapping memory, phase change memory and organics memory. Among these kinds of memories, descrete charge trapping memory is studied widely and CTM(charge trapping memory) is the main research stream because of its compatible process with the current CMOS technology, so CTM has the great potential to become the next-generation non-volatile memory and to occupy the future memory market quickly.
     When the size of fash memory scales down to very small, there will be serious defects on data retention. The thinner the floating barrier layer, the more dangerous the information disclosure, because that the barrier layer will easily produce defects during many P/E cycles, which will cause storage charges leak at one time. Discrete charge trapping memory, which is using the discrete traps in the charge storage layer to store charges seperately, it theoretically offers a good solution to above problem happened in flash memory with small size, at this condition, even if there is some defect in barrier layer, only a small party of the stored charges near the defect area will leak out, which will not affect the whole stored information state and then this device can work normally. There are three main research orientation on the discrete charge trapping memory. First, to achieve the information discrete storage by discrete structure, such as nanocrystal memory. Second, by using the traps or defects existing in material itself to store information seperately. Third, to combine the above tow methods together.
     Nanocrystal memory is a kind of non-volatile memory using the nanocrystals as the strage medium, such use of discrete nanocrystals can easily achieve discrete charges storage, which solve the information leakage happened in traditional flash memory when the barrier oxide getting thinner and thinner. Besides, nanocrystal memory can reduce the operating voltages and maintain good data retention. So it is also a strong contender for the next generation of nonvolatile memory, attracting great interest from the world. Although there are many advantages of nanocrystal memory, take the following features for example, good P/E speed, low operating voltages and so on. When the size is getting small, the number of the nanocrystals will get strict limited, because the larger the number of the nanocrystals and the diameter of the nanocrytals, the better the storage performance of the nanocrystal memory will be, obviously, the above phenomenon is a contradiction. And the number of nanocrystals in different devices from the same production process may be very different, which will be a great impact for device uniformity. Therefore, we need to explore a more ideal nonvolatile memory.
     At the same time, CTM is adopting the traps or defects existing in different charge trapping layer material itseltf to store charges, even in these materials having more or better traps an defects by modification to achieve better storage function. It also can achieve multibits storage, thus the storage density will be improved with the same area, same technology. At present, the main CTM structure SONOS device can at least reach22nm process node.Thus, charge trapping memory is undoubtedly a effective solution to many problems, such as the decline in reliability in the traditional floating memory under small size, breaking the bottleneck of the further reduction of nanocrystal memory size.
     In summary, this paper has launched a series of simulation studies about discrete charge trapping memory, Firstly, this article briefly describes the storage mechanism, structure and application of flash memory, and then the simple describtion of CTM storage mechanism, structure and research information. In chapter three, the main focus is put on the nanocrytal memory structure simulation and its corresponding electric simulation, which offers the relationship between the nanocrystal memory structure and the storage properties. In chapter four, great attention is put to the material selection guidance for charge trapping layer in CTM, the whole chapter focuse on the performance parameters extraction. A new perspective and method is adopted here to study CTM. MS, which is a material soft for material calculation and analysis, is used to computer charge trapping layer material, in order to offer a scientific method for material selection. Some research about effective defects selection is also done here, to assit the trapping layer material selection. All these work can play a great role in CTM research, which can reduce the CTM research costs, shorten the research cycle and ensure the experiment success. In final chapter, the overall study summarizes the work of this article and gives a outlook.
引文
[1]XIA Z L, KIM D S, LEE J Y, LEE K H, Investigation of Charge Loss Mechanisms in Planar and Raised STI Charge Trapping Flash Memories[C], Bologna, Italy, SISPAD 2010,14-A.2,pp.233-236
    [2]WU J Y, CHEN Y T, LIN M H, et al. Ultrathin HfON Trapping Layer for Charge-Trap Memory Made by Atomic Layer Deposition[J], IEEE ELECTRON DEVICE LETTER,2010 SEPTEMBER,VOL.31.NO.9,pp.993-995
    [3]ANDREA P, LUCA L, HEH D, et al. Modeling TANOS Memory Program Transients to Investigate Charge-Trapping Dynamics[J], IEEE ELECTRON DEVICE LETTERS,2009 AUGUST, VOL.30. NO.8,pp.882-884.
    [4]YANG H J, ALBERT C, LIN S H, YEH F S, et al. Improved High Temperature Retention for Charge-Trapping Memory by Using Double Quantum Barriers[J], IEEE ELECTRON LETTERS,2008,29 (4),pp.386-388.
    [5]Sandip Tiwari, Farhan Rana, Hussein Hanafi, Allan Hartstein, Emmanuel F. Crabbe and Kevin Chan, A silicon nanocrystals based memory[J], Appl.Phys.Lett. 68(10),4 March 1996,pp.1377-1379.
    [6]Zengtao Liu, Chungho Lee, Venkat Narayanan, Gen Pei, and Edwin Chihchuan Kan, Metal Nanocrystal Memories-Part I:Device Design and Fabrication[J], IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.49,NO.9,SEPTEMBER 2002,pp.1606-1613.
    [7]Weihua Guan, Shibing Long, Ming Liu, Zhigang Li, Yuan Hu and Qi Liu, Fabrication and charging characteristics of MOS capacitor with metal nanocrystals embedded in gate oxide[J], J.Phys.D:Appl.Phys.40(2007):2754-2758
    [8]Yu-Hsien Lin, Chao-Hsin Chien, Ching-Tzung Lin, Ching-Wei Chen, Chun-Yen Chang and Tan-Fu Lei, High Performance Multi-bit Nonvolatile HfO2 Nanocrystal Memory Using Spinodal Phase Separation of Hafnium Silicate[C], IEDM2004:1080-1082.
    [9]J.J.Lee, X.Wang, W.Bai, N.Lu, J.Liu, and D.L.Kwong, Theoretical and Experimental Investigation of Si Nanocrystal Memory Device with HfO2 High-k Tunneling Dielectric[C], Symposium on VLSI Technology Digest of Technical Papers 2003:33-34.
    [10]Seung Jae Baik, Siyoung Choi, U-In Chung, and Joo Tae Moon, High Speed and Nonvolatile Si Nanocrystal Memory for Scaled Flash Technology using Highly Field-Sensitive Tunnel Barrier[C], IEDM2003:545-548.
    [11]Yueran Liu, Sagnik Dey, Shan Tang, David Q. Kelly, J.Sarkar, and Sanjay K. Banerjee, Improved Performance of SiGe Nanocrystal Memory With VARIOT Tunnel Barrier[J], IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.53,NO.10, OCTOBER 2006,pp.2598-2602.
    [12]Y.M. Wan, K.van der Jeugd, T.Baron, B.De Salvo, P.Mur, Improved size dispersion of silicon nanocrystals grown in a batch LPCVD reactor[C], Mater.Res.Soc.Symp.Proc.Vol.8302005:D6.1.1-D6.1.6.
    [13]R.Muralidhar, R.F.Steimle, M.Sadd, et.al. An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V[C],2004 IEEE International Conference on Integrated Circuit Design and Technology:31-35.
    [14]L.Larcher and A.Padovani, Fundamental Reliability Issues of Advanced Charge-Trapping Flash Memory Devices[C], ICECS 2010,pp.1009-1012.
    [15]Zhigang Li, Weihua Guan, Ming Liu, Shibing Long, Rui Jia, Jin Lv, Yi Shi, Xinwei Zhao, Charge storage characteristics of metal-induced nanocrystalline in erbium-doped amorphous silicon films[J], Thin Solid Film 516(2008):7657-7660.
    [16]Boaz Eitan, Paolo Pavan, Ilan Bloom, Efraim Aloni Frommer, and David Finzi, NROM:A Novel Localized Trapping,2-bit Nonvolatile Memory Cell[J], IEEE ELECTRON DEVICE LETTERS, VOL.21,NO.11,NOVEMBER 2000, pp.543-545.
    [17]Chang Hyun Lee, Kyung In Choi, Myoung Kwan Cho, Yun Heub Song, Kyu Charn Park, and Kinam Kim, A Novel SONOS Structure of SiO2-SiN-A12O3 with TaN metal gate for multi-giga bit Flash memories[C], IEDM 2003:613-616.
    [18]Hang-Ting Lue, Szu-Yu Wang, Erh-Kun Lai, Yen-Hao Shih, Sheng-Chih Lai, Ling-Wu Yang, Kuang-Chao Chen, Joseph Ku, Kuang-Yeu Hsieh, Rich Liu, and Chih-Yuan Lu, BE-SONOS:A Bandgap Engineering SONOS with Excellent Performance and Reliability[C], IEDM2005:547-550.
    [19]SHIM S I, YEH F C, WANG X W, et al. Low Voltage High Speed Programming/ Erasing Charge Trapping Memory with Metal-Al2O3-SiN-Si3N4-Si Structure[C]. Monterey, California,Non-Volatile semiconductor Memory Workshop,22nd IEEE, 2007:103-105.
    [20]ZHANG G, CHANG H R, LI H M, et al. Modified Potential Well Formed by Si/SiO2/TiN/TiO2/SiO2/TaN for Flash Memory Application[J]. IEEE TRANSACTION ON ELECTRON DEVICE,2010,57(11):2794-2800
    [21]CHANG-LIAO K, LIU L, YE Z, et al. Improved Operation Characteristics for Charge-Trapping Flash Memory Devices with SiGe buried channel and Stacked Charge-Trapping Layers[C].Shanghai,China, Solid-State and Integrated Circuit Technology (ICSICT),2010 10th IEEE International Conference,2010:1061-1064.
    [22]CHA S, KIM H, CHOI D,et al. Memory Characteristics of Multilayer Structures with Lanthanum-Aluminate Charge Trap by Fowler-Nordheim Tunneling[C]. Hongkong, China, Nanoelectronics Conference (INEC),2010:1210-1211.
    [23]Mohammed B. Zahid, Daniel Ruiz Aguado, R.Degraeve, W.C.Wang, Bogdan Govoreanu, Maria Toledano-Luque, V.V.Afanas'ev, and Jan Van Houdt, Applying Complementary Trap Characterization Technique to Crystalline Ll-Phase-A12O3 for Improved Understanding of Novolatile Memory Operation and Reliability[J], IEEE TRANSACTIONS ON ELECTRON DEVICE, VOL.57,NO.11, NOVEMBER 2010,pp.2907-2916.
    [24]S.H.Lin, H.J.Yang, W.B.Chen, F.S.Yeh, Sean P. McAlister, and Albert Chin, Improving the Retention and Endurance Characteristics of Charge-Trapping Memory by Using Double Quantum Barriers[J], IEEE TRANSACTION ON ELECTRON DEVICE, VOL.55.NO.7.JULY 2008, pp.1708-1713.
    [25]Hang-Ting Lue, Sheng-Chih Lai, Tzu-Hsuan Hsu, Pei-Ying Du, Szu-Yu Wang, Kuang-Yeu Hsieh, Rich Liu, and Chih-Yuan Lu, Modeling of Barrier-Engineering Charge-Trapping NAND Flash Devices[J], IEEE TRANSACTION ON DEVICE AND MATERIALS RELIABILITY,VOL.10,NO.2,JUNE 2010,pp.222-232.
    [26]Liu Qi, Guan Weihua, Long Shibing, Jia Rui, Liu Ming, Chen Junning, Resistive Switching Memory Effect of ZrO2 Films with Zr+ Implanted[J], Applied Physics Letters, Vol.92,No.1,Jan 2008, pp.012117-012117-3.
    [27]Akeed A.Pavel and Naz Islam, On the Choice of High-k Dielectrics for Metal Nanocrystal Memory to Improve Data Retention[J], IEEE TRANSACTION ON NANOTECHNOLOGY, VOL.9,NO.3, MAY 2010, pp.345-347.
    [28]WU J Y, CHEN YT, LIN M H, et al. Ultrathin HfON Trapping Layer for Charge-Trap Memory Made by Atomic Layer Deposition[J], IEEE ELECTRON DEVICE LETTER,2010 SEPTEMBER,VOL.31.NO.9:993-995
    [29]Kinam Kim, Technology for sub-50nm DRAM and NAND Flash Manufacturing[J], IEDM2005:323-326.
    [30]Chakraborty, GSengupta, A.Requejo, F.G. Sarkar, C. K, Study of the relative performance of silicon and germanium nanoparticles embedded gate oxide in metal-oxide-semiconductor memory devices[J], Journal of Applied Physics,VOL.109,NO.6, Mar 2011, pp.064504-064504-6
    [31]Shiqian Yang, Qin Wang, Manhong Zhang, Shibing Long, Jing Liu and Ming Liu, Titanium-tungsten nanocrystals embedded in a SiO2/A12O3 gate dielectric stack for low-voltage operation in non-volatile memory[J], Nanotechnology 21(2010), pp.1-5.
    [32]Jeanlex Soares de Sousa, Robby Peibst, Milena Erenburg, Eberhard Bugiel, GA.Farias, Jean-Pierre Leburton, and Karl R.Hofmann, Single-Electron Charging and Discharging Analyses in Ge-Nanocrystal Memories[J], IEEE TRANSACTION ON ELECTRON DEVICE, VOL.58,N0.2, FEBRUARY 2011, pp.376-383.
    [33]Qin Wang, Rui Jia, Weihua Guan, Weilong Li, Qi Liu, Yuan Hu, Shibing Long, Baoqin Chen, Ming Liu, Tianchun Ye, Wensheng Lu and Long Jiang, Comparison of discrete-storage nonvolatile memories, advantage of hybrid method for fabrication of Au nanocrystals nonvolatile memory[J], Phys.D:Appl.Phys. 41(2008),pp.1-5.
    [34]C.-Y.Peng, W.Q.Zhang, X.Sun, Z.G.Liu, Sharon Cui, and T.P. Ma, A Charge-Trapping Memory Structure Featuring Low-Voltage High-Speed[C], IEDM2010:261-262.
    [35]Ho-Myoung An, Eui Bok Lee, Hee-Dong Kim, Yu Jeong Seo, and Tae Geun Kim, A New Class of Charge-Trap Flash Memory With Resistive Switching Mechanisms
    [J], IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.57,NO.10, OCTOBER 2010, pp.2398-2404.
    [36]Atanu Das, Liann Be Chang, Ray Ming Lin, Siddheswar Maikap, An Observation of Charge Trapping Phenomena in GaN/AlGaN/Gd2O3 MOS Schottky Structure[C],4th IEEE Internatinal NanoElectronics Conferences, Jan.2011,pp.1-2.
    [37]H.J.Yang, C.F.Cheng, W.B.Chen, S.H.Lin, F.S.Yeh, Sean P.McAlister, and Albert Chin, Comparison of MONOS Memory Device Integrity When Using Hfl-x-yNxOy Trapping Layers With Different N Compositions[J], IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.55,NO.6, JUNE 2008, pp.1417-1423.
    [38]M.Florian Beug, Thomas Melde, Malte Czernohorsky, Raik Hoffmann, Jan Paul, Roman Knoefler, and Armin T.Tilke, Analysis of TANOS Memory Cells With Sealing Oxide Containing Blocking Dielectric[J], IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.57,NO.7,JULY 2010, pp.1590-1596.
    [39]L.Liu, J.P.Xu, F.Ji, X.D.Huang, and P.T.Lai, A Novel MONOS Memory With High-κ HfLaON as charge-storage layer[J], IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL.11,NO.2,JUNE 2011, pp.244-247.
    [40]Chenxin Zhu, Zongliang Huo, Zhongguang Xu, Manhong Zhang, Qin Wang, Jing Liu, Shibing Long, and Ming Liu, Performance enhancement of multilevel cell nonvolatile memory by using a bandgap engineered high-K trapping layer[J], APPLIED PHYSICS LETTERS 97,2010,253503-1-253503-3.
    [41]J.P.Colonna, M.Bocquet, G.Molas, N.Rochat, P.Blaise, H.Grampeix, C.Licitra, D.Lafond, L.Masoero, V.Vidal, J.P.Barnes, M.Veillerot, and K.Yckache, Study of parasitic trapping in alumina used as blocking oxide for nonvolatile memories[J], J.Vac.Scl.Technol.B 29(1), Jan/Feb 2011,pp.01AE02-1-01AE02-5.
    [42]Dong Hua Li, Jang-Gn Yun, Jung Hoon Lee, and Byung-Gook Park, Scaling behaviors of silicon-nitride layer for charge-trapping memory[J], J.Vac.Sci. Technoi.A28(4), Jul/Aug 2010, pp.675-678.
    [43]Min Choul Kim, Chang Oh Kim, Houng Taek Oh, Suk-Ho Choi, K.Belay, R.G.Elliman, and S.P.Russo, Nonvolatile memories using deep traps formed in HfO2 by Nb ion implantation[J], JOURNAL OF APPLIED PHYSICS 109, 053703-1-053703-4.
    [44]Ping-Hung Tsai, Kuei-Shu Chang-Liao, Tai-Yu Wu, Tien-Ko Wang, Pei-Jer Tzeng, Cha-Hsin Lin, Lung-Sheng Lee and Ming-Jin Tsai, Novel SONOS-Type Nonvolatile Memory Device with Stacked Tunneling and charge-Trapping layers[C], ISDRS 2007,student paper.
    [45]G.Molas, L.Masoero, P.Blaise, A.Padovani, J.P.Colonna, E.Vianello,et.al. Investigation of the role of H-related defects in Al2O3 blocking layer, IEDM 2010:536-539.
    [46]C.Sandhya, Udayan Ganguly, Nihit Chattar, Christopher Olsen, Sean M.Seutter, Lucien Date, Raymond Hung, Juzer M.Vasi, and Souvik Mahapatra, Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler-Nordheim Tunneling Program/Erase Operation[J], IEEE ELECTRON DEVICE LETTERS, VOL.30,NO.2,FEBRUARY 2009, pp.171-173.
    [47]Mario Lanza, Marc Porti, Montserrat Nafri a, Xavier Aymerich, GUnther Benstetter, Edgar Lodermeier, et.al. Conductivity and Charge Trapping After Electrical Stress in Amorphous and Polycrustalline Al2O3-Based Devices Studied With AFM-Related Techniques[J], IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL.10,NO.2, MARCH 2011, pp.344-351.
    [48]G.Congedo, S.Spiga, U.Russo, A.Lamperti, O.Salicio, and E.Cianci, Evaluation of DyScOx as an alternative blocking dielectric in TANOS memories with Si3N4 or Si-rich charge trapping layers[J], J.Vac.Sci.Technol.B29(1), Jan/Feb 2011, pp.01AE04-1-01AE04-7.
    [49]Joe E.Brewer, Manzur Gill, Nonvolatile Memory Technologies with Emphasis on Flash [M], WILEY-INTERSCIENCE A JOHN WILEY & SONS, INC, PUBLICATION,2008.
    [50]Kenji Shiraishi, Keita Yamaguchi, Akira Otake, Katsumasa Kamiya, Yasuteru Shigeta, Guiding Principles for Charge Trap Memories-A Theoretical pproach-[C], ICSICT2010, pp.1096-1099.
    [51]K.Yamaguchi, A.Otake, K.Kobayashi, and K.Shiraishi, Atomistic Guiding Principles for MONOS-type Memories with High Program/Erase Cycle Endurance[C], IEDM2009, pp.1-4.
    [52]C.Y.Tsai, T.H.Lee, and Albert Chin, Arsenic-Implanted HfON Charge-Trapping Flash Memory With Large Memory Window and Good Retention[J], IEEE ELECTRON DEVICES LETTERS, VOL.32, NO.3, MARCH 2011, pp.381-383.

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