ESD保护栅结构的Trench MOSFET设计制造
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摘要
功率MOSFET是将微电子技术和电力电子技术融合起来的新一代功率半导体器件。因其具有输入阻抗高、开关速度快、输出电流大和热稳定性好、安全工作区宽等优点,在电源保护、电源开关、DC/DC变换器和同步整流等电子设备中得到广泛应用。
本文给出了一种带有ESD保护栅结构的Trench MOSFET的设计流程。和普通MOSFET相比,其创新之处在于植入了ESD保护结构,使其抗ESD能力相比普通MOSFET显著提高。本文的目的是在达到设计目标的同时尽量减少光刻版的层数,降低单位面积的导通电阻,从而有效控制成本。
第一部分是研究背景,包括功率MOSFET和ESD保护型功率MOSFET的发展、应用以及市场前景等。第二部分是理论基础,介绍了Trench MOSFET和ESD的理论知识,提出了在栅极区制造ESD保护结构方法,此方法可以有效控制芯片面积。第三部分是工程实践,首先通过经典理论公式推导出外延片规格;终端结构使用场板、多晶硅场限环和截止环的复合结构;ESD保护二极管先P型掺杂再N型注入的顺序使N注入可以和N+源区同时形成,减少了光刻版的数量;接下来使用Tsuprem4和Medici模拟软件初步定出流程基本条件,通过工程批的流片和封装数据对模拟条件进行校准和调整,最终的结果完全满足了预期的设计目标。
Power MOSFETs are an important class of discrete devices for a variety of power conversion applications because of high input impedance, high switching frequency,large output current, good thermal stability and large safe operating area.It is being widely applied in the electronics equipments such as buttery protection , switching-mode power supply, DC-DC converter , synchronous rectifiers and etc.
In this paper, a gate ESD protected Trench MOSFET is designed. The innovation is that this kind of Trench MOSFET get better ability on enduring ESD than normal MOSFET. The purpose of this article is to reduce the cost by decreasing the mask quantity and reducing RDSON per unit area.
The first part of this article is the research background. It includes the development, application and market prospects of power MOSFET and the ESD protected MOSFET. The second part is the theory including the basic theory of Trench MOSFET and ESD. Making ESD structure at the Gate PAD field is also be presented, this method can reduce die size effectively. The third part is the engineering practice. firstly, the Epi spec is get by a academic expressions; the terminal introduce a special structure with Field-board, poly Guard-ring and Stop-ring together; manufacturing ESD diode on the method of P type doping first and then N type implant so that N type implant can be formed at the same time with N+ source implant, by this way we can reduce one mask layer; Tsuprem4 and Medici software are used to get the basic condition of the process, after analyzing the result of engineering lot CP data, FT data and HBM ESD data, then the best design is selected which achieves expected aim very well.
本文给出了一种带有ESD保护栅结构的Trench MOSFET的设计流程。和普通MOSFET相比,其创新之处在于植入了ESD保护结构,使其抗ESD能力相比普通MOSFET显著提高。本文的目的是在达到设计目标的同时尽量减少光刻版的层数,降低单位面积的导通电阻,从而有效控制成本。
第一部分是研究背景,包括功率MOSFET和ESD保护型功率MOSFET的发展、应用以及市场前景等。第二部分是理论基础,介绍了Trench MOSFET和ESD的理论知识,提出了在栅极区制造ESD保护结构方法,此方法可以有效控制芯片面积。第三部分是工程实践,首先通过经典理论公式推导出外延片规格;终端结构使用场板、多晶硅场限环和截止环的复合结构;ESD保护二极管先P型掺杂再N型注入的顺序使N注入可以和N+源区同时形成,减少了光刻版的数量;接下来使用Tsuprem4和Medici模拟软件初步定出流程基本条件,通过工程批的流片和封装数据对模拟条件进行校准和调整,最终的结果完全满足了预期的设计目标。
Power MOSFETs are an important class of discrete devices for a variety of power conversion applications because of high input impedance, high switching frequency,large output current, good thermal stability and large safe operating area.It is being widely applied in the electronics equipments such as buttery protection , switching-mode power supply, DC-DC converter , synchronous rectifiers and etc.
In this paper, a gate ESD protected Trench MOSFET is designed. The innovation is that this kind of Trench MOSFET get better ability on enduring ESD than normal MOSFET. The purpose of this article is to reduce the cost by decreasing the mask quantity and reducing RDSON per unit area.
The first part of this article is the research background. It includes the development, application and market prospects of power MOSFET and the ESD protected MOSFET. The second part is the theory including the basic theory of Trench MOSFET and ESD. Making ESD structure at the Gate PAD field is also be presented, this method can reduce die size effectively. The third part is the engineering practice. firstly, the Epi spec is get by a academic expressions; the terminal introduce a special structure with Field-board, poly Guard-ring and Stop-ring together; manufacturing ESD diode on the method of P type doping first and then N type implant so that N type implant can be formed at the same time with N+ source implant, by this way we can reduce one mask layer; Tsuprem4 and Medici software are used to get the basic condition of the process, after analyzing the result of engineering lot CP data, FT data and HBM ESD data, then the best design is selected which achieves expected aim very well.
引文
[1]杨斌《中国功率器件市场发展现状》半导体产业研究中心2007-01
[2]刘恩科,朱秉升,罗晋生,等.半导体物理学[M].北京:国防工业出版社,1999:1—177.
[3]陈星弼.功率MOSFET与高压集成电路,南京:东南大学出版社,1990
[4]张为佐.功率半导体器件的新发展[A].电子产品世界,1998年1-2月,美国国际整流器公司(IR) p76
[5] D.Ueda et a1.,A new vertical power MOSFET structure with extremely reduced on-resistante.IEEE Trans.ED-32.No.1,P.2(1985)
[6] C.Bulucea.R.Rossen.Trench DMOS transistor technology for high current(100A range)switching,.Solid-State Electronics,Vo1.34,No.5,P.493(1991)
[7] S.Matsumoto et a1.,Ultra-low-specific on-resistance trench contacts for source and body regions realized by self-aligned process,Electronics Lett.,v01.27,P.1640—1642,199l
[8]Jongdae Kim,“A Novel technique for Fabricating High Reliable Trench DMOSFETs Using self-Align technique and Hydrogen Annealing”,IEEE Transactions On Electron Devices Vo1.50,No.2,Feb.2003
[9]Hidefumi Takaya,Kyosuke Miyagi,Kimimori Hamada,Yasushi Okura, Norihito Tokura,Akira Kuroyanagi,“Floating Island and Thick Bottom Oxide Trench Gate MOSFET(FITMOS)”,Proceedings of the 17 International Symposium on Power Semiconductor Devices&IC’S May 23-27,2005
[10]Suliman SA,Gallogunta N,Trabzon L,Hao J,Dolny G,Ridley R,etal.“the impact of Trench geometry and processing on the performance and reliability of low voltage power UMOSFETs.”,In Proc Reliability Physics Symposium,2001.P.308-14.
[11]Sodhi,R.,etal.“High-densityultra-low RDSON volts n-channel Trench FET for DC-DC converter application”,llth Intl.Symp.on Power Semiconductor Device and ICs (ISPSD’99),Toronto,Ont.,Canada,May 1999,PP.307-309.
[12]美施敏著《半导体器件物理与工艺》第二版苏州大学出版社
[13]闫冬梅,张雯.50V/40mΩVDMOSFET单胞尺寸的最佳设计[A].微处理机,2004,2:5.
[14]Park C K.Lee Kwyro.Experiments and 2D-simulations for quasi-saturation effect in power VDMOS transistor[C].In:Proc ISPSD.1990:219~222
[15]吴晓鹏,张娜.沟槽栅低压功率MOSFET的发展(上).北京工业大学功率器件及功率集成电路研究室.
[16] Lorenz, L. et al.,“COOLMOSTM-a new milestone in high voltage Power MOS”, Proceedings of ISPSD’99, 26-28 May 1999, pp.3-10.
[17]M.A.A. in’t Zandt et al.,“Record-low 4 mΩ·mm2 specific on-resistance for 20V Trench MOSFETs”, Proceedings of ISPSD’03, 14-17 April 2003, pp.32-35.
[18] Smerklo, L et al.,“The selection of cell optimal form and cells arrangement on the chip at DMOSFET design”, CADSM2003, pp.285
[19]孙嘉兴,杨颖,林爽.VDMOSFET的终端优化设计辽宁大学学报自然科学版第33卷第三期2006年辽宁大学物理系
[20] R.G.Wangner,J.Soden,and C.F.Hawkins.Extent and cost of EOS/ESD damage in an IC manufacturing process[C].In:Proc.15th EOS/ESD Symposium,1993:49-55.
[21]百度百科ESD词条什么是ESD http://baike.baidu.com/view/176445.htm
[22]殷志文.三种ESD模型及其防护设计,深圳电子学会电子可靠性专业委员会
[23]石甫渊,苏根政.具有ESD保护的齐纳二极管的DMOS,美国通用半导体公司,中国专利,02810428.5 [P].2002-5-22
[24]罗宏伟,恩云飞,杨银堂,朱樟明.多指条nMOSFET抗ESD设计技术[A].西安电子科技大学微电子所电路与系统学报2004年12月第9卷第六期p132-134
[25]李泽宏,易黎,张磊.多晶硅ESD结构保护的垂直双扩散金属氧化物半导体功率器件,中国专利,200610022264.2[P].2007-5-16
[26]丹尼尔.S.卡拉夫特,哈姆扎.伊尔马兹,史蒂文.萨普.用于功率金属氧化物半导体场效应晶体管及集成电路的递减电压多晶硅二极管静电放电电路,中国专利,200780034918.6[P].2007-10-1
[27]南京国盛电子有限公司VDMOS功率器件用硅外延片
[28]何进,王新,陈星粥.VDMOS均匀掺杂外延区的优化设计[J].半导体学报,1999,20(11):977-982.
[29]王蓉,李德昌.低压功率VDMOS的结构设计研究[A].电子科技,2010,23(4): 33-34
[30]朱袁正,秦旭光.一种深沟槽大功率MOS器件及其制造方法,中国专利,200710302461.4[P].2008-7-2
[31]阮刚著《集成电路工艺和器件的计算机模拟-IC TCAD技术概论》复旦大学出版社
[32]南通富士通封装厂内部文件“TSSOP-8 BONDING DIAGRAM”
[2]刘恩科,朱秉升,罗晋生,等.半导体物理学[M].北京:国防工业出版社,1999:1—177.
[3]陈星弼.功率MOSFET与高压集成电路,南京:东南大学出版社,1990
[4]张为佐.功率半导体器件的新发展[A].电子产品世界,1998年1-2月,美国国际整流器公司(IR) p76
[5] D.Ueda et a1.,A new vertical power MOSFET structure with extremely reduced on-resistante.IEEE Trans.ED-32.No.1,P.2(1985)
[6] C.Bulucea.R.Rossen.Trench DMOS transistor technology for high current(100A range)switching,.Solid-State Electronics,Vo1.34,No.5,P.493(1991)
[7] S.Matsumoto et a1.,Ultra-low-specific on-resistance trench contacts for source and body regions realized by self-aligned process,Electronics Lett.,v01.27,P.1640—1642,199l
[8]Jongdae Kim,“A Novel technique for Fabricating High Reliable Trench DMOSFETs Using self-Align technique and Hydrogen Annealing”,IEEE Transactions On Electron Devices Vo1.50,No.2,Feb.2003
[9]Hidefumi Takaya,Kyosuke Miyagi,Kimimori Hamada,Yasushi Okura, Norihito Tokura,Akira Kuroyanagi,“Floating Island and Thick Bottom Oxide Trench Gate MOSFET(FITMOS)”,Proceedings of the 17 International Symposium on Power Semiconductor Devices&IC’S May 23-27,2005
[10]Suliman SA,Gallogunta N,Trabzon L,Hao J,Dolny G,Ridley R,etal.“the impact of Trench geometry and processing on the performance and reliability of low voltage power UMOSFETs.”,In Proc Reliability Physics Symposium,2001.P.308-14.
[11]Sodhi,R.,etal.“High-densityultra-low RDSON volts n-channel Trench FET for DC-DC converter application”,llth Intl.Symp.on Power Semiconductor Device and ICs (ISPSD’99),Toronto,Ont.,Canada,May 1999,PP.307-309.
[12]美施敏著《半导体器件物理与工艺》第二版苏州大学出版社
[13]闫冬梅,张雯.50V/40mΩVDMOSFET单胞尺寸的最佳设计[A].微处理机,2004,2:5.
[14]Park C K.Lee Kwyro.Experiments and 2D-simulations for quasi-saturation effect in power VDMOS transistor[C].In:Proc ISPSD.1990:219~222
[15]吴晓鹏,张娜.沟槽栅低压功率MOSFET的发展(上).北京工业大学功率器件及功率集成电路研究室.
[16] Lorenz, L. et al.,“COOLMOSTM-a new milestone in high voltage Power MOS”, Proceedings of ISPSD’99, 26-28 May 1999, pp.3-10.
[17]M.A.A. in’t Zandt et al.,“Record-low 4 mΩ·mm2 specific on-resistance for 20V Trench MOSFETs”, Proceedings of ISPSD’03, 14-17 April 2003, pp.32-35.
[18] Smerklo, L et al.,“The selection of cell optimal form and cells arrangement on the chip at DMOSFET design”, CADSM2003, pp.285
[19]孙嘉兴,杨颖,林爽.VDMOSFET的终端优化设计辽宁大学学报自然科学版第33卷第三期2006年辽宁大学物理系
[20] R.G.Wangner,J.Soden,and C.F.Hawkins.Extent and cost of EOS/ESD damage in an IC manufacturing process[C].In:Proc.15th EOS/ESD Symposium,1993:49-55.
[21]百度百科ESD词条什么是ESD http://baike.baidu.com/view/176445.htm
[22]殷志文.三种ESD模型及其防护设计,深圳电子学会电子可靠性专业委员会
[23]石甫渊,苏根政.具有ESD保护的齐纳二极管的DMOS,美国通用半导体公司,中国专利,02810428.5 [P].2002-5-22
[24]罗宏伟,恩云飞,杨银堂,朱樟明.多指条nMOSFET抗ESD设计技术[A].西安电子科技大学微电子所电路与系统学报2004年12月第9卷第六期p132-134
[25]李泽宏,易黎,张磊.多晶硅ESD结构保护的垂直双扩散金属氧化物半导体功率器件,中国专利,200610022264.2[P].2007-5-16
[26]丹尼尔.S.卡拉夫特,哈姆扎.伊尔马兹,史蒂文.萨普.用于功率金属氧化物半导体场效应晶体管及集成电路的递减电压多晶硅二极管静电放电电路,中国专利,200780034918.6[P].2007-10-1
[27]南京国盛电子有限公司VDMOS功率器件用硅外延片
[28]何进,王新,陈星粥.VDMOS均匀掺杂外延区的优化设计[J].半导体学报,1999,20(11):977-982.
[29]王蓉,李德昌.低压功率VDMOS的结构设计研究[A].电子科技,2010,23(4): 33-34
[30]朱袁正,秦旭光.一种深沟槽大功率MOS器件及其制造方法,中国专利,200710302461.4[P].2008-7-2
[31]阮刚著《集成电路工艺和器件的计算机模拟-IC TCAD技术概论》复旦大学出版社
[32]南通富士通封装厂内部文件“TSSOP-8 BONDING DIAGRAM”