无线通信中剪枝FFT算法研究及其可配置VLSI设计与实现
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摘要
随着无线通信技术的快速发展,人们已经不再满足于简单的语音通信和低速率的数据传输,来自高速数据及多媒体业务的市场需求推动了各领域中无线通信标准的快速演进。但同时快速增长的高速数据传输需求也给无线通信系统的设计及其硬件实现带来了一系列的挑战,其中一个重要方面便是高速数据传输与复杂通信系统实现中巨大运算量所需的能量消耗和移动通信终端有限的电池容量之间的矛盾。虽然半导体工艺技术仍然遵循着摩尔定律在发展,但单纯依赖工艺的进步已经不能完全抵消无线通信系统中运算量快速增长所带来的功耗增加,通过设计方法和硬件架构上的改进以提高硬件实现的功耗效率成为目前研究者关注的重点。
从提高硬件实现功耗效率的角度出发,本文针对无线通信系统中,尤其是OFDM/OFDMA系统和认知无线电系统中具有广泛应用的剪枝FFT算法及其硬件实现进行了系统的研究,从算法、结构和硬件实现的不同层面对剪枝FFT进行了优化和改进。
本文首先分析了无线通信中剪枝FFT的应用,其中重点研究了OFDM/OFDMA系统中信道估计和调制解调以及认知无线电系统中的频谱感知和动态频谱接入算法中剪枝FFT使用的特点,确定了无线通信中剪枝FFT的应用需求；在分析和总结已有剪枝FFT算法和实现的基础上,确定了本文的研究内容和研究目标。
然后本文研究了通用的剪枝FFT算法。针对现有剪枝FFT算法中剪枝灵活性和适用范围不足的问题,文中提出了一种通用的混合基剪枝FFT算法,并给出了一般混合基SFG的剪枝计算方法；另外本文提出了一种分层剪枝策略,和高基(High-Radix) FFT的组合分解算法相结合,进一步降低了剪枝FFT的算法复杂度。
在通用剪枝FFT算法研究的基础上,本文针对通用剪枝FFT实现中的关键问题——剪枝SFG信息的组织方法进行了研究,其中重点针对硬件实现中剪枝信息的表示、存储和使用等问题进行了分析。文中提出了一种优化的SFG剪枝信息压缩方法,利用FFT SFG的结构特点和合理的软硬件划分,有效降低了剪枝信息的存储需求。
接下来本文研究了剪枝FFT的硬件实现架构并设计了通用的剪枝FFT可配置IP核。不同于已有文献中基于可编程计算平台或基于ASIC专用硬件的实现方法,本文从灵活性和功耗效率出发,根据通用剪枝FFT的算法特点,重新划分了剪枝FFT实现的软硬件界线,设计了以剪枝蝶形运算指令为核心的通用剪枝FFT可配置IP核,一方面为剪枝FFT的实现提供了高效灵活的运算引擎,另一方面为系统级剪枝FFT实现的优化提供了足够的灵活性。
最后本文设计并实现了通用可配置剪枝FFT处理器。文中针对剪枝蝶形运算指令的存储进行了优化,降低了剪枝FFT实现的硬件代价。基于本文结构的灵活性,提出了一种减少旋转因子读取的方法,降低了剪枝FFT计算中旋转因子存储器操作的能量消耗。本文设计的剪枝FFT处理器成功的基于SMIC0.13μm工艺进行了流片,测试结果验证了本文设计的有效性。
As the fast development of the wireless communication technology, its applications are no longer limited to voice and low data rates transmission. The huge market demand from the high data rates communication that can support streaming media, mobile internet, and etc. drives all wireless communication standards in various domains toward higher date rates.
But the rapid increase on data rates in wireless communication has also brought a series of challenges to the design and the hardware implementation of wireless communication systems, one important point of which is that on one hand the higher data rates processing and correspondingly the more complex wireless communication systems need more power consumption, but on the other hand the capacity of the battery increases in a much slower rate. Though the semiconductor technology still follows the Moore's Law, there is still a wide gap between the fast increasing power consumption and the capacity of the battery. More and more attention is paid to improve the design methodology and implementation architecture for higher power efficiency in wireless implementation.
Motivated by the importance of power efficiency in wireless communication systems, this dissertation studies the algorithm and the hardware implementation of FFT pruning that can be widely used in wireless communication for higher power efficiency in implementing some special FFT processing, and presents optimization and modification on existing algorithms and implementation schemes with the consideration on algorithm, architecture and hardware implementation.
Firstly this dissertation analyzes the application of FFT pruning in wireless communication, such as the DFT-based channel estimation in OFDM systems, modulation and demodulation in OFDMA systems, spectrum sensing in cognitive radio and spectrum shaping in dynamic spectrum access, and ascertain the requirement of FFT pruning in wireless communication. Then the research targets and contents are clarified on the basis of the complete survey on existing related work.
Secondly this dissertation presents our studies on generic FFT pruning algorithms. Being aware of the lack of enough flexibility and adaptability in existing algorithms, a novel pruning scheme is developed for mixed-radix and high-radix FFT pruning. The proposed approach is applicable over a wide range of FFT lengths and input/output pruning patterns. In addition, it can effectively employ the benefits of high-radix FFT algorithms that have lower computational complexity.
Then this dissertation focuses on the organization of the pruned SFG information which is one of the key points in effectively implementing the generic FFT pruning. The contents in this part concentrate on three aspects:pruned SFG description, storage of the information and the basic method of employing the information in implementing generic FFT pruning. This part also presents a new scheme for cutting down the storage of the pruned SFG information by employing the structural feature of SFG and software-hardware co-design methodology.
Following chapter mainly studies the hardware architecture of FFT pruning. Unlike exiting implementation schemes which are pure software on general or specific programmable platform or pure hardware in ASIC, this dissertation designs a reconfigurable IP core with pruned butterfly computing instruction for generic pruned FFT implementation. It adopts a new software-hardware partition strategy according to the algorithm feature of FFT pruning and can be used as the computing engine for FFT pruning. It also provides necessary flexibility for the optimization when implementing FFT pruning algorithm on system level.
Finally, based on the reconfigurable IP core, an integrated pruned FFT processor is designed and implemented. The scheme for decreasing storage proposed in previous part is employed for instruction compression and a new butterfly computing order in each stage of FFT processing is adopted that reduce the number of the reading operation on twiddle factor memory and corresponding power consumption. The processor is fabricated in SMIC0.13μm1P8M and the chip testing result validates the design.
从提高硬件实现功耗效率的角度出发,本文针对无线通信系统中,尤其是OFDM/OFDMA系统和认知无线电系统中具有广泛应用的剪枝FFT算法及其硬件实现进行了系统的研究,从算法、结构和硬件实现的不同层面对剪枝FFT进行了优化和改进。
本文首先分析了无线通信中剪枝FFT的应用,其中重点研究了OFDM/OFDMA系统中信道估计和调制解调以及认知无线电系统中的频谱感知和动态频谱接入算法中剪枝FFT使用的特点,确定了无线通信中剪枝FFT的应用需求；在分析和总结已有剪枝FFT算法和实现的基础上,确定了本文的研究内容和研究目标。
然后本文研究了通用的剪枝FFT算法。针对现有剪枝FFT算法中剪枝灵活性和适用范围不足的问题,文中提出了一种通用的混合基剪枝FFT算法,并给出了一般混合基SFG的剪枝计算方法；另外本文提出了一种分层剪枝策略,和高基(High-Radix) FFT的组合分解算法相结合,进一步降低了剪枝FFT的算法复杂度。
在通用剪枝FFT算法研究的基础上,本文针对通用剪枝FFT实现中的关键问题——剪枝SFG信息的组织方法进行了研究,其中重点针对硬件实现中剪枝信息的表示、存储和使用等问题进行了分析。文中提出了一种优化的SFG剪枝信息压缩方法,利用FFT SFG的结构特点和合理的软硬件划分,有效降低了剪枝信息的存储需求。
接下来本文研究了剪枝FFT的硬件实现架构并设计了通用的剪枝FFT可配置IP核。不同于已有文献中基于可编程计算平台或基于ASIC专用硬件的实现方法,本文从灵活性和功耗效率出发,根据通用剪枝FFT的算法特点,重新划分了剪枝FFT实现的软硬件界线,设计了以剪枝蝶形运算指令为核心的通用剪枝FFT可配置IP核,一方面为剪枝FFT的实现提供了高效灵活的运算引擎,另一方面为系统级剪枝FFT实现的优化提供了足够的灵活性。
最后本文设计并实现了通用可配置剪枝FFT处理器。文中针对剪枝蝶形运算指令的存储进行了优化,降低了剪枝FFT实现的硬件代价。基于本文结构的灵活性,提出了一种减少旋转因子读取的方法,降低了剪枝FFT计算中旋转因子存储器操作的能量消耗。本文设计的剪枝FFT处理器成功的基于SMIC0.13μm工艺进行了流片,测试结果验证了本文设计的有效性。
As the fast development of the wireless communication technology, its applications are no longer limited to voice and low data rates transmission. The huge market demand from the high data rates communication that can support streaming media, mobile internet, and etc. drives all wireless communication standards in various domains toward higher date rates.
But the rapid increase on data rates in wireless communication has also brought a series of challenges to the design and the hardware implementation of wireless communication systems, one important point of which is that on one hand the higher data rates processing and correspondingly the more complex wireless communication systems need more power consumption, but on the other hand the capacity of the battery increases in a much slower rate. Though the semiconductor technology still follows the Moore's Law, there is still a wide gap between the fast increasing power consumption and the capacity of the battery. More and more attention is paid to improve the design methodology and implementation architecture for higher power efficiency in wireless implementation.
Motivated by the importance of power efficiency in wireless communication systems, this dissertation studies the algorithm and the hardware implementation of FFT pruning that can be widely used in wireless communication for higher power efficiency in implementing some special FFT processing, and presents optimization and modification on existing algorithms and implementation schemes with the consideration on algorithm, architecture and hardware implementation.
Firstly this dissertation analyzes the application of FFT pruning in wireless communication, such as the DFT-based channel estimation in OFDM systems, modulation and demodulation in OFDMA systems, spectrum sensing in cognitive radio and spectrum shaping in dynamic spectrum access, and ascertain the requirement of FFT pruning in wireless communication. Then the research targets and contents are clarified on the basis of the complete survey on existing related work.
Secondly this dissertation presents our studies on generic FFT pruning algorithms. Being aware of the lack of enough flexibility and adaptability in existing algorithms, a novel pruning scheme is developed for mixed-radix and high-radix FFT pruning. The proposed approach is applicable over a wide range of FFT lengths and input/output pruning patterns. In addition, it can effectively employ the benefits of high-radix FFT algorithms that have lower computational complexity.
Then this dissertation focuses on the organization of the pruned SFG information which is one of the key points in effectively implementing the generic FFT pruning. The contents in this part concentrate on three aspects:pruned SFG description, storage of the information and the basic method of employing the information in implementing generic FFT pruning. This part also presents a new scheme for cutting down the storage of the pruned SFG information by employing the structural feature of SFG and software-hardware co-design methodology.
Following chapter mainly studies the hardware architecture of FFT pruning. Unlike exiting implementation schemes which are pure software on general or specific programmable platform or pure hardware in ASIC, this dissertation designs a reconfigurable IP core with pruned butterfly computing instruction for generic pruned FFT implementation. It adopts a new software-hardware partition strategy according to the algorithm feature of FFT pruning and can be used as the computing engine for FFT pruning. It also provides necessary flexibility for the optimization when implementing FFT pruning algorithm on system level.
Finally, based on the reconfigurable IP core, an integrated pruned FFT processor is designed and implemented. The scheme for decreasing storage proposed in previous part is employed for instruction compression and a new butterfly computing order in each stage of FFT processing is adopted that reduce the number of the reading operation on twiddle factor memory and corresponding power consumption. The processor is fabricated in SMIC0.13μm1P8M and the chip testing result validates the design.
引文
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[1]Johnson, L.G.. Conflict free memory addressing for dedicated FFT hardware[J]. IEEE Transactions on Circuits and Systems Ⅱ:Analog and Digital Signal Processing. 1992,39(5), pp.312-316.
[2]Byung G. Jo and Myung H. Sunwoo. New continuous-flow mixed-radix (CFMR) FFT Processor using novel in-place strategy[J]. IEEE Transactions on Circuits and Systems I:Regular Papers.2005,52(5), pp.911-919.
[3]Chun-Lung Huang, Syu-Siang Long and Muh-Tian Shiue. A low power and variable-length FFT processor design for flexible MIMO OFDM systems[J]. IEEE International Symposium on Circuits and Systems (ISCAS),2009.
[4]Sapatnekar S S, Su H H. Analysis and optimization of power grids [J]. IEEE Design and Test of Computers,2003,20 (3),7-15.
[5]Chao-Ming Cheng, Chien-Chang Huang and Yuan-Hao Huang. An Energy-Efficient Partial FFT Processor for the OFDMA Communication System[J]. IEEE Transactions on Circuits and Systems Ⅱ:Express Briefs.2010,57(2): pp.136-140.