无线接入SOC芯片的低功耗物理设计
摘要
当代超大规模集成电路设计日趋成熟,集成电路产业已经成为现代工业发展的基石,已经被广泛的应用到计算机、通讯、互联网、制造业等。当工艺发展到深亚微米的时候,功耗对电路的影响已经成为集成电路设计中的不可忽略的问题。功耗不但直接影响芯片的封装形式和成本,而且过高的功耗将导致芯片热量的增加,直接影响着芯片的可靠性。同时片上系统的设计是集成电路工艺提高的必然结果。对电路的性能、功耗、成本和可靠性都非常有利,已经成为集成电路发展的方向。但由于门数较多,功耗也就成为一个设计中的瓶颈问题。
无线接入SOC芯片是无线自组织网的节点芯片,无线传感网络的上层协议采用的是基于IEEE802.15.4自行开发的协议,主要是针对低功耗、低速率的应用,数据传输速率在100Kps左右。本文研究了该芯片从逻辑综合到物理实现各个阶段的低功耗设计及其实施方法,为芯片的低功耗设计提供了方法和流程上的参考。该设计在芯片中均获得了有效的验证,可以应用在其它芯片设计中。为其它的芯片设计奠定基础。
全文首先详细阐述了低功耗设计技术的发展状况以及研究意义,接下来具体分析了功耗的组成,以及在逻辑设计阶段动态功耗和静态功耗的优化方法。论文以无线接入SOC芯片为例,基于Cadence的EDA平台,对无线接入SOC芯片在逻辑综合阶段进行了低功耗的优化,主要采用的是门控时钟方法,并比较了优化结果;同时对无线接入SOC芯片的完成了后端设计,并对于物理实现的每个过程中的功耗优化策略进行了详细研究。在布局阶段:通过不断分析比较得到了最佳功耗布局方案;在时钟树生成阶段:采用多种功耗优化方法实现了低功耗设计。论文最后分析了深亚微米工艺条件下电源完整性问题,并进行了物理验证,以及问题的修复。
In the present ages, the development of VLSI design is tend to be mature, IC industry has become the footstone of the development of modern industry, It has been broad applied to computer, communication, internet and manufacturing. When the process grow to deep sub micron, power could not be ignored in IC design., it not only effect the package and cost, but also lead to the too much heat, which directly effect chip reliability. SOC design is the result of IC development. It’s helpful for the circuit performance, power, cost and reliability, which has become to the direction of IC development. But with area growing, power has become to the key problem of IC design.
Wireless access SOC chip is Wireless access chip, higher-layer protocol is based on the IEEE802.15.4 own develop protocol, mostly based on low power, low speed application, transmission speed is about 100Kps. This paper describes concept and methods of the implement of low power design of WirelessChip from logic synthesis to physical design, which provide a reference of implement method and flow. It can apply to other chip design to the basic of other chip design.
This paper first provide an overview of low power technology development and research signification; then discusses the power distribution and optimization of all level. presents the method of low power synthesis of WirelessChip;.Based on Cadence EDA platform, implemented logic design and emphasized clock tree synthesis of low power, implemented low power physical design, floorplan phase adopt many methods for a better result, cts phase applied many ways to implemented low power design. At last this paper analyzed the power and physical verification problem of deep-sub micron process.
无线接入SOC芯片是无线自组织网的节点芯片,无线传感网络的上层协议采用的是基于IEEE802.15.4自行开发的协议,主要是针对低功耗、低速率的应用,数据传输速率在100Kps左右。本文研究了该芯片从逻辑综合到物理实现各个阶段的低功耗设计及其实施方法,为芯片的低功耗设计提供了方法和流程上的参考。该设计在芯片中均获得了有效的验证,可以应用在其它芯片设计中。为其它的芯片设计奠定基础。
全文首先详细阐述了低功耗设计技术的发展状况以及研究意义,接下来具体分析了功耗的组成,以及在逻辑设计阶段动态功耗和静态功耗的优化方法。论文以无线接入SOC芯片为例,基于Cadence的EDA平台,对无线接入SOC芯片在逻辑综合阶段进行了低功耗的优化,主要采用的是门控时钟方法,并比较了优化结果;同时对无线接入SOC芯片的完成了后端设计,并对于物理实现的每个过程中的功耗优化策略进行了详细研究。在布局阶段:通过不断分析比较得到了最佳功耗布局方案;在时钟树生成阶段:采用多种功耗优化方法实现了低功耗设计。论文最后分析了深亚微米工艺条件下电源完整性问题,并进行了物理验证,以及问题的修复。
In the present ages, the development of VLSI design is tend to be mature, IC industry has become the footstone of the development of modern industry, It has been broad applied to computer, communication, internet and manufacturing. When the process grow to deep sub micron, power could not be ignored in IC design., it not only effect the package and cost, but also lead to the too much heat, which directly effect chip reliability. SOC design is the result of IC development. It’s helpful for the circuit performance, power, cost and reliability, which has become to the direction of IC development. But with area growing, power has become to the key problem of IC design.
Wireless access SOC chip is Wireless access chip, higher-layer protocol is based on the IEEE802.15.4 own develop protocol, mostly based on low power, low speed application, transmission speed is about 100Kps. This paper describes concept and methods of the implement of low power design of WirelessChip from logic synthesis to physical design, which provide a reference of implement method and flow. It can apply to other chip design to the basic of other chip design.
This paper first provide an overview of low power technology development and research signification; then discusses the power distribution and optimization of all level. presents the method of low power synthesis of WirelessChip;.Based on Cadence EDA platform, implemented logic design and emphasized clock tree synthesis of low power, implemented low power physical design, floorplan phase adopt many methods for a better result, cts phase applied many ways to implemented low power design. At last this paper analyzed the power and physical verification problem of deep-sub micron process.
引文
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[2] Bhasker著.徐振林译.Verilog HDL硬件描述语言.机械工业出版1997 pp22～45
[3] 梁宇, SOC低功耗设计与DFT[D], 东南大学博士学位论文, 2000.
[4] Wan M, Zhang H, George V, et al, Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System, Journal of VLSI Signal Processing, 2000
[5] Jun Yang, Rajiv Gupta, Chun Jun Zhuang, Frequent Value Encoding for Low Power Data Buses, ACM Transactions on Design Automation of Electronic Systems, Vol. 9, No. 3, July 2004.
[6] G. G. Shahidi, SOI technology for the GHz era, IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.
[7] Tesi di Dottorato di Ricerca in Ingegneria dell'Informazione, Università degli Studi di Brescia,Power Estimation and Optimization Methodologies for Digital Circuits and Systems, http://www.elet.polimi.it/upload/silvano/mioweb5/Paperi_IEEE/index.htm
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[9] Kao James T, Chandrakasan Anantha P, Dural-Threshold Voltage Techniques for Low-Power Digital Circuits [J], IEEE Journal of Solid-State Circuits, July 2000, 35(7).
[10] J P.Vanoostende, et al. Evaluation of the limitations of the simple CMOS powerestimation formula: comparison with accurate estimation.In: Proc of European workshop on power and timing modeling, Paris,1992, 16-25
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[12] Lekatsas H,Henkel J,Wolf W,Arithmetic Coding for Lower Power Embedded System Design.In:Data Compression Conference,Utah,2000,430-439
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[16] Z.Lu, J. Hein, M. Humphrey, M. Stan, J. Lach and K. Skadron, control-theroretic dynamic frequency and voltage scaling, In Proceeding of the 2002 Workshop on Self-Healing, Adaptive and Self-Managed systems (SHAMAN’02), June 2002.
[17] Kaushik Roy,Sharat Prasad.Low Power CMOS VLSI Circuit Design.New York:A wiley Interscience Publication,2000,5-43
[18] M.Johnson,D.Somasekhar,K.Roy.Leakage control with efficient use of transistor stacks in single threshold CMOS.In: Proc of 36th Design Automation Conf,New Orleans,1999,442-445
[19] Johan Pouwelse, Koen Langendoen, Henk Spis, Dynamic Voltage Scaling on a Low-Power Microprocessor.
[20] N. Zamdmer, A. Ray, J-O. Plouchart, L. Wagner, N. Fong, K. A. Jenkins, W. Jin, P. Smeys, I. Yang, G.Shahidi, and F. Assaderaghi, SOI CMOS for Low Power and RF, Symposium on VLSI Technology, Digest of Technical Papers, p. 85, 2001.
[21] G. Shahidi, SOI technology for the GHz era, IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.
[22] ITRS,International Technology Roadmap for Semiconductor,2001 Edition.http://public.itrs.net/Files/2001ITRS/Home.htm
[23] Yuan Taur,T.H.Ning.Fundamentals of Modern VLSI Devices.New York:Cambridge Univ.Press,1998,120-128
[24] Design Compiler User Manual, Version 5.0.11, Cadence Co, September 2003.
[25] Quick Reference for Power Compiler, Version 4.1.1, Cadence Co, August 2004.
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[27] Low Power in EncounterTM Design Compiler Ultra, Version 4.1.2, Cadence Co, 2004.
[28] Encounter User Guide, Product Version 4.1.2, Cadence Co, 2004.
[29] Segars S, Low power design techniques for microprocessors [A], ISSCC[C], 2001.
[30] Erik J. Mentze, Kevin M. Buck, Herbert L. Hess, David Cox, Mohammad Mojarradi,A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25um, PD SOI Process,ISVL’04, p.218, Feb2004.
[31] Yangdong Deng, Wojciech P. Maly, Interconnect characteristics of 2.5-D system integration scheme, Proceedings of the 2001 international symposium on Physical design, Pages: 171-175, 2001.
[32] G.Wei and M. Horowitz,A Lower Power Switching Power Supply for Self-Clocked S ystem.International Symposium on Low Power Electronics and Design,pp313-317,Aug.1996.
[33] NanoRoute User’s Manual.Version 4.1.2,Cadence Co,2004
[34] N.Verghese,D.Allstot,and M. Wolfe.Verification techniques for substrate coupling and their application to mixed-signal IC design[J].IEEE J. Solid-State Circuit,vol. 31,pp. 354-365,Mar.1996
[35] M. Beattie and L. Pileggi. IC analyzes includeing extracted inductance models[C],Proc.36th Int. Conf. Design Automation,June 1999,pp.915-920
[36] CeltIC User Guide, Product Version 4.3, Cadence Co, 2004
[37] Takashi Mitsuhashi, Ernest S.Kuh.Power and Ground Network Topology Optimization for Cell based VLSI[C].29th ACMIIEEE Design Automation Conference 1992
[38] VoltageStorm Transistor-Level PGS User Guide, Version 4.0.1, Cadence Co, 2004
[39] Standard Verification Rule Format Manual. Mentor Company,2003.9. pp 200-1684
[2] Bhasker著.徐振林译.Verilog HDL硬件描述语言.机械工业出版1997 pp22～45
[3] 梁宇, SOC低功耗设计与DFT[D], 东南大学博士学位论文, 2000.
[4] Wan M, Zhang H, George V, et al, Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System, Journal of VLSI Signal Processing, 2000
[5] Jun Yang, Rajiv Gupta, Chun Jun Zhuang, Frequent Value Encoding for Low Power Data Buses, ACM Transactions on Design Automation of Electronic Systems, Vol. 9, No. 3, July 2004.
[6] G. G. Shahidi, SOI technology for the GHz era, IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.
[7] Tesi di Dottorato di Ricerca in Ingegneria dell'Informazione, Università degli Studi di Brescia,Power Estimation and Optimization Methodologies for Digital Circuits and Systems, http://www.elet.polimi.it/upload/silvano/mioweb5/Paperi_IEEE/index.htm
[8] Frank Schirrmeister, Design for Low Power at the Electronic System Level, ChipVision Design Systems, Avant Technology Inc. 2004.
[9] Kao James T, Chandrakasan Anantha P, Dural-Threshold Voltage Techniques for Low-Power Digital Circuits [J], IEEE Journal of Solid-State Circuits, July 2000, 35(7).
[10] J P.Vanoostende, et al. Evaluation of the limitations of the simple CMOS powerestimation formula: comparison with accurate estimation.In: Proc of European workshop on power and timing modeling, Paris,1992, 16-25
[11] C. Guardiani, A. Macii, E. Macii, M. Poncino, M. Rossello, R. Scarsi, e R. ZafalonA A,RTL Power Embedded Estimation in a Industrial Design Flow, IEEE Alessandro Volta Memorial Workshop on Low-Power Design, Como, Italy, 4-5 marzo, 1999, pp. 91-96.
[12] Lekatsas H,Henkel J,Wolf W,Arithmetic Coding for Lower Power Embedded System Design.In:Data Compression Conference,Utah,2000,430-439
[13] L.Benini and G. De Micheli, Dynamic Power Management of Circuit and System:Design Techniques and CAD Tools, Klwer, 1997.
[14] Pant P,Vivek De,Chatterjee A.Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks.In:Proceeding of Design Automation Conference,Las Vegas,1997,403-408
[15] V. Zaccaria, M. Sami, e D. Sciuto, Power Estimation and Optimization Methodologies for VLIW-Based Embedded Systems, Kluwer Academic Publishers, Boston Hard bound, ISBN 1-4020-7377-1, February 2003, 203 pp.
[16] Z.Lu, J. Hein, M. Humphrey, M. Stan, J. Lach and K. Skadron, control-theroretic dynamic frequency and voltage scaling, In Proceeding of the 2002 Workshop on Self-Healing, Adaptive and Self-Managed systems (SHAMAN’02), June 2002.
[17] Kaushik Roy,Sharat Prasad.Low Power CMOS VLSI Circuit Design.New York:A wiley Interscience Publication,2000,5-43
[18] M.Johnson,D.Somasekhar,K.Roy.Leakage control with efficient use of transistor stacks in single threshold CMOS.In: Proc of 36th Design Automation Conf,New Orleans,1999,442-445
[19] Johan Pouwelse, Koen Langendoen, Henk Spis, Dynamic Voltage Scaling on a Low-Power Microprocessor.
[20] N. Zamdmer, A. Ray, J-O. Plouchart, L. Wagner, N. Fong, K. A. Jenkins, W. Jin, P. Smeys, I. Yang, G.Shahidi, and F. Assaderaghi, SOI CMOS for Low Power and RF, Symposium on VLSI Technology, Digest of Technical Papers, p. 85, 2001.
[21] G. Shahidi, SOI technology for the GHz era, IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.
[22] ITRS,International Technology Roadmap for Semiconductor,2001 Edition.http://public.itrs.net/Files/2001ITRS/Home.htm
[23] Yuan Taur,T.H.Ning.Fundamentals of Modern VLSI Devices.New York:Cambridge Univ.Press,1998,120-128
[24] Design Compiler User Manual, Version 5.0.11, Cadence Co, September 2003.
[25] Quick Reference for Power Compiler, Version 4.1.1, Cadence Co, August 2004.
[26] Saraju P. Mohanty, N. Ranganathan, University of South Florida,V. Krishna, Agilent Technology,Datapath Scheduling using Dynamic Frequency Clocking,IEEE Computer Society Annual Symposium on VLSI, April 25 - 26, 2002, Pittsburgh, Pennsylvania.
[27] Low Power in EncounterTM Design Compiler Ultra, Version 4.1.2, Cadence Co, 2004.
[28] Encounter User Guide, Product Version 4.1.2, Cadence Co, 2004.
[29] Segars S, Low power design techniques for microprocessors [A], ISSCC[C], 2001.
[30] Erik J. Mentze, Kevin M. Buck, Herbert L. Hess, David Cox, Mohammad Mojarradi,A Low Voltage to High Voltage Level Shifter in a Low Voltage, 0.25um, PD SOI Process,ISVL’04, p.218, Feb2004.
[31] Yangdong Deng, Wojciech P. Maly, Interconnect characteristics of 2.5-D system integration scheme, Proceedings of the 2001 international symposium on Physical design, Pages: 171-175, 2001.
[32] G.Wei and M. Horowitz,A Lower Power Switching Power Supply for Self-Clocked S ystem.International Symposium on Low Power Electronics and Design,pp313-317,Aug.1996.
[33] NanoRoute User’s Manual.Version 4.1.2,Cadence Co,2004
[34] N.Verghese,D.Allstot,and M. Wolfe.Verification techniques for substrate coupling and their application to mixed-signal IC design[J].IEEE J. Solid-State Circuit,vol. 31,pp. 354-365,Mar.1996
[35] M. Beattie and L. Pileggi. IC analyzes includeing extracted inductance models[C],Proc.36th Int. Conf. Design Automation,June 1999,pp.915-920
[36] CeltIC User Guide, Product Version 4.3, Cadence Co, 2004
[37] Takashi Mitsuhashi, Ernest S.Kuh.Power and Ground Network Topology Optimization for Cell based VLSI[C].29th ACMIIEEE Design Automation Conference 1992
[38] VoltageStorm Transistor-Level PGS User Guide, Version 4.0.1, Cadence Co, 2004
[39] Standard Verification Rule Format Manual. Mentor Company,2003.9. pp 200-1684