DVD伺服控制微处理器集成电路的设计
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摘要
作为DVD驱动和管理SOC(System On Chip)芯片中的一部分，DVD伺服控制微处理器被设计用来执行DVD系统的伺服控制程序，如聚焦，旋转，寻道，寻迹等控制任务。
为了获得比较高的性能，设计DVD伺服控制微处理器时，采用了具有RISC特征的指令集，程序和数据总线分离的哈佛结构，内部使用了四条程序和数据总线。为了支持加法，减法，乘法，跳转及数据传输等指令设计了相应的执行和控制逻辑。
为了适应DVD伺服控制微处理器执行伺服控制算法，本次设计中DVD伺服控制微处理器采用三块独立的位宽不同的内存空间和相应的总线和20位宽的内部数据总线和运算逻辑单元。内存空间中SVRAM(State Variable RAM)和KRAM(Coefficient RAM)用来存放程序的变量和参数，第三块IRAM(Instruction RAM)用来存放DVD伺服控制微处理器的程序。
DVD伺服控制微处理器集成电路的设计严格地遵循深亚微米数字集成电路设计流程。本次设计因采用了数字集成电路RTL级低功耗设计技术，使得DVD伺服控制微处理器有很好的节能特性，功耗仅有0.2 mW／MHz。本次设计还采用了指令执行单元在时钟的上升沿和下降沿都进行数据处理的设计结构使得指令流水线的级数降低到两级，从而降低了指令流水线控制逻辑设计的复杂度，也省去了编译器设计时对各种冒险的处理。
DVD伺服控制微处理器集成电路的设计经过验证能达到要求的性能，绝大部分指令都在一个时钟周期内完成，在台积电．18um CMOS工艺下，DVD伺服控制微处理可达到100MHz的时钟频率。
As a part of DVD drive manager SOC (System On Chip) , DVD servo control microprocessor architecture was designed to perform routine, periodic servo tasks, such as focus, spindle, track seeking and track following.
To archive high performance, DVD servo control microprocessor uses RISC like instruction set. Harvard architecture has been used for the servo control microprocessor, having four program and data buses. In order to support addition, subtraction, multiplication, branch and movement instruction, corresponding control logic and execute unit were designed..
There are three distinct and memory spaces with associated buses and 20bits internal data bus and operation unit. In light of the algorithms for which the SCP is intended, this particular organization is a natural choice. Two of the memories, the SVRAM (State Variable RAM) and the KRAM (Coefficient RAM), store program variables and constants. A third memory, the IRAM (Instruction RAM), provides program storage.
Design of servo control microprocessor strictly follows the design flow of deep submicron digital IC. Servo control microprocessor introduces low power design technology in RTL level, so it has good power saving feature, only consuming 0.2 mW/MHz. Instructions execute unit processes data not only at positive edge of clock, but also at negative edge of clock, so instruction pipeline was shortened to two levels. This reduces design complexity of instruction pipeline control logic, avoid dealing with pipeline hazards when designing compiler.
Design of DVD servo control microprocessor was validated and can meet system performance. Most of instructions can finish in a clock cycle. Using TSMC . 18um COMS process, DVD servo control microprocessor can run at 100 MHz frequencies.
为了获得比较高的性能，设计DVD伺服控制微处理器时，采用了具有RISC特征的指令集，程序和数据总线分离的哈佛结构，内部使用了四条程序和数据总线。为了支持加法，减法，乘法，跳转及数据传输等指令设计了相应的执行和控制逻辑。
为了适应DVD伺服控制微处理器执行伺服控制算法，本次设计中DVD伺服控制微处理器采用三块独立的位宽不同的内存空间和相应的总线和20位宽的内部数据总线和运算逻辑单元。内存空间中SVRAM(State Variable RAM)和KRAM(Coefficient RAM)用来存放程序的变量和参数，第三块IRAM(Instruction RAM)用来存放DVD伺服控制微处理器的程序。
DVD伺服控制微处理器集成电路的设计严格地遵循深亚微米数字集成电路设计流程。本次设计因采用了数字集成电路RTL级低功耗设计技术，使得DVD伺服控制微处理器有很好的节能特性，功耗仅有0.2 mW／MHz。本次设计还采用了指令执行单元在时钟的上升沿和下降沿都进行数据处理的设计结构使得指令流水线的级数降低到两级，从而降低了指令流水线控制逻辑设计的复杂度，也省去了编译器设计时对各种冒险的处理。
DVD伺服控制微处理器集成电路的设计经过验证能达到要求的性能，绝大部分指令都在一个时钟周期内完成，在台积电．18um CMOS工艺下，DVD伺服控制微处理可达到100MHz的时钟频率。
As a part of DVD drive manager SOC (System On Chip) , DVD servo control microprocessor architecture was designed to perform routine, periodic servo tasks, such as focus, spindle, track seeking and track following.
To archive high performance, DVD servo control microprocessor uses RISC like instruction set. Harvard architecture has been used for the servo control microprocessor, having four program and data buses. In order to support addition, subtraction, multiplication, branch and movement instruction, corresponding control logic and execute unit were designed..
There are three distinct and memory spaces with associated buses and 20bits internal data bus and operation unit. In light of the algorithms for which the SCP is intended, this particular organization is a natural choice. Two of the memories, the SVRAM (State Variable RAM) and the KRAM (Coefficient RAM), store program variables and constants. A third memory, the IRAM (Instruction RAM), provides program storage.
Design of servo control microprocessor strictly follows the design flow of deep submicron digital IC. Servo control microprocessor introduces low power design technology in RTL level, so it has good power saving feature, only consuming 0.2 mW/MHz. Instructions execute unit processes data not only at positive edge of clock, but also at negative edge of clock, so instruction pipeline was shortened to two levels. This reduces design complexity of instruction pipeline control logic, avoid dealing with pipeline hazards when designing compiler.
Design of DVD servo control microprocessor was validated and can meet system performance. Most of instructions can finish in a clock cycle. Using TSMC . 18um COMS process, DVD servo control microprocessor can run at 100 MHz frequencies.
引文
[1] Abdellatif Bellaouar, Mohamed Elmasry I. Low-Power Digital Vlsi Design, Kluwer Academic Publishers, 1995
[2] K. Roy and A. chatterjee, "low-Power VLSI Design, " IEEE Design and Test of Computers, Winter 1994.
[3] L. H. Lee, J. Scott, B. Moyer, and J. Arends, "Low-cost branch folding for embedded applications with small tight loops, "MICRO-32, pp.103-111, Nov.1999.
[4] J. Monteiro, S. Devadas, and A. Ghosh, "Sequential logic optimization for low power using input-disabling precomputation architectures, " IEEE Trans. Computer-Aided Design, vol.17, pp.279-284, Mar.1998.
[5] V. Tiwari, S. Malik, and P. Ashar, "Guarded evaluation: Pushing power management to logic synthesis/design, " IEEE Trans. Computer-Aided Design, vol.17, pp. 1051-1060, Oct. 1998.
[6] W. M. Chung and M. Sachdev, "A comparative analysis of dual edge triggered flip-flops, " in 2000 Canadian Conf. Electrical and Computer Engineering, vol.1, 2000.
[7] A. Dharchoudhuryet al., "Transistor-level sizing and timing verification of domino circuits in the PowerPC microprocessor, " in Proc. IEEE Int. Conf. Computer Design, Oct.1997.
[8] F. Anceau, "A synchronous approach for clocking VLSI systems, " IEEE J. Solid-State Circuits, vol.SC-17, pp. 51-56, Feb. 1982.
[9] M. A. Franklin and D. F. Wann, "Asynchronous and clocked control structures for VLSI based interconnection networks, " in Proc. 9th Annu. Symp. Computer Architecture, Apr. 1982, pp. 50-59.
[10] D. Wann and M. Franklin, "Asynchronous and clocked control structures for VLSI based interconnection networks, " IEEE Trans. Comput., vol. C-32, pp. 284-293, Mar. 1983.
[11] S. Dhar, M. Franklin and D. Wann, "Reduction of clock delays in VLSI structures, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1984, pp. 778-783.
[12] S. Unger and C.-J. Tan, "Optimal clocking schemes for high speed digital systems, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1983, pp. 366-369.
[13] J. Beausang and A. Albicki, "A method to obtain an optimal clocking scheme for a digital system, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1983, pp. 68-72.
[14] S. H. Unger and C.-J. Tan, "Clocking schemes for high-speed digital systems, " IEEE Trans. Comput., vol.C-35, pp. 880-895, Oct. 1986.
[15] D.Noice, R.Mathews, and J. Newkirk, "A clocking discipline for two-phase digital systems, " in Proc. IEEE Int. Conf. Circuits and
Computers, Sept. 1982, pp. 108-111.
[16] C. Svensson, "Signal resynchronization in VLSI system, " Int. VLSI J., vol.4, pp. 75-80, Mar. 1986.
[17] F. Anceau, "A synchronous approach for clocking VLSI systems, " IEEE J. Solid-State Circuits, vol.SC-17, pp.51-56, Feb. 1982.
[18] M. A. Franklin and D. F. Wann, "Asynchronous and clocked control structures for VLSI based interconnection networks, " in Proc. 9th Annu. Symp. Computer Architecture, Apr. 1982, pp.50-59.
[19] D. Warm and M. Franklin, "Asynchronous and clocked control structures for VLSI based interconnection networks, " IEEE Trans. Comput., vol. C-32, pp. 284-293, Mar. 1983.
[20] S. Dhar, M. Franklin, andD. Warm, "Reduction of clock delays in VLSI structures, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1984, pp. 778-783.
[21] S. Unger and C.-J. Tan, "Optimal clocking schemes for high speed digital systems, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1983, pp. 366-369.
[22] J. Beausang and A. Albicki, "A method to obtain an optimal clocking scheme for a digital system, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1983, pp. 68-72.
[23] S. H. Unger and C.-J. Tan, "Clocking schemes for high-speed digital systems, " IEEE Trans. Comput., vol.C-35, pp.880-895, Oct. 1986.
[24] D. Noice, R. Mathews, and J. Newkirk, "A clocking discipline for two-phase digital systems, " in Proc. IEEE Int. Conf. Circuits and Computers, Sept. 1982, pp. 108-111.
[25] C. Svensson, "Signal resynchronization in VLSI system, " Int. VLSI J., vol. 4, pp.75-80, Mar. 1986.
[26] M. S. McGregor, P. B. Denyer, and A. F. Murray, "A single-phase clocking scheme for CMOS VLSI, " in Proc. Stanford Conf. Advanced Research in VLSI, Mar. 1987, pp. 257-271.
[26] M. Hatamian and G. L. Cash, "Parallel bit-level pipelined VLSI designs for high-speed signal processing, " Proc. IEEE, vol.75, pp. 1192-1202, Sept. 1987.
[28] M. Hatamian, L. A. Hornak, T. E. Little, S. T. Tewksbury, and P. Franzon, "Fundamental interconnection issues, " AT&T Tech. J., vol.66, pp. 13-30, July/Aug. 1987.
[29] K. D. Wagner, "Clock system design, " IEEE Des. Test Comput., pp. 9-27, Oct. I988.
[30] A. F. Champernowne, L. B. Bushard, J. T. Rusterholz, and J. R. Schomburg, "Latch-to-latch timing rules, " IEEE Trans. Comput., vol. 39, pp. 798-808, June 1990.
[31] D. G. Messerschmitt, "Synchronization in digital system design, " IEEE J. Select. Areas Commun., vol.8, pp. 1404-1419, Oct. 1990.
[32] M. Afghahi and C. Svensson, "Performance of synchronous and asynchronous schemes
for VLSI systems, " IEEE Trans. Comput., vol.41, pp.858- 872, July 1992.
[33] V. Chi, "Designing salphasic clock distribution systems, " in Proc. Symp. Integrated Systems, Mar.1993, pp.219-233.
[34] V. L. Chi, "Salphasic distribution of clock signals for synchronous systems, " IEEE Trans. Comput., vol.43, pp.597-602, May 1994.
[35] M. C. Papaefthymiou and K. H. Randall, "Edge-triggering vs. twophase level-clocking, " in Proc. Symp. Integrated Systems, Mar. 1993, pp. 201-218.
[36] W. K. C. Lam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Valid clocking in wavepipelined circuits, " in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1992, pp. 124-131.
[37] D. A. Joy and M. J. Ciesielski, "Clock period minimization with wave pipelining, " IEEE Trans. Computer-Aided Design, vol. 12, pp. 461-472, Apr. 1993.
[38] C. T. Gray, W. Liu, and R. K. Cavin Ⅲ, "Timing constraints for wave-pipelined systems, " IEEE Trans. Computer-Aided Design, vol.13, pp. 987-1004, Aug. 1994.
[39] X. Zhang and R. Sridhar, "Synchronization of wave-pipelined circuits, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1994, pp. 164-167.
[40] E. G. Friedman, "Clock distribution design in VLSI circuits—An overview, " in Proc. IEEE Int. Symp. Circuits and Systems, May 1993, pp. 1475-1478.
[41] K. A. Sakallah, T. N. Mudge, T. M. Burks, and E. S. Davidson, "Synchronization of pipelines, " IEEE Trans. Computer-Aided Design, vol.12, pp. 1132-1146, Aug. 1993.
[42] E. G. Friedman, Ed., High Performance Clock Distribution Networks. Norwell, MA: Kluwer, 1997.
[43] J. L. Neves and E. G. Friedman, "Minimizing power dissipation in nonzero skew-based clock distribution networks, " in Proc. IEEE Int. Symp. Circuits and Systems, May 1995, pp. 1576-1579.
[44] A. Vittal and M.Marek-Sadowska, "Power optimal buffered clock tree design, " in Proc. ACM/IEEE Design Automation Conf., June 1995, pp. 497-502.
[45], "Low-power buffered clock tree design, " IEEE Trans. Computer-Aided Design, vol.16, pp.965-975, Sept. 1997.
[46] S. Pullela, N. Menezes, and L. T. Pillage, "Low power IC clock tree design, " in Proc. Custom Integrated Circuits Conf., May 1995, pp.12.4.1-12.4.4.
[47] M. Nekili, Y. Savaria, and G. Bois, "Design of clock distribution networks in presence of process variations, " in Proc. IEEE 8th Great Lakes Symp. VLSI, Feb. 1998.
[48] M. Nekili, G. Bols, and Y. Savaria, "Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations, " IEEE Trans. VLSI Syst., vol.5, pp.161-174, June 1997.
[49] mQ. Zhu and W. W. M. Dai, "High-speed clock network sizing optimization based on
distributed RC and lossy RLC interconnect models, " IEEE Trans. Computer-Aided Design, vol.15, pp. 1106-1118, Sept. 1996.
[50] Y. Ogawa, T. Ishii, Y. Shiraishi, H. Terai, T. Kozawa, K. Yuyama, and K. Chiba, "Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSI's, " in Proc. ACM/IEEE 23rd Design Automation Conf., June 1986, pp.404-410.
[51] S. Boon, S. Butler, R. Byrne, B. Setering, M. Casalanda, and A. Scherf, "High performance clock distribution for CMOS ASICs, " in Proc. IEEE Custom Integrated Circuits Conf., May 1989, pp.15.4.1-15.4.5.
[52] A. Chao, "Clock tree synthesis for largegatearrays, " in High Performance Systems, 1989, p.32.
[2] K. Roy and A. chatterjee, "low-Power VLSI Design, " IEEE Design and Test of Computers, Winter 1994.
[3] L. H. Lee, J. Scott, B. Moyer, and J. Arends, "Low-cost branch folding for embedded applications with small tight loops, "MICRO-32, pp.103-111, Nov.1999.
[4] J. Monteiro, S. Devadas, and A. Ghosh, "Sequential logic optimization for low power using input-disabling precomputation architectures, " IEEE Trans. Computer-Aided Design, vol.17, pp.279-284, Mar.1998.
[5] V. Tiwari, S. Malik, and P. Ashar, "Guarded evaluation: Pushing power management to logic synthesis/design, " IEEE Trans. Computer-Aided Design, vol.17, pp. 1051-1060, Oct. 1998.
[6] W. M. Chung and M. Sachdev, "A comparative analysis of dual edge triggered flip-flops, " in 2000 Canadian Conf. Electrical and Computer Engineering, vol.1, 2000.
[7] A. Dharchoudhuryet al., "Transistor-level sizing and timing verification of domino circuits in the PowerPC microprocessor, " in Proc. IEEE Int. Conf. Computer Design, Oct.1997.
[8] F. Anceau, "A synchronous approach for clocking VLSI systems, " IEEE J. Solid-State Circuits, vol.SC-17, pp. 51-56, Feb. 1982.
[9] M. A. Franklin and D. F. Wann, "Asynchronous and clocked control structures for VLSI based interconnection networks, " in Proc. 9th Annu. Symp. Computer Architecture, Apr. 1982, pp. 50-59.
[10] D. Wann and M. Franklin, "Asynchronous and clocked control structures for VLSI based interconnection networks, " IEEE Trans. Comput., vol. C-32, pp. 284-293, Mar. 1983.
[11] S. Dhar, M. Franklin and D. Wann, "Reduction of clock delays in VLSI structures, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1984, pp. 778-783.
[12] S. Unger and C.-J. Tan, "Optimal clocking schemes for high speed digital systems, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1983, pp. 366-369.
[13] J. Beausang and A. Albicki, "A method to obtain an optimal clocking scheme for a digital system, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1983, pp. 68-72.
[14] S. H. Unger and C.-J. Tan, "Clocking schemes for high-speed digital systems, " IEEE Trans. Comput., vol.C-35, pp. 880-895, Oct. 1986.
[15] D.Noice, R.Mathews, and J. Newkirk, "A clocking discipline for two-phase digital systems, " in Proc. IEEE Int. Conf. Circuits and
Computers, Sept. 1982, pp. 108-111.
[16] C. Svensson, "Signal resynchronization in VLSI system, " Int. VLSI J., vol.4, pp. 75-80, Mar. 1986.
[17] F. Anceau, "A synchronous approach for clocking VLSI systems, " IEEE J. Solid-State Circuits, vol.SC-17, pp.51-56, Feb. 1982.
[18] M. A. Franklin and D. F. Wann, "Asynchronous and clocked control structures for VLSI based interconnection networks, " in Proc. 9th Annu. Symp. Computer Architecture, Apr. 1982, pp.50-59.
[19] D. Warm and M. Franklin, "Asynchronous and clocked control structures for VLSI based interconnection networks, " IEEE Trans. Comput., vol. C-32, pp. 284-293, Mar. 1983.
[20] S. Dhar, M. Franklin, andD. Warm, "Reduction of clock delays in VLSI structures, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1984, pp. 778-783.
[21] S. Unger and C.-J. Tan, "Optimal clocking schemes for high speed digital systems, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1983, pp. 366-369.
[22] J. Beausang and A. Albicki, "A method to obtain an optimal clocking scheme for a digital system, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1983, pp. 68-72.
[23] S. H. Unger and C.-J. Tan, "Clocking schemes for high-speed digital systems, " IEEE Trans. Comput., vol.C-35, pp.880-895, Oct. 1986.
[24] D. Noice, R. Mathews, and J. Newkirk, "A clocking discipline for two-phase digital systems, " in Proc. IEEE Int. Conf. Circuits and Computers, Sept. 1982, pp. 108-111.
[25] C. Svensson, "Signal resynchronization in VLSI system, " Int. VLSI J., vol. 4, pp.75-80, Mar. 1986.
[26] M. S. McGregor, P. B. Denyer, and A. F. Murray, "A single-phase clocking scheme for CMOS VLSI, " in Proc. Stanford Conf. Advanced Research in VLSI, Mar. 1987, pp. 257-271.
[26] M. Hatamian and G. L. Cash, "Parallel bit-level pipelined VLSI designs for high-speed signal processing, " Proc. IEEE, vol.75, pp. 1192-1202, Sept. 1987.
[28] M. Hatamian, L. A. Hornak, T. E. Little, S. T. Tewksbury, and P. Franzon, "Fundamental interconnection issues, " AT&T Tech. J., vol.66, pp. 13-30, July/Aug. 1987.
[29] K. D. Wagner, "Clock system design, " IEEE Des. Test Comput., pp. 9-27, Oct. I988.
[30] A. F. Champernowne, L. B. Bushard, J. T. Rusterholz, and J. R. Schomburg, "Latch-to-latch timing rules, " IEEE Trans. Comput., vol. 39, pp. 798-808, June 1990.
[31] D. G. Messerschmitt, "Synchronization in digital system design, " IEEE J. Select. Areas Commun., vol.8, pp. 1404-1419, Oct. 1990.
[32] M. Afghahi and C. Svensson, "Performance of synchronous and asynchronous schemes
for VLSI systems, " IEEE Trans. Comput., vol.41, pp.858- 872, July 1992.
[33] V. Chi, "Designing salphasic clock distribution systems, " in Proc. Symp. Integrated Systems, Mar.1993, pp.219-233.
[34] V. L. Chi, "Salphasic distribution of clock signals for synchronous systems, " IEEE Trans. Comput., vol.43, pp.597-602, May 1994.
[35] M. C. Papaefthymiou and K. H. Randall, "Edge-triggering vs. twophase level-clocking, " in Proc. Symp. Integrated Systems, Mar. 1993, pp. 201-218.
[36] W. K. C. Lam, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, "Valid clocking in wavepipelined circuits, " in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1992, pp. 124-131.
[37] D. A. Joy and M. J. Ciesielski, "Clock period minimization with wave pipelining, " IEEE Trans. Computer-Aided Design, vol. 12, pp. 461-472, Apr. 1993.
[38] C. T. Gray, W. Liu, and R. K. Cavin Ⅲ, "Timing constraints for wave-pipelined systems, " IEEE Trans. Computer-Aided Design, vol.13, pp. 987-1004, Aug. 1994.
[39] X. Zhang and R. Sridhar, "Synchronization of wave-pipelined circuits, " in Proc. IEEE Int. Conf. Computer Design, Oct. 1994, pp. 164-167.
[40] E. G. Friedman, "Clock distribution design in VLSI circuits—An overview, " in Proc. IEEE Int. Symp. Circuits and Systems, May 1993, pp. 1475-1478.
[41] K. A. Sakallah, T. N. Mudge, T. M. Burks, and E. S. Davidson, "Synchronization of pipelines, " IEEE Trans. Computer-Aided Design, vol.12, pp. 1132-1146, Aug. 1993.
[42] E. G. Friedman, Ed., High Performance Clock Distribution Networks. Norwell, MA: Kluwer, 1997.
[43] J. L. Neves and E. G. Friedman, "Minimizing power dissipation in nonzero skew-based clock distribution networks, " in Proc. IEEE Int. Symp. Circuits and Systems, May 1995, pp. 1576-1579.
[44] A. Vittal and M.Marek-Sadowska, "Power optimal buffered clock tree design, " in Proc. ACM/IEEE Design Automation Conf., June 1995, pp. 497-502.
[45], "Low-power buffered clock tree design, " IEEE Trans. Computer-Aided Design, vol.16, pp.965-975, Sept. 1997.
[46] S. Pullela, N. Menezes, and L. T. Pillage, "Low power IC clock tree design, " in Proc. Custom Integrated Circuits Conf., May 1995, pp.12.4.1-12.4.4.
[47] M. Nekili, Y. Savaria, and G. Bois, "Design of clock distribution networks in presence of process variations, " in Proc. IEEE 8th Great Lakes Symp. VLSI, Feb. 1998.
[48] M. Nekili, G. Bols, and Y. Savaria, "Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations, " IEEE Trans. VLSI Syst., vol.5, pp.161-174, June 1997.
[49] mQ. Zhu and W. W. M. Dai, "High-speed clock network sizing optimization based on
distributed RC and lossy RLC interconnect models, " IEEE Trans. Computer-Aided Design, vol.15, pp. 1106-1118, Sept. 1996.
[50] Y. Ogawa, T. Ishii, Y. Shiraishi, H. Terai, T. Kozawa, K. Yuyama, and K. Chiba, "Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSI's, " in Proc. ACM/IEEE 23rd Design Automation Conf., June 1986, pp.404-410.
[51] S. Boon, S. Butler, R. Byrne, B. Setering, M. Casalanda, and A. Scherf, "High performance clock distribution for CMOS ASICs, " in Proc. IEEE Custom Integrated Circuits Conf., May 1989, pp.15.4.1-15.4.5.
[52] A. Chao, "Clock tree synthesis for largegatearrays, " in High Performance Systems, 1989, p.32.