芯片尺寸封装（CSP）的热应力及热失效分析研究
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摘要
电子器件封装以尺寸最小化和电互连密度最大化为特征，被誉为新一代封装—芯片尺寸封装(CSP)的产生，虽然间距尺寸和体积很小，但也存在一些问题。当前国内外关于芯片尺寸封装的试验研究还很少，基本还处于计算机模拟阶段。
本文首先总结了芯片尺寸封装几种结构类型和常见的失效机理，据此选择一种特定的芯片尺寸封装产品—CSP-SOC，利用ANSYS软件分别建立CSP-SOC有限元2D 1／2截面模型和3D 1／4模型，模拟CSP-SOC封装在标准工业热循环温度—40℃～125℃条件下，并运用APDL程序命令实现周期温度载荷的控制，得到上述温度循环条件下产生的热应力应变情况。然后从材料、设计等方面进行参数分析，同时对2D和3D结果进行线性和非线性分析比较，结合当前已有类似封装参考实验结果作热失效、寿命预测分析，改进并得到一种新的简化寿命预测方程，为今后的高密度封装奠定良好的基础。
研究结果表明封装本身由于各材料之间的热膨胀系数(CTE)不同，会产生热应力和应力集中现象，当强度低于热应力时候就会发生失效。封装整体变形位移最大在PCB板上。对焊球来说，应力应变最大发生在靠近外侧焊球上。对3D模型，由于多考虑了一个方向，发现整体弹性应变最大靠近焊球与基板结合处，填胶应变最小。整体封装应力应变最大发生在芯片边缘区域，靠近环氧树脂填充物和填胶，这也证明了CSP-SOC焊球放四周，避免放置芯片的下面的优点和结构的合理性。从应力应变分布结果和已有类似封装热循环试验对比，结果基本一致。对2D模型，虽不能看出另一方向应力应变，但从变形位移随时间变化图上，清晰的看出焊球最大变化位移随时间在X方向平稳上升，Y方向变化由于温度影响比较明显，出现陡增陡减后，第三个循环后趋于平稳。PCB应力应变在温度变化开始时随时间变化较大，后趋于平稳，这也验证PCB在工作时能为焊球和基板提供良好的支撑作用。
借助以能量为基础的疲劳模型和一种简化模型对焊球和封装整体寿命分析计算，结果对比表明，前者计算过程较复杂，但和后者寿命预测差别不是很大。改进并得到一种简化寿命预测方程，对比分析寿命预测结果和已有类似寿命试验表明，误差在10％，符合要求。
The new generation computers and electronic devices are characterized with minimized package profile and maximum interconnect density. Be praised as the new generation package-chip scale package, with small pitch and little volume, but also exists some problems. The test study on chip scale package is little, also in a computer simulative analysis phase.
The paper firstly summarizes the different types and normal invalidation of chip scale package. Hereby, the paper selects a special CSP product-chip scale package-substrate on chip, using the ANSYS builds the two dimension 1/2 model of cross section and three dimension 1/4 model of whole package, then on the condition of the standard industry thermal cycle temperature-40℃～125℃, combining APDL command language, completing the control of thermal cycle temperature load, simulating the thermal stress and strain of CSP-SOC under the above-mentioned condition. Then completed the parameters analysis from the materials and design, and compared the two dimension and three dimension analysis results, then compare with the precedent test result, analysize the invalidation and life prediction, bring forward a new formula on life prediction, establish a good base for the high density package in future.
The results show that the package, due to different coefficient of thermal expanded(CTE), engenders thermal stress and strain, it will make the package disabled when theintension is low than thermal stress. And the maximum deformed displacement of the wholepackage occurs in PCB. To solder balls, the maximum stress and strain occurs in the outersolder ball. To the three dimension model, additional direction is considered, it is found thatthe maximum elastic strain exists in the interface of the solder balls and PCB, and theminimum strain exsits in the underfill tape, the whole package stress occurs in the edge areaof chip, it is also proved that the solder balls are placed around the chip better than under thechip, it is more reasonable and advanced. Comparing the stress and strain distribution resultswith the similar package test results, it is consistent. For all, the stress and strain isn't reflectedin the 2D model, but from the figure of the deformed displacement opposite to time, we cansee that the maximum displacement on solder joint is increasing along X direction nolinearly,and is fluctuant along Y direction due to suffering from temperature impact but is invariably after three cycle of temperature. The stress variation is bigger along with time in the temperature cycling moment, but it is balanced subsequently. This may say the PCB provides a good sustentation for the solder joint and substrate when is normally Woking.
In virtue of the energy-based fatigue model and a simplified model to calculate the life of solder joint and the whole package respectively. Comparing the result, former model calculating process is complicated, and the two results are consistent. A new simple model is mended and gained, comparing the previous similar test life with the calculated life; the error is 10% only lower than standard deviation.
本文首先总结了芯片尺寸封装几种结构类型和常见的失效机理，据此选择一种特定的芯片尺寸封装产品—CSP-SOC，利用ANSYS软件分别建立CSP-SOC有限元2D 1／2截面模型和3D 1／4模型，模拟CSP-SOC封装在标准工业热循环温度—40℃～125℃条件下，并运用APDL程序命令实现周期温度载荷的控制，得到上述温度循环条件下产生的热应力应变情况。然后从材料、设计等方面进行参数分析，同时对2D和3D结果进行线性和非线性分析比较，结合当前已有类似封装参考实验结果作热失效、寿命预测分析，改进并得到一种新的简化寿命预测方程，为今后的高密度封装奠定良好的基础。
研究结果表明封装本身由于各材料之间的热膨胀系数(CTE)不同，会产生热应力和应力集中现象，当强度低于热应力时候就会发生失效。封装整体变形位移最大在PCB板上。对焊球来说，应力应变最大发生在靠近外侧焊球上。对3D模型，由于多考虑了一个方向，发现整体弹性应变最大靠近焊球与基板结合处，填胶应变最小。整体封装应力应变最大发生在芯片边缘区域，靠近环氧树脂填充物和填胶，这也证明了CSP-SOC焊球放四周，避免放置芯片的下面的优点和结构的合理性。从应力应变分布结果和已有类似封装热循环试验对比，结果基本一致。对2D模型，虽不能看出另一方向应力应变，但从变形位移随时间变化图上，清晰的看出焊球最大变化位移随时间在X方向平稳上升，Y方向变化由于温度影响比较明显，出现陡增陡减后，第三个循环后趋于平稳。PCB应力应变在温度变化开始时随时间变化较大，后趋于平稳，这也验证PCB在工作时能为焊球和基板提供良好的支撑作用。
借助以能量为基础的疲劳模型和一种简化模型对焊球和封装整体寿命分析计算，结果对比表明，前者计算过程较复杂，但和后者寿命预测差别不是很大。改进并得到一种简化寿命预测方程，对比分析寿命预测结果和已有类似寿命试验表明，误差在10％，符合要求。
The new generation computers and electronic devices are characterized with minimized package profile and maximum interconnect density. Be praised as the new generation package-chip scale package, with small pitch and little volume, but also exists some problems. The test study on chip scale package is little, also in a computer simulative analysis phase.
The paper firstly summarizes the different types and normal invalidation of chip scale package. Hereby, the paper selects a special CSP product-chip scale package-substrate on chip, using the ANSYS builds the two dimension 1/2 model of cross section and three dimension 1/4 model of whole package, then on the condition of the standard industry thermal cycle temperature-40℃～125℃, combining APDL command language, completing the control of thermal cycle temperature load, simulating the thermal stress and strain of CSP-SOC under the above-mentioned condition. Then completed the parameters analysis from the materials and design, and compared the two dimension and three dimension analysis results, then compare with the precedent test result, analysize the invalidation and life prediction, bring forward a new formula on life prediction, establish a good base for the high density package in future.
The results show that the package, due to different coefficient of thermal expanded(CTE), engenders thermal stress and strain, it will make the package disabled when theintension is low than thermal stress. And the maximum deformed displacement of the wholepackage occurs in PCB. To solder balls, the maximum stress and strain occurs in the outersolder ball. To the three dimension model, additional direction is considered, it is found thatthe maximum elastic strain exists in the interface of the solder balls and PCB, and theminimum strain exsits in the underfill tape, the whole package stress occurs in the edge areaof chip, it is also proved that the solder balls are placed around the chip better than under thechip, it is more reasonable and advanced. Comparing the stress and strain distribution resultswith the similar package test results, it is consistent. For all, the stress and strain isn't reflectedin the 2D model, but from the figure of the deformed displacement opposite to time, we cansee that the maximum displacement on solder joint is increasing along X direction nolinearly,and is fluctuant along Y direction due to suffering from temperature impact but is invariably after three cycle of temperature. The stress variation is bigger along with time in the temperature cycling moment, but it is balanced subsequently. This may say the PCB provides a good sustentation for the solder joint and substrate when is normally Woking.
In virtue of the energy-based fatigue model and a simplified model to calculate the life of solder joint and the whole package respectively. Comparing the result, former model calculating process is complicated, and the two results are consistent. A new simple model is mended and gained, comparing the previous similar test life with the calculated life; the error is 10% only lower than standard deviation.
引文
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[2] Jurgen Wilde, Elena Zukowski. Probabilistic Analysis of the Influences of Design Parameter on the Reliability of Chip Scale Packages. Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2006: 1-8
[3] 李桂云．微电子封装的发展趋势．电子与封装，2003，3(2)：12-14．
[4] 谢恩恒．新世纪IC封装的回顾和发展趋势展望．电子与封装，2003，3(4)：1-5．
[5] 张增年．微电子产品的可靠性分析．宁夏大学学报(自然科学版)，1998，19(3)：248-249．
[6] Lall, P, Singh, N, Suhling, J.C, Strickland, et al. Thermo-mechanical reliability tradeoffs for deployment of area array packages in harsh environments joints.IEEE Transactions on Components and Packaging Technologies, 2005, 28(3):457-466.
[7] W. Engelmaier, Reliability of leadfree solder joints revisited, Global SMT & Packaging, 2003.
[8] Lau, J.H., Lee, S.W. Microvias for Low Cost, High Density Interconnects. New York: 2001.
[9] 刘于，黄大贵．微电子封装技术的现状及发展．现状·趋势·战略，2002，40(460)：18-20
[10] 李枚．微电子封装技术的发展与展望．半导体技术，2000，25(5)：1-3．
[11] Ikuo Shohjia, Hideo Morib, Yasumitsu Orii et al. Solder joint reliability evaluation of chip scale package using a modified Coffin-Manson equation. Microelectronics Reliability, 2004(44):269-274.
[12] 高尚通．微电子封装与设备．电子与封装，2002，2(6)：1-5．
[13] 杜晓松，杨邦朝．芯片尺寸封装技术．微电子学，2000，30(6)：25-29．
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