摘要
差分跳频通信,又称相关跳频通信,是近几年发展起来的新型通信技术。与
传统跳频技术相比,差分跳频通信系统具有跳速高,传输带宽宽,硬件构成简单
等特点,并在抗干扰、抗衰落能力上显示了突出的优势。
软件无线电是伴随着高速模数转换器件和数字信号处理器的飞速发展而逐
步成熟起来的通信体系,对传统的通信结构提出了挑战,正在渗透到各种通信系
统的设计之中。目前,基于软件无线电技术的短波差分跳频电台正是军事通信研
究的热点,本文将就基于软件无线电技术的差分跳频通信接收机的实现进行深入
的研究,重点对系统的硬件设计和解跳算法进行了论述。
本文以差分跳频通信系统的实现为目的。根据软件无线电的理论,首先设计
了完整的差分跳频通信接收机框图,分析了射频-中频模拟信道,中频处理模块、
数字信号处理主板的硬件设计。文中对采用高速 ADC 器件 AD6644 的中频处理模
块进行了详细的研究,该 ADC 采样率可达 65MHz,精度为 14bit,并提出基于 FFT
的频域分析和基于直方图的统计分析两种方法对中频处理模块的性能进行了论
证,以保证满足系统的设计需要。本文还设计了基于 TMS320C6201 的高速数字信
号处理主板。板上资源包括 SBSRAM、SDRAM、FLASH、双口 RAM 等器件,该主板
可通过扩展槽与中频处理模块相连,并可实现双处理器并行工作。文中还详细分
析了 DSP 中重要寄存器的设置方法。经过最终的调试,该主板不仅能满足现有接
收机的需要,还为将来的功能升级提供了硬件空间。
结合 DSP 主板的设计,本文设计了基于 DSP 的软件解跳算法的程序流程,提
出了一种新型的跳对齐方法,对 FFT 进行了优化,并设计了解跳频图案的方法。
最后,以设计的中频采样子板和 DSP 主板为硬件平台,实现了对中频跳频序列的
解跳运算,并达到了设计的要求。
本课题得到了天津市自然科学基金项目的资助,项目编号:023800111
Differential Frequency Hopping (DFH) is a new type of communication
technique, which growing up in these years. Compared with the conventional
Frequency Hopping technique, DFH can achieve desirable performance feature of
high hopping rate, spectral re-use, multi-path fading mitigation, and interference
resistance, furthermore, DFH system need less hardware, implementing easily.
With the developing of high-speed ADC and ultra-speed DSP , Software Defined
Radio (SDR) based on DSP can be implemented at present, the conventional
communication system frame is challenged. SDR affect the design of new
communication system. Now, research on DFH radio based on SDR is hotspot in
military communication system . This paper will talk more about how to implement
DFH radio receiver based on SDR, focus on the hardware design and demodulation
algorithms.
In this paper , the implementation of DFH system receiver is target. Intermediate
Frequency (IF) sampling digitial scheme is given. Expatiate on the channel from RF
to IF, the IF processing module, and main board design based on DSP. The paper
introduce more about IF processing module based on AD6644, which is up to 65MHz
sampling rate and 14-bit precision. After test of the module by using the methods of
FFT and histogram, the request of ADC module can be meet. The hardware design of
main board based on TMS320C6201 is pivot in this paper, the detail is given,onboard,
including SBSRAM、SDRAM、FLASH、DPRAM and so on. As a daughter board , the
IF processing module can link to main board by slot , Two main board also can link
together for dual-DSP parallel processing. The value of register in DSP is given. The
main board not only fit to the need of this system,but also provide hardware space for
updating in future.
The demodulation optimized algorithms of DFH based on DSP is presented,
introducing a new optional hopping synchronization method, optimizing the FFT
algorithms, and giving a method of demodulate frequency hopping pattern. At last,
using the hadware platform above, dumodulating data stream from IF frequency
hopping sequenc is implemented.
引文
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京,国防工业出版社,2002,4~9
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[5] Ma Yusong,Liu Kaihua, A Design of Differential Frequency Hopping Pattern,
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