基于元构件的FPGA硬件构件设计技术研究
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摘要
随着集成度的提高,芯片内部晶体管数目越来越多,集成电路设计的复杂度越来越高,计算机辅助设计技术愈发变得重要。由于具有硬件基于空域并行处理的特点且可编程,FPGA被广泛应用在不同领域。传统FPGA设计需要经过逻辑综合、映射、装箱和布局布线处理几个阶段,针对不同阶段的设计算法成为研究热点。博士研究课题依托国家863计划信息技术领域重大课题“可重构路由器构件组研制”,针对FPGA硬件构件流水线设计特性以及元构件概念的提出,对基于元构件的FPGA硬件构件设计技术进行了相关研究。论文的主要研究内容和创新工作如下:
(1)针对FPGA设计周期长、开发效率低的问题,在对硬件构件结构进行分析的基础上提炼出具有基本功能的硬件编程程序——元构件,并利用某一具体型号FPGA逻辑单元块网表类型是固定的、可以直接调用的结构特点,将硬件描述语言级元构件进行逻辑综合、映射、装箱后放入元构件库中供硬件构件开发时调用,提出了基于元构件的FPGA设计流程。利用该设计流程可以加速FPGA硬件构件的开发进度。
(2)针对FPGA设计映射阶段现有再综合算法为了保证时序电路关键路径时延不超过设计时钟周期而对路径时延增加的映射方案进行舍弃的问题,利用时序电路中存在的时间裕量消除路径时延增加的影响,通过局部重定时消除寄存器对映射范围的限制,通过全局重定时保证整个时序电路满足时钟周期的要求,提出了一种基于时间裕量参数的时序电路再综合算法。实验结果表明,该算法能在设计时钟周期约束下有效提高映射面积优化能力。
(3)针对FPGA设计装箱阶段现有算法对布通率优化支持有限的问题,从装箱操作过程中相关网线被完全吸收的可行度和对减少被占用端口的贡献度两方面研究出发,构造了布通率驱动函数,并通过吸收关键路径来满足路径时延要求,通过爬山法提高资源利用率,提出了一种基于网线吸收和端口占用分析的FPGA装箱算法。实验结果表明,该算法能有效降低逻辑单元块外部网线数和平均被占用引脚数,从而提高整个电路后续布线布通率。实验同时表明结合时延驱动参数该算法能更有效地降低装箱后电路关键路径时延。
(4)针对FPGA设计布局阶段现有模拟退火算法中以各自布局关键路径时延为基础衡量布局质量的时延代价计算在一定条件下并不能准确反映实际布局变化情况的问题,证明了以统一关键路径时延为基准进行计算的时延代价在任何情况下都可与布局变化情况相匹配,通过引入惩罚系数有效降低关键路径时延增加布局方案被接受的概率,并根据惩罚系数对关键路径时延收敛效果的影响制定基准值设置标准,验证模拟退火过程在每次温度标准下设置一致的关键路径时延基准是有效的,提出了一种以统一关键路径时延为基准FPGA模拟退火布局算法。实验结果表明,该算法能在线性拥挤代价增加有限的情况下有效降低关键路径时延。
(5)针对模拟退火算法搜索空间大、运行时间长、不适应大规模电路布局的问题,利用元构件内部逻辑单元块之间联系紧密、在理想情况下往往布局在相邻位置的特点,提出了基于元构件的二次布局方案。元构件初始布局利用解析法进行元构件间以及元构件和端口间线长优化,通过保证元构件布局区域边长平衡进行布通率优化。元构件内部逻辑单元块再次布局则利用较好初始布局质量通过设置较低的模拟退火初始温度和移动范围加快逻辑单元块模拟退火布局进程。实验结果表明,二次布局算法能在保障布局质量的前提下有效降低运行时间。
With the improvement of integration, the number of transistors inside the chip is increasing. As the design's complexity of integrated circuit is getting higher and higher, computer aided design technology has become increasingly important. Due to the hardware parallel processing based on spatial characteristics and programmable, FPGA has been widely used in different areas. Traditionally FPGA design needs to go through logic synthesis, mapping, packing, placement and routing processing stages, and the algorithms for different stages of design flow become research focus. Combined with the research of the National High-Tech Research and Development Program of China (863 program)“Research of Reconfigurable Router and its Components”in information technology field, this dissertation mainly studies the design technology in view of meta-component and pipe line design characteristic of FPGA hardware component. The main works and contributions in this paper are outlined as follows:
As FPGA design cycle is long, in order to accelerate FPGA hardware component development progress, a new FPGA development flow is proposed. Meta-components are extracted based on hardware component structure analysing. As the block level netlist format of a specific type of FPGA is fixed, which can used directly, the hardware description language level netlist of meta-component can be transformed into block level netlist by carrying on logic synthesis, mapping and packing in advance, which can be called from its library directly in hardware component designing.
In order to guarantee that the Critical Path Delay (CPD) of sequential circuits shall not exceed design clock cycle, the re-synthesis algorithm in technology mapping step discards all the mapping process which increases path delay. A sequential re-synthesis algorithm based on slack parameters is proposed. The increasing delay is compensated by slack, restriction on the scope of the mapping is broken by local retiming and the requirement of clock cycle is guaranteed by global retiming. Experimental results show that the proposed algorithm can improve the efficiency of area optimization of re-synthesis algorithm under the restriction of design clock cycle.
In order to improve routability in FPGA design packing step, a packing algorithm based on analysis of wire absorption and port occupancy is proposed. A routability driven function is defined based on analysis of influence of packing on wire absorption and port occupancy. Path delay requirements are ensured by absorbing critical paths and area-efficiency is improved by hill-climbing. Experimental results show that by absorbing more wires and decreasing occupying ports, the proposed algorithm can improve routability efficiently. In addition, the CPD also can be decreased by integrating delay driven parameter.
In traditional simulated annealing algorithm in FPGA design placement step, the timing quality of one layout is measured by timing cost which is calculated based on its CPD. In some circumstances, the timing cost and the layout transformation does not match. A simulated annealing FPGA placement algorithm based on unified CPD is proposed which proves that the timing cost calculated based on unified CPD can match layout transformation in all circumstances, the probability of accepting a move which exceeding CPD is reduced by introducing punishment factor, benchmark standard of punishment factor is setting according to impact on convergence of CPD. Experimental results show that the proposed algorithm can decrease CPD effectively.
As the searching space is large, simulated annealing needs more operation time and does not adapt to large-scale circuit’s placement. A twice placement scheme is proposed according to the characteristics that the internal logic unit blocks in meta-component are closely related and ideally layout in adjacent position. A region distribution technology for meta-component initial placement is proposed. This technology first carries on wire optimization by using quadratic method, and then carries on routability optimization by partitioning meta-component set in a way which ensures balanced length-width ratio of distributed region for meta-component. As to block placement in distributed area for meta-components, the simulated annealing layout process can be accelerated by setting a lower annealing temperature and a smaller moving range. Experimental results show that the proposed twice placement scheme is effective.
(1)针对FPGA设计周期长、开发效率低的问题,在对硬件构件结构进行分析的基础上提炼出具有基本功能的硬件编程程序——元构件,并利用某一具体型号FPGA逻辑单元块网表类型是固定的、可以直接调用的结构特点,将硬件描述语言级元构件进行逻辑综合、映射、装箱后放入元构件库中供硬件构件开发时调用,提出了基于元构件的FPGA设计流程。利用该设计流程可以加速FPGA硬件构件的开发进度。
(2)针对FPGA设计映射阶段现有再综合算法为了保证时序电路关键路径时延不超过设计时钟周期而对路径时延增加的映射方案进行舍弃的问题,利用时序电路中存在的时间裕量消除路径时延增加的影响,通过局部重定时消除寄存器对映射范围的限制,通过全局重定时保证整个时序电路满足时钟周期的要求,提出了一种基于时间裕量参数的时序电路再综合算法。实验结果表明,该算法能在设计时钟周期约束下有效提高映射面积优化能力。
(3)针对FPGA设计装箱阶段现有算法对布通率优化支持有限的问题,从装箱操作过程中相关网线被完全吸收的可行度和对减少被占用端口的贡献度两方面研究出发,构造了布通率驱动函数,并通过吸收关键路径来满足路径时延要求,通过爬山法提高资源利用率,提出了一种基于网线吸收和端口占用分析的FPGA装箱算法。实验结果表明,该算法能有效降低逻辑单元块外部网线数和平均被占用引脚数,从而提高整个电路后续布线布通率。实验同时表明结合时延驱动参数该算法能更有效地降低装箱后电路关键路径时延。
(4)针对FPGA设计布局阶段现有模拟退火算法中以各自布局关键路径时延为基础衡量布局质量的时延代价计算在一定条件下并不能准确反映实际布局变化情况的问题,证明了以统一关键路径时延为基准进行计算的时延代价在任何情况下都可与布局变化情况相匹配,通过引入惩罚系数有效降低关键路径时延增加布局方案被接受的概率,并根据惩罚系数对关键路径时延收敛效果的影响制定基准值设置标准,验证模拟退火过程在每次温度标准下设置一致的关键路径时延基准是有效的,提出了一种以统一关键路径时延为基准FPGA模拟退火布局算法。实验结果表明,该算法能在线性拥挤代价增加有限的情况下有效降低关键路径时延。
(5)针对模拟退火算法搜索空间大、运行时间长、不适应大规模电路布局的问题,利用元构件内部逻辑单元块之间联系紧密、在理想情况下往往布局在相邻位置的特点,提出了基于元构件的二次布局方案。元构件初始布局利用解析法进行元构件间以及元构件和端口间线长优化,通过保证元构件布局区域边长平衡进行布通率优化。元构件内部逻辑单元块再次布局则利用较好初始布局质量通过设置较低的模拟退火初始温度和移动范围加快逻辑单元块模拟退火布局进程。实验结果表明,二次布局算法能在保障布局质量的前提下有效降低运行时间。
With the improvement of integration, the number of transistors inside the chip is increasing. As the design's complexity of integrated circuit is getting higher and higher, computer aided design technology has become increasingly important. Due to the hardware parallel processing based on spatial characteristics and programmable, FPGA has been widely used in different areas. Traditionally FPGA design needs to go through logic synthesis, mapping, packing, placement and routing processing stages, and the algorithms for different stages of design flow become research focus. Combined with the research of the National High-Tech Research and Development Program of China (863 program)“Research of Reconfigurable Router and its Components”in information technology field, this dissertation mainly studies the design technology in view of meta-component and pipe line design characteristic of FPGA hardware component. The main works and contributions in this paper are outlined as follows:
As FPGA design cycle is long, in order to accelerate FPGA hardware component development progress, a new FPGA development flow is proposed. Meta-components are extracted based on hardware component structure analysing. As the block level netlist format of a specific type of FPGA is fixed, which can used directly, the hardware description language level netlist of meta-component can be transformed into block level netlist by carrying on logic synthesis, mapping and packing in advance, which can be called from its library directly in hardware component designing.
In order to guarantee that the Critical Path Delay (CPD) of sequential circuits shall not exceed design clock cycle, the re-synthesis algorithm in technology mapping step discards all the mapping process which increases path delay. A sequential re-synthesis algorithm based on slack parameters is proposed. The increasing delay is compensated by slack, restriction on the scope of the mapping is broken by local retiming and the requirement of clock cycle is guaranteed by global retiming. Experimental results show that the proposed algorithm can improve the efficiency of area optimization of re-synthesis algorithm under the restriction of design clock cycle.
In order to improve routability in FPGA design packing step, a packing algorithm based on analysis of wire absorption and port occupancy is proposed. A routability driven function is defined based on analysis of influence of packing on wire absorption and port occupancy. Path delay requirements are ensured by absorbing critical paths and area-efficiency is improved by hill-climbing. Experimental results show that by absorbing more wires and decreasing occupying ports, the proposed algorithm can improve routability efficiently. In addition, the CPD also can be decreased by integrating delay driven parameter.
In traditional simulated annealing algorithm in FPGA design placement step, the timing quality of one layout is measured by timing cost which is calculated based on its CPD. In some circumstances, the timing cost and the layout transformation does not match. A simulated annealing FPGA placement algorithm based on unified CPD is proposed which proves that the timing cost calculated based on unified CPD can match layout transformation in all circumstances, the probability of accepting a move which exceeding CPD is reduced by introducing punishment factor, benchmark standard of punishment factor is setting according to impact on convergence of CPD. Experimental results show that the proposed algorithm can decrease CPD effectively.
As the searching space is large, simulated annealing needs more operation time and does not adapt to large-scale circuit’s placement. A twice placement scheme is proposed according to the characteristics that the internal logic unit blocks in meta-component are closely related and ideally layout in adjacent position. A region distribution technology for meta-component initial placement is proposed. This technology first carries on wire optimization by using quadratic method, and then carries on routability optimization by partitioning meta-component set in a way which ensures balanced length-width ratio of distributed region for meta-component. As to block placement in distributed area for meta-components, the simulated annealing layout process can be accelerated by setting a lower annealing temperature and a smaller moving range. Experimental results show that the proposed twice placement scheme is effective.
引文
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