基于CMOS工艺的射频功率放大器的设计
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摘要
这篇论文以射频发射机末端的功率放大器为研究对象,根据无线局域网的802.11a标准,应用Agilent公司的ADS电路仿真软件,进行功率放大器的设计与模拟。
首先,在系统分析功率放大器的结构、设计原理、性能指标的基础上,根据功率放大器的应用背景,选择A类放大器进行设计。设计时综合多种因素,合理选用共源共栅结构和共源结构的三级差分放大电路,进行增益和输出功率分配,然后应用ADS软件进行设计、优化和仿真。仿真结果为:在1.8V的电源电压条件下,输出功率Pout在P1dB点为21.7dBm,输出饱和功率大约为23.5dBm,在5.2GHz处,正向传输系数S21达到25.4dB,输出三阶互调量为29.5dBm。功率增加效率PAE最大为29%,静态工作电流为810mA。输出结果表明,设计的功率放大器在其工作频率范围绝对稳定,实现了很好的输入输出匹配,具有较好的线性度和隔离度,最终的仿真结果满足802.11a标准。
其次,针对三级放大器级数多、效率较低、集成度不高的缺点,提出了一种改进的二级功率放大器的设计,改进的措施主要包括设计无源螺旋形电感、合理运用Cascode电感接入、改进偏置电路的设计。仿真结果为:P1dB点的Pout为18dBm,输入输出匹配的情况下,功率增益为30dB,1dB压缩点的PAE为16%,输出三阶交调点IP3是26.8dBm,静态工作电流为252mA。结果表明,改进的功率放大器各项性能指标达到设计要求。
最后进行功率放大器的版图设计。根据深亚微米CMOS工艺的特点,将已设计和仿真好的功率放大器,采用TSMC 0.18μm CMOS工艺元件库,应用Cadence软件画出版图。上述工作对射频电路的设计有一定的参考价值。
This paper presents the design of Power Amplifer,the key component in the end of RF transmitter.According to the Wireless LAN 802.11a standard,the Power Amplifier is designed and simulated with the ADS circuit simulation software of Agilent.
First of all,on the basis of analyzing power amplifier's structure,design principle and performance,according to the application of power amplifier background,select the Class A amplifier to design.By applying synthesizing a number of factors,select third-stage differential amplifier of cascode structure and co-source structure reasonably,to distribute gain and output power.Then use ADS software to design,optimize and simulate.The simulation results are:under the conditions of 1.8 V supply voltage,the output power Pout is up to 21.7 dBm at P1dB compression point,saturated power output is about 23.5 dBm.at 5.2 GHz.positive transmission coefficient S21 reaches 25.4 dB,the output point of third-stage intermodulation is about 29.5 dBm.The Power-Added Efficiency PAE is about 29%at saturation point.Static work current is about 810 mA.The output results show that the power amplifier in the frequency range has absolute stability,reaches a very good input and output match,obtains good linearity and isolation,the ultimate simulation results meet 802.(?)a standard.
Secondly,aim to low efficiency,low integration and more stages of the third-stage Power Amplifier,a second-stage Power Amplifier is bring forward to ameliorate these shortcomings,The measurements includes the design of passive spiral inductor,rational use of Cascode inductors,improving the bias circuit design.The simulation results are:the output power Pout is 18 dBm in P1dB point,in the condition of input and output match,the power gain is 30 dB at 5.2 GHz,the PAE at 1dB compression point is 16%,the output of IP3 is 26.8 dBm,the total static work current is about 252 mA.These results indicate that the performance of improved Power Amplifier meets the design requirements.
Finally,execute the design of layout.According to the characteristics of CMOS technology in Deep Submicron,by using TSMC 0.18μm CMOS technology library and Cadence software,draw the layout of the Power Amplifier circuits that have been completing design and simulation.These above jobs have certain value to the work of the RF circuit design.
首先,在系统分析功率放大器的结构、设计原理、性能指标的基础上,根据功率放大器的应用背景,选择A类放大器进行设计。设计时综合多种因素,合理选用共源共栅结构和共源结构的三级差分放大电路,进行增益和输出功率分配,然后应用ADS软件进行设计、优化和仿真。仿真结果为:在1.8V的电源电压条件下,输出功率Pout在P1dB点为21.7dBm,输出饱和功率大约为23.5dBm,在5.2GHz处,正向传输系数S21达到25.4dB,输出三阶互调量为29.5dBm。功率增加效率PAE最大为29%,静态工作电流为810mA。输出结果表明,设计的功率放大器在其工作频率范围绝对稳定,实现了很好的输入输出匹配,具有较好的线性度和隔离度,最终的仿真结果满足802.11a标准。
其次,针对三级放大器级数多、效率较低、集成度不高的缺点,提出了一种改进的二级功率放大器的设计,改进的措施主要包括设计无源螺旋形电感、合理运用Cascode电感接入、改进偏置电路的设计。仿真结果为:P1dB点的Pout为18dBm,输入输出匹配的情况下,功率增益为30dB,1dB压缩点的PAE为16%,输出三阶交调点IP3是26.8dBm,静态工作电流为252mA。结果表明,改进的功率放大器各项性能指标达到设计要求。
最后进行功率放大器的版图设计。根据深亚微米CMOS工艺的特点,将已设计和仿真好的功率放大器,采用TSMC 0.18μm CMOS工艺元件库,应用Cadence软件画出版图。上述工作对射频电路的设计有一定的参考价值。
This paper presents the design of Power Amplifer,the key component in the end of RF transmitter.According to the Wireless LAN 802.11a standard,the Power Amplifier is designed and simulated with the ADS circuit simulation software of Agilent.
First of all,on the basis of analyzing power amplifier's structure,design principle and performance,according to the application of power amplifier background,select the Class A amplifier to design.By applying synthesizing a number of factors,select third-stage differential amplifier of cascode structure and co-source structure reasonably,to distribute gain and output power.Then use ADS software to design,optimize and simulate.The simulation results are:under the conditions of 1.8 V supply voltage,the output power Pout is up to 21.7 dBm at P1dB compression point,saturated power output is about 23.5 dBm.at 5.2 GHz.positive transmission coefficient S21 reaches 25.4 dB,the output point of third-stage intermodulation is about 29.5 dBm.The Power-Added Efficiency PAE is about 29%at saturation point.Static work current is about 810 mA.The output results show that the power amplifier in the frequency range has absolute stability,reaches a very good input and output match,obtains good linearity and isolation,the ultimate simulation results meet 802.(?)a standard.
Secondly,aim to low efficiency,low integration and more stages of the third-stage Power Amplifier,a second-stage Power Amplifier is bring forward to ameliorate these shortcomings,The measurements includes the design of passive spiral inductor,rational use of Cascode inductors,improving the bias circuit design.The simulation results are:the output power Pout is 18 dBm in P1dB point,in the condition of input and output match,the power gain is 30 dB at 5.2 GHz,the PAE at 1dB compression point is 16%,the output of IP3 is 26.8 dBm,the total static work current is about 252 mA.These results indicate that the performance of improved Power Amplifier meets the design requirements.
Finally,execute the design of layout.According to the characteristics of CMOS technology in Deep Submicron,by using TSMC 0.18μm CMOS technology library and Cadence software,draw the layout of the Power Amplifier circuits that have been completing design and simulation.These above jobs have certain value to the work of the RF circuit design.
引文
[1]池保勇,余志平,石秉学.CMOS射频集成电路分析与设计[M].北京:清华大学出版社,2006
[2]王家忠.无线通信功率放大器发展趋势[J].电子产品世界.2004.(1):35-39
[3]支传德,杨华中,汪蕙.CMOS射频功率放大器的设计方法[J].电子技术应用.2006.(9):1-3
[4]张国艳,黄如,张兴等.CMOS射频集成电路的研究进展[J].微电子学.2004.34(8):377-384
[5]Keerti,A.Pham.SiGe power devices for 802.11a WLAN applications at 5 GHz.Electronics Letters[J].2003.39(16)
[6]Gang liu.tsu-jae king liu,all m.niknejad.A 1.2V,24.VGHZ Fully Integrated Linear CMOS Power Amplifier With Efficiency Enhancement[J].IEEE 2006 Custom Integrated Circuits Conference.2006.7:141-144
[7]A.Komijani.A.Hajimiri.A 24 GHz,14.5 dBm fully integrated Power Amplifier in 0.18μm CMOS[J].IEEE Custom Integrated Circuits Conf.2004.(10):561-564
[8]Yun Seong Eo,Kwang Du Lee.A Fully Integrated 24dBm CMOS Power Amplifier for 802.11 a WLAN Applications[J].IEEE Microwave and Wireless Components Letters.2004.14(11):1-3
[9]J.L.Dawson,T.H.Lee.Automatic phase alignment for a fully integrated Cartesian feedback power amplifier system[J].IEEE Journal of Solid-State Circuits.2003.38(12):2269-2279
[10]I.Aoki,S.Kee,D.B.Rutledge etc.Fully integrated CMOS power amplifier design using the Distributive Active-Transformer architecture[J].IEEE Solid-State Circuits.2002.37(3):371-383
[11]Weimin Zhang,Ee-Sze Khoo,Terry Tear.A Low Voltage Fully-Integrated 0.18um CMOS Power Amplifier for 5GHz WLAN[J].2002 proc.of the 28~(th)European Solid-State Circuits Conf.2002.(9):215-217
[12]Hector Solar,Roc Berenguer,Unai Alvarado etc.A Fully Integrated 26.5 dBm CMOS Power Amplifier for IEEE 802.11a WLAN Standard with on-chip "power inductor"[J].IEEE.2006:1875-1878
[13]Tirdad Sowlati,Domine Leenaerts.A 2.4GHz 0.18 um CMOS Self-Biased Cascode Power Amplifier with 23dBm Output Power.ISSCC 2002:294-295
[14]Kenichi Okada,Hiroaki Hoshino,Hidetoshi Onodera.Modeling and Optimization of On-Chip Spiral Inductor in S-parameter Domain[J].ISCAS.2004:154-156
[15]C.Patrick Yue,and S.Simon Wong.On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's[J].IEEE JOURNAL OF SOLID-STATE CIRCUITS.1998.33(5):743-753
[16]Kenichi Okada,Hiroaki Hoshino,Hidetoshi Onodera.Modeling and Optimization of On-Chip Spiral Inductor in S-parameter Domain[J].ISCAS.2004:154-156
[17]N.Wongkomet,L.Tee,P.Gray.A 1.7GHz 1.5W CMOS RF Doherty Power Amplifier for Wireless Communications[J].IEEE ISSCC Digest of Technical Papers.2006(2):486-487
[18]F.H.Raab,P.Asbeck,S.Cripps etc.Power Amplifiers and Transmitters for RF and Microwave[J].IEEE Transactions on MTT.2002.50(3):814-826
[19]S.Zhang,J.Madic,P.Bretchko etc.A novel power-amplifier module for quad-band wireless handset applications[J].IEEE Trans Microwave Theory Tech.2003.51(11):2203-2210
[20]Mark Ciampa.无线局域网设计与实现[M].北京科学出版社.2003
[21]B.Razavi.A 2.4-GHZ 0.25-μm CMOS Dual-Mode Direct-Convers(?)Transceiver for Bluetooth and 802.11b[J].IEEE JOURNAL OF SOLID-STATE CIRCUITS.1999.34(10):1382-1385
[22]B.Razavi.A 2.4-GHZ CMOS receiver for IEEE 802.11 wireless LANS[J].IEEE JOURNAL OF SOLID-STATE CIRCUITS.1999.34(10):1382-1385
[23]Masoud Zargari,David K.Su,C.Patrick Yue etc.A 5GHz CMOS transceiver for IEEE 802.11aWLAN Systems[J].IEEE Solid-State Circuits.2002.37(12):1-3
[24]赵博.功率放大器中负载阻抗的确定[J].平原大学学报.2001.18(2):45-46
[25]Mona M.Hella,Mohammed Ismail.RF CMOS Power Amplifiers[J].Mohammed Ismail.Ohio State University.2002
[26]阿地力.依米提,刘吉超.关于提高功率放大器效率问题的探讨[J].自然科学版.2005.24(6):47-51
[27]陈建新,谢万波,杨维明等.射频放大器前馈技术仿真[J].北京工业大学学报.2006.32(10):870-874
[28]李军.射频功率放大器的线性化技术[J].世界电子元器件.2003.(7):37-38
[29]孙玲.高效率射频功率放大器线性化技术的比较研究[J].南通大学学院学报.2002.(3)
[30]龚剑,张祖荫,郭伟.射频功率放大器模块的设计与实现[J].计算机和数字工程 2006.36(11):81-183
[31]Peter wager,Winfried Bakalski,Andrif V.Vasylyev.17-GHZ 50-60 mw Power Amplifiers in 0.13μm Standard CMOS[J].IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS.2006.16(1):37-39
[32]毕查德.拉扎维.模拟CMOS集成电路设计[M].第一版.西安:西安交通大学出版社.2003
[33]吕剑锋,孙虹.射频功率放大器的稳定性分析[J].国外电子测量技术.2005.121(3):11-14
[34]GEIS LA,DUNLEAVY LP.Power Contours Plots Using Linear Simulator[J].Microwave J,1996.(6):60-70
[35]杨贤松.用ADS进行宽带微波功放的仿真设计[J].通信对抗.2006.(1):55-57
[36]TSMC.TSMC 0.18UM MIXED SIGNAL 1P6MSAMCIDE 1.8V/3.3V RF SPICE MODELS.REV1.1.TSMC:11-18-02
[37]Guillenno Gonzalez.微波晶体管放大器分析与设计[M].第二版.北京:清华大学出版社,2003
[38]王燕.CMOS射频集成电路功率放大器设计[D].哈尔滨工业大学硕士学位论文.2006
[39]施超,庄奕琪.CMOS射频集成电路中器件模型的研究[J].微电子学.2002.32(6):405-408
[40]Jongchan Kang,Daekyu Yu,Youngoo Yang etc.Highly Linear 0.18μm CMOS Power Amplifier With Deep n-Well Structure[J].IEEE Journey of Solid-State Circuit.2006.(5):1073-1079
[41]CADENCE.Layout Editor Training Manual[M].Version 4.3.2.Educational Services Group.1994
[42]Alan Hastings.模拟电路版图的艺术[M].第二版.电子工业出版社,2007
[43]R.Thueringer,M.Tiebout,W.Simbuerger etc.A 36 GHz linear 50output driver in 0.12μm standard CMOS[J].IEEE Radio Frequency Integrated Circuits(RFIC)Symp.2003.(7):207-210
[44]罗品贵,赵亚东.高效率线性RF功放的研究与设计[J].电讯技术.2004.(5):124-127
[2]王家忠.无线通信功率放大器发展趋势[J].电子产品世界.2004.(1):35-39
[3]支传德,杨华中,汪蕙.CMOS射频功率放大器的设计方法[J].电子技术应用.2006.(9):1-3
[4]张国艳,黄如,张兴等.CMOS射频集成电路的研究进展[J].微电子学.2004.34(8):377-384
[5]Keerti,A.Pham.SiGe power devices for 802.11a WLAN applications at 5 GHz.Electronics Letters[J].2003.39(16)
[6]Gang liu.tsu-jae king liu,all m.niknejad.A 1.2V,24.VGHZ Fully Integrated Linear CMOS Power Amplifier With Efficiency Enhancement[J].IEEE 2006 Custom Integrated Circuits Conference.2006.7:141-144
[7]A.Komijani.A.Hajimiri.A 24 GHz,14.5 dBm fully integrated Power Amplifier in 0.18μm CMOS[J].IEEE Custom Integrated Circuits Conf.2004.(10):561-564
[8]Yun Seong Eo,Kwang Du Lee.A Fully Integrated 24dBm CMOS Power Amplifier for 802.11 a WLAN Applications[J].IEEE Microwave and Wireless Components Letters.2004.14(11):1-3
[9]J.L.Dawson,T.H.Lee.Automatic phase alignment for a fully integrated Cartesian feedback power amplifier system[J].IEEE Journal of Solid-State Circuits.2003.38(12):2269-2279
[10]I.Aoki,S.Kee,D.B.Rutledge etc.Fully integrated CMOS power amplifier design using the Distributive Active-Transformer architecture[J].IEEE Solid-State Circuits.2002.37(3):371-383
[11]Weimin Zhang,Ee-Sze Khoo,Terry Tear.A Low Voltage Fully-Integrated 0.18um CMOS Power Amplifier for 5GHz WLAN[J].2002 proc.of the 28~(th)European Solid-State Circuits Conf.2002.(9):215-217
[12]Hector Solar,Roc Berenguer,Unai Alvarado etc.A Fully Integrated 26.5 dBm CMOS Power Amplifier for IEEE 802.11a WLAN Standard with on-chip "power inductor"[J].IEEE.2006:1875-1878
[13]Tirdad Sowlati,Domine Leenaerts.A 2.4GHz 0.18 um CMOS Self-Biased Cascode Power Amplifier with 23dBm Output Power.ISSCC 2002:294-295
[14]Kenichi Okada,Hiroaki Hoshino,Hidetoshi Onodera.Modeling and Optimization of On-Chip Spiral Inductor in S-parameter Domain[J].ISCAS.2004:154-156
[15]C.Patrick Yue,and S.Simon Wong.On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's[J].IEEE JOURNAL OF SOLID-STATE CIRCUITS.1998.33(5):743-753
[16]Kenichi Okada,Hiroaki Hoshino,Hidetoshi Onodera.Modeling and Optimization of On-Chip Spiral Inductor in S-parameter Domain[J].ISCAS.2004:154-156
[17]N.Wongkomet,L.Tee,P.Gray.A 1.7GHz 1.5W CMOS RF Doherty Power Amplifier for Wireless Communications[J].IEEE ISSCC Digest of Technical Papers.2006(2):486-487
[18]F.H.Raab,P.Asbeck,S.Cripps etc.Power Amplifiers and Transmitters for RF and Microwave[J].IEEE Transactions on MTT.2002.50(3):814-826
[19]S.Zhang,J.Madic,P.Bretchko etc.A novel power-amplifier module for quad-band wireless handset applications[J].IEEE Trans Microwave Theory Tech.2003.51(11):2203-2210
[20]Mark Ciampa.无线局域网设计与实现[M].北京科学出版社.2003
[21]B.Razavi.A 2.4-GHZ 0.25-μm CMOS Dual-Mode Direct-Convers(?)Transceiver for Bluetooth and 802.11b[J].IEEE JOURNAL OF SOLID-STATE CIRCUITS.1999.34(10):1382-1385
[22]B.Razavi.A 2.4-GHZ CMOS receiver for IEEE 802.11 wireless LANS[J].IEEE JOURNAL OF SOLID-STATE CIRCUITS.1999.34(10):1382-1385
[23]Masoud Zargari,David K.Su,C.Patrick Yue etc.A 5GHz CMOS transceiver for IEEE 802.11aWLAN Systems[J].IEEE Solid-State Circuits.2002.37(12):1-3
[24]赵博.功率放大器中负载阻抗的确定[J].平原大学学报.2001.18(2):45-46
[25]Mona M.Hella,Mohammed Ismail.RF CMOS Power Amplifiers[J].Mohammed Ismail.Ohio State University.2002
[26]阿地力.依米提,刘吉超.关于提高功率放大器效率问题的探讨[J].自然科学版.2005.24(6):47-51
[27]陈建新,谢万波,杨维明等.射频放大器前馈技术仿真[J].北京工业大学学报.2006.32(10):870-874
[28]李军.射频功率放大器的线性化技术[J].世界电子元器件.2003.(7):37-38
[29]孙玲.高效率射频功率放大器线性化技术的比较研究[J].南通大学学院学报.2002.(3)
[30]龚剑,张祖荫,郭伟.射频功率放大器模块的设计与实现[J].计算机和数字工程 2006.36(11):81-183
[31]Peter wager,Winfried Bakalski,Andrif V.Vasylyev.17-GHZ 50-60 mw Power Amplifiers in 0.13μm Standard CMOS[J].IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS.2006.16(1):37-39
[32]毕查德.拉扎维.模拟CMOS集成电路设计[M].第一版.西安:西安交通大学出版社.2003
[33]吕剑锋,孙虹.射频功率放大器的稳定性分析[J].国外电子测量技术.2005.121(3):11-14
[34]GEIS LA,DUNLEAVY LP.Power Contours Plots Using Linear Simulator[J].Microwave J,1996.(6):60-70
[35]杨贤松.用ADS进行宽带微波功放的仿真设计[J].通信对抗.2006.(1):55-57
[36]TSMC.TSMC 0.18UM MIXED SIGNAL 1P6MSAMCIDE 1.8V/3.3V RF SPICE MODELS.REV1.1.TSMC:11-18-02
[37]Guillenno Gonzalez.微波晶体管放大器分析与设计[M].第二版.北京:清华大学出版社,2003
[38]王燕.CMOS射频集成电路功率放大器设计[D].哈尔滨工业大学硕士学位论文.2006
[39]施超,庄奕琪.CMOS射频集成电路中器件模型的研究[J].微电子学.2002.32(6):405-408
[40]Jongchan Kang,Daekyu Yu,Youngoo Yang etc.Highly Linear 0.18μm CMOS Power Amplifier With Deep n-Well Structure[J].IEEE Journey of Solid-State Circuit.2006.(5):1073-1079
[41]CADENCE.Layout Editor Training Manual[M].Version 4.3.2.Educational Services Group.1994
[42]Alan Hastings.模拟电路版图的艺术[M].第二版.电子工业出版社,2007
[43]R.Thueringer,M.Tiebout,W.Simbuerger etc.A 36 GHz linear 50output driver in 0.12μm standard CMOS[J].IEEE Radio Frequency Integrated Circuits(RFIC)Symp.2003.(7):207-210
[44]罗品贵,赵亚东.高效率线性RF功放的研究与设计[J].电讯技术.2004.(5):124-127