一种12位流水线结构模数转换器的设计
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摘要
随着电路系统数字化程度不断提高，模数转换器作为模拟信号与数字信号的接口电路，其作用也越来要重要，本文给出了一种流水线结构模数转换器的设计方案，对流水线结构原理进行了较为细致的分析介绍，论文从整体电路结构到具体电路的设计实现方面都作了许多工作。本次论文目标是设计最高采样时钟频率50M，转换精度为12位流水线型模数转换器，设计中采用了十级流水线模式的结构：第一级四位flash子模数转换器，后面为八级每级1.5位再加一位flash子模数转换器的流水线结构，子模块电路设计中我们完成了高精度的采样保持电路、高增益带宽积的运算跨导放大器电路、低失调电压低功耗高速度比较器电路、1.5位结构子模数转换电路以及数字校正电路、时钟产生以及稳定电路、基准电压产生和缓冲驱动电路以及参考电流源电路的设计．
本次设计采用上华0.5um DPDM CMOS工艺试流片，应用Cadence Spectre仿真工具对电路仿真表明设计可以达到十二位精度要求，最高采样速率达到50Msample／s，测试结果静态参数指标达到了设计要求．本电路可以应用在音频，视频设备、通讯接收器的中频采样等领域。
As an interface circuit of analog signal and digital signal, Analog to digital converters get more and more important with the digitalize of circuit system. This thesis submitted a design of 12 bit pipeline analog to digital converter. We did much work in the system architecture design and the transistor level module circuit design. The purpose of this thesis is design a 50Msample/s 12 bit resolution pipeline ADC . A ten stage pipelined architecture was used in this design .The first stage is an 4 bit flash sub ADC, followed by eight stages 1. 5 bit per stage sub ADC and an 1 bit flash ADC. These ten stages formed the ADC core. We accomplished the sub module circuits design, such as high resolution sample and hold circuit, high gain wide bandwidth operational transconductance amplifier ,low offset voltage、low power, high speed comparator, 1.5 bit per stage sub ADC, digital correction circuit, clock stabilization and generation circuit , the trasistor level band gap reference voltage with output buffers and current source reference circuit.
This design was tape out based on CSMC 0.5um 2P2M CMOS process. The simulation and optimization of circuit is accomplished and the simulation results are obtained with Cadence Spectre. The simulation results show that the circuit can get 12 bit resolution . The highest sample rates can be 50MSample/s. The test results show that the requirement of the static performance of circuit units can be well achieved. This circuit can be used in the fields of video and audio instruments and the sample of intermediate frequency transceiver of communication.
本次设计采用上华0.5um DPDM CMOS工艺试流片，应用Cadence Spectre仿真工具对电路仿真表明设计可以达到十二位精度要求，最高采样速率达到50Msample／s，测试结果静态参数指标达到了设计要求．本电路可以应用在音频，视频设备、通讯接收器的中频采样等领域。
As an interface circuit of analog signal and digital signal, Analog to digital converters get more and more important with the digitalize of circuit system. This thesis submitted a design of 12 bit pipeline analog to digital converter. We did much work in the system architecture design and the transistor level module circuit design. The purpose of this thesis is design a 50Msample/s 12 bit resolution pipeline ADC . A ten stage pipelined architecture was used in this design .The first stage is an 4 bit flash sub ADC, followed by eight stages 1. 5 bit per stage sub ADC and an 1 bit flash ADC. These ten stages formed the ADC core. We accomplished the sub module circuits design, such as high resolution sample and hold circuit, high gain wide bandwidth operational transconductance amplifier ,low offset voltage、low power, high speed comparator, 1.5 bit per stage sub ADC, digital correction circuit, clock stabilization and generation circuit , the trasistor level band gap reference voltage with output buffers and current source reference circuit.
This design was tape out based on CSMC 0.5um 2P2M CMOS process. The simulation and optimization of circuit is accomplished and the simulation results are obtained with Cadence Spectre. The simulation results show that the circuit can get 12 bit resolution . The highest sample rates can be 50MSample/s. The test results show that the requirement of the static performance of circuit units can be well achieved. This circuit can be used in the fields of video and audio instruments and the sample of intermediate frequency transceiver of communication.
引文
[1] Behzad Razavi. "Principle of Data Conversion System Design" [M]. Wiley-IEEE Press, 1995
[2] J. G. Proakis, et al., "Introduction to Digital Signal Processing", Macmillan Publishing Company, 1989.
[3] 陈震初．“发展我国数据转换电路的几点建议”．微电子学，1998，Vol．28，No．4：233~235
[4] 易婷．“高性能∑△模数转换器设计”，博士论文复旦大学，2004
[5] Behzad Razavi. "Principle of Data Conversion System Design" [M]. Wiley-IEEE Press, 1995
[6] 高光天．“模数转换器应用技术”[M]．北京：科学出版社，2001．36-40
[7] 蒋和全．“高速模数转换器 (ADC) 部份参数的动态测试研究”[D]．北京：中国期刊网优秀博硕士学位论文全文数据库，2000
[8] B. tternes, A. Briskemyr, etc. "A 1.2V 220MS/s lOb Pipelined ADC inplenented inO. 13um Digital CMOS". ISSCC Dig. Tech. Papers. Feb, 2004.
[9] Yang, W.; Kelly, D.; Mehr, L.; Sayuk, M. T.; Singer, L.; "A 3-V 340-mW 14-b 75-Msample/sCMOS ADC with 85-dB SFDR at Nyquist input" in Solid-State Circuits, IEEE. Journal of Volume 36, Issue 12, Dec. 2001
[10] Cormac S. G. Conroy. "A High-Speed Parallel Pipeline A/D Converter Technique in CMOS" [J]. Memorandum No. UCB/ERL M94/9, Electronics Research Laboratory, U. C. Berkeley, February 1994, pp. 119-132.
[11] Ausin. J. L,. Torelli. G, Duque-Carrillo, J. F. Linearity enhancement of oversampled pipeline A/D converters using sigma-delta modulation. Circuit Theory and Design[J], 2005. Proceedings of the 2005 European Conference on Volume 2, 28 Aug. -2 Sept. 2005 Page(s): Ⅱ/59 - Ⅱ/62 vol.
[12] Rudy Van de Plassche. Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 1994
[13] P. E. Allen, "CMOS analog circuit design" -2nd, Oxford University Press, Inc., 2002
[14] 毕查德．拉扎维著，陈贵灿，程军，张瑞智等译；“模拟CMOS集成电路设计”，西安交通大学出版社2003年
[15] 李福乐．“适宜于系统集成的高速高精度模数转换电路设计技术研究”．清华大学工学博士论文，2003
[16] D. W. Cline' s Ph D Thesis. "Noise/speed/power trade-offs in pipeline A/D converters[D]," U. C. Berkeley, 1995.
[17] C. S. G. Conroy, D. W. Cline, and P. R. Gray, "An 8-bit 85-Mample/s parallel pipeline A/D converter in lum CMOS,": LEES J. Solid-State Circuits, vol. 28, no. 4, Apri] 1993, pp. 447-454
[18] IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std 1241-2000
[19] L. A. Singer and T. L. Brooks. A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter. Symp. VLSI Circuits Dig. Tech. Papers[J]. Jun. 1996, pp. 94-95.
[20] Frank W. Singor and W. Martin, Snelgrove, Switched-Capacitor Bandpass Delta-Sigma A/D Modulation at 10.7 MHz, IEEE J. Solid-State Circuits, vol. 30, no. 3, March 1995: 184-192.
[21] Thomas B. Cho, "Low-Power Low--Voltage Analog-to-Digital Conversion Techniques Using Pipelined Architectures," Memorandum No. UCB/ERL M95123, Electronics Research Laboratory, U. C. Berkeley, April 1995, pp. 98—102.
[22] 朱樟明，杨银堂，柴常春；“新型 CMOS 采样／保持电路的设计研究”微电子学 Vol．34，No．3 Jun．2004
[23] A. Abo, "Design for Reliability of Low-Voltage, Switched-Capacitor Circuits," PhD Thesis, University of California, Berkeley, May 1999
[24] Carl R. Grace; Paul J. Hurst; and Stephen H. Lewis; "A 12-bit 80-MSample/s pipelined ADC With Bootstrapped Digital Calibration" in Solid-State Circuits, IEEE Journal OF Volume 40, NO. 12, May 2005
[25] Y. Chiu, P. Gray and B. Nikolio, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE J. Solid-State Circuits, vol. 39, pp. 2139-2151, Dec. 2004.
[26] Lee, Y. P.; Geiger, R. L.; "Gain error correction scheme for multiply-by-two gain amplifier in pipelined ADC" in Circuits and Systems, 1999/42~(nd) Midwest Symposium on Volume 1, 8-11 Aug. 1999
[27] S. H. Lewis, H. S. Fetterman , "A 10-b 20 M samples/s analog-to-digital converter IEEE Journal of solid-state circuits", 1992, Vol. 27, No. 3: 351~357
[28] D W. Cline , "Noise, Speed, and Power Trade-oAfs in Pipelined Analog to Digital Converters". U. C. Berkeley Doctoral Thesis, 1994.
[29] L. A. Singer and T. L. Brooks, "A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1996, pp. 94 -95.
[30] S. H. Lewis "Optimizing the stage resolution in Pipelined Multistage Analog-to-Digital Converters for Video-Rate Applications". IEEE Transactions on Circuits and System -Ⅱ. 1992, 39(8): 516-523
[31] M. Y. Azizi , A. Saeedfar, H. Z. Hoseini , O. Shoaei,; "Thermal noise analysis of multi-bit SC gain-stages for low-voltage high-resolution pipeline ADC design" in Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on Volume 2, 10-11 July 2003
[32] L. Singer, S. Ho, M. Timko, and D. Kelly, "A 12-b 65-Msample/s CMOS ADC with 82-dB SFDR at 120 MHz," in ISSCC Diff. Tech. Papers, Feb. 2000, pp. 38 -39.,
[33] C. Enz. and G. Ternes, "Circuit techniques for reducing the effects of opamp imperfections: Autozeroing, correlated double sampling and chopper stabilization," Proc. IEEE, pp. 1584-1614, Nov. 1996
[34] 秦世才，高清运．现代模拟集成电子学[M]．北京：科学出版社，2003：1
[35] R J. Baker CMOS Mixed-Signal Circuit Design. IEEE Press, Wiley interscience, 2002, 312-385
[36] Seung-Bin You, Zu-Whan Lee, Hee Cheol Choi, Ho-Jin Park, Jae-Whui Kim, P. Chung, "A 3. 3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter" in Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on Volume 1, 28-31 May 2000
[37] Law, Waisiu.; "Digital calibration of non-ideal pipelined analog-to-digital converters.", Ph. D. Source: Dissertation Abstracts International, Volume: 64-11, Section: B 2003
[38] George Chien. High-Speed, Low-Power, Low Voltage pipelined Analog-to-Digital Converter[D]. Ph. D. Thesis. University of California, Berkeley, 1996..
[39] 黄立中，陈贵灿，程军．10位20Msample／s CMOS 流水线A／D转换器的设计．西安交通大学学报，Vol33，No7，1999，pp102-104
[40] 邬成，刘文平，权海洋，罗来华“一种10位 50MSPS CMOS 流水线A／D转换器”微电子学Vol．34．No．6 Dec．2004
[41] R. J Baker, H. W. Li, and D. E. Boyce, "CMOS Circuit Design, Layout, and Simulation", New York, Inc., 1998.
[42] 王松林、贾云彬、来新泉、王洪义．“一款基于 BICMOS 工艺的高 PSRR 的带隙基准电路”[J]．电子质量 (质量工程卷) 2005年1期
[43]．李桂华，孙仲林，吉利久．“CMOS 锁相环PLL 的设计研究．半导体杂志”，2000，Vol．25，NO．3，pp．30-37
[44] Alan Hastings, "The Art of Analog Layout", Prentice Hall International, Inc., 2001
[2] J. G. Proakis, et al., "Introduction to Digital Signal Processing", Macmillan Publishing Company, 1989.
[3] 陈震初．“发展我国数据转换电路的几点建议”．微电子学，1998，Vol．28，No．4：233~235
[4] 易婷．“高性能∑△模数转换器设计”，博士论文复旦大学，2004
[5] Behzad Razavi. "Principle of Data Conversion System Design" [M]. Wiley-IEEE Press, 1995
[6] 高光天．“模数转换器应用技术”[M]．北京：科学出版社，2001．36-40
[7] 蒋和全．“高速模数转换器 (ADC) 部份参数的动态测试研究”[D]．北京：中国期刊网优秀博硕士学位论文全文数据库，2000
[8] B. tternes, A. Briskemyr, etc. "A 1.2V 220MS/s lOb Pipelined ADC inplenented inO. 13um Digital CMOS". ISSCC Dig. Tech. Papers. Feb, 2004.
[9] Yang, W.; Kelly, D.; Mehr, L.; Sayuk, M. T.; Singer, L.; "A 3-V 340-mW 14-b 75-Msample/sCMOS ADC with 85-dB SFDR at Nyquist input" in Solid-State Circuits, IEEE. Journal of Volume 36, Issue 12, Dec. 2001
[10] Cormac S. G. Conroy. "A High-Speed Parallel Pipeline A/D Converter Technique in CMOS" [J]. Memorandum No. UCB/ERL M94/9, Electronics Research Laboratory, U. C. Berkeley, February 1994, pp. 119-132.
[11] Ausin. J. L,. Torelli. G, Duque-Carrillo, J. F. Linearity enhancement of oversampled pipeline A/D converters using sigma-delta modulation. Circuit Theory and Design[J], 2005. Proceedings of the 2005 European Conference on Volume 2, 28 Aug. -2 Sept. 2005 Page(s): Ⅱ/59 - Ⅱ/62 vol.
[12] Rudy Van de Plassche. Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 1994
[13] P. E. Allen, "CMOS analog circuit design" -2nd, Oxford University Press, Inc., 2002
[14] 毕查德．拉扎维著，陈贵灿，程军，张瑞智等译；“模拟CMOS集成电路设计”，西安交通大学出版社2003年
[15] 李福乐．“适宜于系统集成的高速高精度模数转换电路设计技术研究”．清华大学工学博士论文，2003
[16] D. W. Cline' s Ph D Thesis. "Noise/speed/power trade-offs in pipeline A/D converters[D]," U. C. Berkeley, 1995.
[17] C. S. G. Conroy, D. W. Cline, and P. R. Gray, "An 8-bit 85-Mample/s parallel pipeline A/D converter in lum CMOS,": LEES J. Solid-State Circuits, vol. 28, no. 4, Apri] 1993, pp. 447-454
[18] IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters, IEEE Std 1241-2000
[19] L. A. Singer and T. L. Brooks. A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter. Symp. VLSI Circuits Dig. Tech. Papers[J]. Jun. 1996, pp. 94-95.
[20] Frank W. Singor and W. Martin, Snelgrove, Switched-Capacitor Bandpass Delta-Sigma A/D Modulation at 10.7 MHz, IEEE J. Solid-State Circuits, vol. 30, no. 3, March 1995: 184-192.
[21] Thomas B. Cho, "Low-Power Low--Voltage Analog-to-Digital Conversion Techniques Using Pipelined Architectures," Memorandum No. UCB/ERL M95123, Electronics Research Laboratory, U. C. Berkeley, April 1995, pp. 98—102.
[22] 朱樟明，杨银堂，柴常春；“新型 CMOS 采样／保持电路的设计研究”微电子学 Vol．34，No．3 Jun．2004
[23] A. Abo, "Design for Reliability of Low-Voltage, Switched-Capacitor Circuits," PhD Thesis, University of California, Berkeley, May 1999
[24] Carl R. Grace; Paul J. Hurst; and Stephen H. Lewis; "A 12-bit 80-MSample/s pipelined ADC With Bootstrapped Digital Calibration" in Solid-State Circuits, IEEE Journal OF Volume 40, NO. 12, May 2005
[25] Y. Chiu, P. Gray and B. Nikolio, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR," IEEE J. Solid-State Circuits, vol. 39, pp. 2139-2151, Dec. 2004.
[26] Lee, Y. P.; Geiger, R. L.; "Gain error correction scheme for multiply-by-two gain amplifier in pipelined ADC" in Circuits and Systems, 1999/42~(nd) Midwest Symposium on Volume 1, 8-11 Aug. 1999
[27] S. H. Lewis, H. S. Fetterman , "A 10-b 20 M samples/s analog-to-digital converter IEEE Journal of solid-state circuits", 1992, Vol. 27, No. 3: 351~357
[28] D W. Cline , "Noise, Speed, and Power Trade-oAfs in Pipelined Analog to Digital Converters". U. C. Berkeley Doctoral Thesis, 1994.
[29] L. A. Singer and T. L. Brooks, "A 14-bit 10-MHz calibration-free CMOS pipelined A/D converter," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1996, pp. 94 -95.
[30] S. H. Lewis "Optimizing the stage resolution in Pipelined Multistage Analog-to-Digital Converters for Video-Rate Applications". IEEE Transactions on Circuits and System -Ⅱ. 1992, 39(8): 516-523
[31] M. Y. Azizi , A. Saeedfar, H. Z. Hoseini , O. Shoaei,; "Thermal noise analysis of multi-bit SC gain-stages for low-voltage high-resolution pipeline ADC design" in Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on Volume 2, 10-11 July 2003
[32] L. Singer, S. Ho, M. Timko, and D. Kelly, "A 12-b 65-Msample/s CMOS ADC with 82-dB SFDR at 120 MHz," in ISSCC Diff. Tech. Papers, Feb. 2000, pp. 38 -39.,
[33] C. Enz. and G. Ternes, "Circuit techniques for reducing the effects of opamp imperfections: Autozeroing, correlated double sampling and chopper stabilization," Proc. IEEE, pp. 1584-1614, Nov. 1996
[34] 秦世才，高清运．现代模拟集成电子学[M]．北京：科学出版社，2003：1
[35] R J. Baker CMOS Mixed-Signal Circuit Design. IEEE Press, Wiley interscience, 2002, 312-385
[36] Seung-Bin You, Zu-Whan Lee, Hee Cheol Choi, Ho-Jin Park, Jae-Whui Kim, P. Chung, "A 3. 3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter" in Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on Volume 1, 28-31 May 2000
[37] Law, Waisiu.; "Digital calibration of non-ideal pipelined analog-to-digital converters.", Ph. D. Source: Dissertation Abstracts International, Volume: 64-11, Section: B 2003
[38] George Chien. High-Speed, Low-Power, Low Voltage pipelined Analog-to-Digital Converter[D]. Ph. D. Thesis. University of California, Berkeley, 1996..
[39] 黄立中，陈贵灿，程军．10位20Msample／s CMOS 流水线A／D转换器的设计．西安交通大学学报，Vol33，No7，1999，pp102-104
[40] 邬成，刘文平，权海洋，罗来华“一种10位 50MSPS CMOS 流水线A／D转换器”微电子学Vol．34．No．6 Dec．2004
[41] R. J Baker, H. W. Li, and D. E. Boyce, "CMOS Circuit Design, Layout, and Simulation", New York, Inc., 1998.
[42] 王松林、贾云彬、来新泉、王洪义．“一款基于 BICMOS 工艺的高 PSRR 的带隙基准电路”[J]．电子质量 (质量工程卷) 2005年1期
[43]．李桂华，孙仲林，吉利久．“CMOS 锁相环PLL 的设计研究．半导体杂志”，2000，Vol．25，NO．3，pp．30-37
[44] Alan Hastings, "The Art of Analog Layout", Prentice Hall International, Inc., 2001