DVB-T系统的数字接收机中下变频技术的研究与仿真
摘要
本文基于欧洲的DVB-T标准,对DVB-T系统接收机中的数字下变频器进行研究和设计。数字下变频器(Digital Down Converter,DDC)作为DVB-T系统数字接收机的重要组成部分,把中频的数字信号搬移到基带,有效的降低了信号的数据率,为后级基带信号处理创造了条件。在满足系统要求的前提下解决了通用芯片价格昂贵、灵活性不强且不利于整体集成的缺陷,有利于日后DVB-T接收芯片ASIC实现。
本课题主要任务是设计一个能够用于DVB-T接收机的数字下变频模块。首先分析了DVB-T系统的结构和数字下变频技术的特点,研究了数字下变频的相关理论与算法,主要算法和理论是:带通采样、CORDIC算法、查表法、内插算法;其次采用自顶向下的模块化设计方法,将数字下变频器按功能划分为若干模块。并在此基础上对数字下变频的各个模块进行频谱分析和算法仿真;最后着重对数字下变频进行硬件设计与优化,采用Verilog HDL语言做为设计内部逻辑的硬件描述语言,实现了DVB-T接收机中数字下变频模块的功能仿真、测试和综合。
为了便于以后ASIC实现,在设计模块时除考虑功能实现外,还要尽可能做到结构优化。在数控振荡器的设计中,给出了基于查找表(LUT)和坐标旋转矢量(CORDIC)两种算法的设计方案,改进NCO的设计,使NCO中的三角函数表资源节省了75%;在FIR滤波器设计时,采用CSD编码和系数分解法对滤波器的系数进行优化,并结合实例给出了它们的优化效果;改进传统Farrow结构内插滤波器。
最后,数字下变频器在Xilinx VirtexⅡ系列FPGA器件下得到硬件实现和验证,满足系统所需的要求。
This paper introduces the structure of the receiver end of DVB-T system, and discusses the study and design of the Digital Down Converter part. Digital Down Converter is a very important part of this system, it converts the IF signal into baseband, reduces the signal rate and then makes it easy for the later real time DSP operation part. Different from other traditional DDC, the architecture we desgined here can meet the needs of later DDC ASIC implementation.
The purpose of this task designs the DDC that is applied to the receiver end of DVB-T system. Firstly, the related theory and algorithm of DDC are introduced. which contants CORDIC、NCO、LUT and interpolator filter. Secondly, using Top-Down design method, The DDC are divided to many function modules and organized to the module library. Meanwhile we simulate the system in Matlab, to check the system feasibility. Finally, the design method and design flow of FPGA are summarized, taking the example of Xilinx's FPGA, and on a basis of it. we use Verilog-HDL to program the system, and implement it in the FPGA chip.
In order to integrate DDC as ASIC , the paper not only focuses on realizing perform ance but on optimizing structure as well. In practice, these function modules are selected, configured and optimized to satisfy the system demand. Firstly, based on look-up table (LUT) and Coordinate Rotation Digital Computer (CORDIC) algorithm, a method for implementing a numerically controlled oscillator(NCO) is described in the paper; Secondly, the multiplier optimizing technology-CSD coding, coefficient analyze for direct structure and reduced adder graph for transpose structure, are discussed. Also the optimizing effect is presented with the examples. Thirdly, design a new structure based on the structure of Farrow in the interpolator filter.
The last part of the dissertation presents system modeling, and shows the testing results.Which is proved that FPGA implementation can meet design request.
本课题主要任务是设计一个能够用于DVB-T接收机的数字下变频模块。首先分析了DVB-T系统的结构和数字下变频技术的特点,研究了数字下变频的相关理论与算法,主要算法和理论是:带通采样、CORDIC算法、查表法、内插算法;其次采用自顶向下的模块化设计方法,将数字下变频器按功能划分为若干模块。并在此基础上对数字下变频的各个模块进行频谱分析和算法仿真;最后着重对数字下变频进行硬件设计与优化,采用Verilog HDL语言做为设计内部逻辑的硬件描述语言,实现了DVB-T接收机中数字下变频模块的功能仿真、测试和综合。
为了便于以后ASIC实现,在设计模块时除考虑功能实现外,还要尽可能做到结构优化。在数控振荡器的设计中,给出了基于查找表(LUT)和坐标旋转矢量(CORDIC)两种算法的设计方案,改进NCO的设计,使NCO中的三角函数表资源节省了75%;在FIR滤波器设计时,采用CSD编码和系数分解法对滤波器的系数进行优化,并结合实例给出了它们的优化效果;改进传统Farrow结构内插滤波器。
最后,数字下变频器在Xilinx VirtexⅡ系列FPGA器件下得到硬件实现和验证,满足系统所需的要求。
This paper introduces the structure of the receiver end of DVB-T system, and discusses the study and design of the Digital Down Converter part. Digital Down Converter is a very important part of this system, it converts the IF signal into baseband, reduces the signal rate and then makes it easy for the later real time DSP operation part. Different from other traditional DDC, the architecture we desgined here can meet the needs of later DDC ASIC implementation.
The purpose of this task designs the DDC that is applied to the receiver end of DVB-T system. Firstly, the related theory and algorithm of DDC are introduced. which contants CORDIC、NCO、LUT and interpolator filter. Secondly, using Top-Down design method, The DDC are divided to many function modules and organized to the module library. Meanwhile we simulate the system in Matlab, to check the system feasibility. Finally, the design method and design flow of FPGA are summarized, taking the example of Xilinx's FPGA, and on a basis of it. we use Verilog-HDL to program the system, and implement it in the FPGA chip.
In order to integrate DDC as ASIC , the paper not only focuses on realizing perform ance but on optimizing structure as well. In practice, these function modules are selected, configured and optimized to satisfy the system demand. Firstly, based on look-up table (LUT) and Coordinate Rotation Digital Computer (CORDIC) algorithm, a method for implementing a numerically controlled oscillator(NCO) is described in the paper; Secondly, the multiplier optimizing technology-CSD coding, coefficient analyze for direct structure and reduced adder graph for transpose structure, are discussed. Also the optimizing effect is presented with the examples. Thirdly, design a new structure based on the structure of Farrow in the interpolator filter.
The last part of the dissertation presents system modeling, and shows the testing results.Which is proved that FPGA implementation can meet design request.
引文
[1]中华人民共和国国家质量监督检验检疫总局中国国家标准化管理委员会.GB20600-2006.数字电视地面广播阐述系统帧结构、信道编码和调制.北京:中国标准出版社,2006
[2]Digital Video Broadcasting(DVB):Framing structure,channel coding and modulation for terrestrial television,European Standard(EN)300744 V1.5.1,European Telecommunications Standard Institute(ETSI),Nov.2004
[3]Yiyan Wu,Ewa Pliszka,Bernard Caron,Pierre Bouchard.Comparison of Terrestrial DTV Transmission Systems:The ATSC 8-VSB,the DVB-T COFDM and the ISDB-T BST-OFDM.[C].IEEE Transactions on Broadcasting,2000,2(46):101-113
[4]Rajitha Bandara Palipana,Kah-Seng Chung.Frequency Domain IQ Correction in a Direct-conversion Receiver or DVB-T[J].IEEE,2005 Asia-PACific Conference on Communications,Perth,Western Australia,2005,10:3-5
[5]郑君里,应启晰,杨为理.信号与系统[M].北京:高等教育出版社,2003:30-112
[6]杨小牛,楼才义,徐建良著.软件无线电原理与应用[M].北京:电子工业出版社,2001:20-178
[7]刘著.iDTV数字电视接收模块的软件设计与实现.[工学硕士学位论文].成都:电子科技大学,2006,4:6-8
[8]贾宁.DVB-T系统中内码系统的算法研究和硬件实现.[工学硕士学位论文].杭州:浙江大学,2006,1:17-22
[9]郭福成,皇甫堪,李纲.数字下变频实现技术研究[J].国防科技大学学报,2000,20(5):95-97
[10]Voider J E.The CORDIC Trigonometric Computing Technique[J].IRE Transations on Electronics Computer,1959,8(3):330-334
[11]黄仰博,孟繁智.基于FPGA的数字下变频器设计[J].微处理器,2005.12:6
[12]何水艳.浅析数字下变频中的NCO[J].高等函授学报(自然科学版),2004.2(17):1
[13]刘玉良,李玲远.数字下变频器中数控振荡器的设计与硬件实现[J].电子技术,2005.5(10):2
[14]Walther J S.A Unified Algorithm for Elementary Functions[C].AFIPS Spring Joint Computer Conf.1997,(38):379-385
[15]Numerical Accuracy and Hardware Tradroffs for CORDIC Arithmetic for Special-Purpose Processors.Kishore Lota,Josph R.Cavallaro[J].IEEE TRANSACTIONS ON COMPUTERS,1993,6(42):7
[16]Xiaobo Ronald Hu,Harber G,Steven Bass C.Expanding the range of Convergence of the CORDIC of the CORDIC Algorithm[J].IEEE Transactions on Computer,1991,(40):13-20
[17]MITOLA J,GERALDQ.Cognitive radio:making software radios more personal[J].IEEE Personal Communications,1999,(8):20-36
[18]刘奕,曾文海.CORDIC算法在数字下变频中的应用[J].电视技术,2006年第4/286期,117-121
[19]李滔,韩月秋.基于流水线CORDIC算法的二角函数发生器[J].系统工程与电子技术,2000,Vol.22,No.4:85-87
[20]李素芝,万建伟.时域离散信号处理[M].长沙:国防科技大学出版社,1994:18-114
[21]竞锦辉.DVB-C接收芯片中数据同步的设计及实现.[工学硕士学位论文].杭州:浙江大学,2003,2:11-21
[22]李鸿翔.可编程数字下变频器的关键技术[J].遥控遥测,2003,24(2):19-22
[23]杨小牛,邹少压,楼才义.软件无线电技术与实现[M].北京:电子工业出版社,2004:112-154
[24]Qiu Xiao-yong,Yang Zi-jie,Wang Shu-rong.The Realization of the Programmable Synchro Controller of HF Ground Wave Radar on FPGA[J].Wuhan Univ(Nat Sci Ed),2005,48(3):375-378
[25]杨力生,韩庆文,杨士中.数字下变频及其频谱分析[J].信息与电子下程,2005:3(2):90-92
[26]宋飞.基于FPGA的数字中频处理技术研究.[硕士学位论文].西安:西安电子科杖大学,2007,1:7-13
[27]刘力.基于FPGA的数字下变频器的设计与应用.[硕士学位论文].成都:电子科技大学,2006,10:6-8
[28]周盛荣.DVB-T接收芯片的设计与开发.[工学硕士学位论文].上海:同济大学,2007.3
[29]湛伟.射频接收芯片结构选择的几个要点[J].质量工程,2007年07期,38-39
[30]李鲁燕.有线电视邻频系统的干扰[J].中国有线电视,2004年11期,58-59
[31]MA Zhi-gang,WEN Bi-yang.CIC Filter Theory in DDC and Implementation by Using FPGA[J].Wuhan University Journal of Natural Sciences,2004,(06):118-123
[32]涂志文.谈谈抑制邻频干扰[J].电视技术,1995年第6期,68-69
[33]程水英,陈鹏举,武传华.带通信号的正交调制与数字下变频器的结构设计[J].无线通信技术,2002,4:17-19
[34]WU Cheng-shing.Modified vector rotational CORDIC(MVR-CORDIC)algorithm and its application to FFT[J].IEEE Transactionson Circuits and Systems.2001,48:548-561
[35]孙丹丹,杨萃元,赵大勇.数字下变频器在软件无线电接收机中的应用[J].信息技术,2002,7:24
[36]李林.基于FPGA的数字下变频电路的设计与实现.[硕士学位论文].成都:电子科技大学,2006:10-50
[37]刘玉良,李玲远.数字下变频器中数控振荡器的设计与硬件实现[J].电子技术,2003,No1:44-45
[38]Hao-Yung Lo,Hsui-Feng Lin,Kuen-Shiuh Yang.A New Method of Implementation of VLSI CORDIC for Sine and Cosine Computation[J].IEEE,1995:1984-1987.
[39]韦逸嘉.数字化中频接收机及其算法研究.[工学硕士学位论文].电子科技大学,成都:2005.06.18-30
[40]郭晓宇,潘登,杨同中.基于FPGA实现FIR滤波器的研究,www.21cn.com.2004,7
[41]徐以涛,王呈贵,王金龙.基于DA算法的FIR滤波器硬件实现[J].解放军理工大学学报(自然科学版),2003,4(3):22-25
[42]黄仰博.基于FPGA的数字滤波器实现技术研究.[工学硕士学位论文].湖南:国防科学技术大学,2004.11(3):11-23
[43]FRANRZESKAKISE,LIUKJR.Class of square mot and division free algorithms and architectures for QRD based adaptive signal processing[C].IEEE Trans Signal Processing,1994,42(9):2455-2469
[44]CS Burrus.Digital filter structures described by distributed arithmetic[J].IEEE Transaction on Circuits and System,1977,3(12):102-107
[45]王诚,薛小刚,钟信潮.FPGA/CPLD设计工具—Xilinx ISE使用详解.人民邮电出版社[M],2004:40-115
[46]Zehavi E.8-Psk trellis codes for a Rayleigh channel[J].IEEE Trans.Commun,1992,40(5):873-884
[47]Yu Hen Hu,Zhenyang Wu.Transactions on Siganl Processing[J].IEEE 1995,(43):331-336
[48]王金明.Verilog HDL程序设计教程[M].北京:人民邮电出版社,2004:13-98
[49]简弘伦.精通Verilog HDL:IC设计核心技术实例详解[M].北京:电子工业出版社,2005:1-88
[50]侯伯亨,顾新编著.VHDL硬件描述语言与数字逻辑电路设计[M].西安:西安电子科技大学出版社,1999:1-119
[2]Digital Video Broadcasting(DVB):Framing structure,channel coding and modulation for terrestrial television,European Standard(EN)300744 V1.5.1,European Telecommunications Standard Institute(ETSI),Nov.2004
[3]Yiyan Wu,Ewa Pliszka,Bernard Caron,Pierre Bouchard.Comparison of Terrestrial DTV Transmission Systems:The ATSC 8-VSB,the DVB-T COFDM and the ISDB-T BST-OFDM.[C].IEEE Transactions on Broadcasting,2000,2(46):101-113
[4]Rajitha Bandara Palipana,Kah-Seng Chung.Frequency Domain IQ Correction in a Direct-conversion Receiver or DVB-T[J].IEEE,2005 Asia-PACific Conference on Communications,Perth,Western Australia,2005,10:3-5
[5]郑君里,应启晰,杨为理.信号与系统[M].北京:高等教育出版社,2003:30-112
[6]杨小牛,楼才义,徐建良著.软件无线电原理与应用[M].北京:电子工业出版社,2001:20-178
[7]刘著.iDTV数字电视接收模块的软件设计与实现.[工学硕士学位论文].成都:电子科技大学,2006,4:6-8
[8]贾宁.DVB-T系统中内码系统的算法研究和硬件实现.[工学硕士学位论文].杭州:浙江大学,2006,1:17-22
[9]郭福成,皇甫堪,李纲.数字下变频实现技术研究[J].国防科技大学学报,2000,20(5):95-97
[10]Voider J E.The CORDIC Trigonometric Computing Technique[J].IRE Transations on Electronics Computer,1959,8(3):330-334
[11]黄仰博,孟繁智.基于FPGA的数字下变频器设计[J].微处理器,2005.12:6
[12]何水艳.浅析数字下变频中的NCO[J].高等函授学报(自然科学版),2004.2(17):1
[13]刘玉良,李玲远.数字下变频器中数控振荡器的设计与硬件实现[J].电子技术,2005.5(10):2
[14]Walther J S.A Unified Algorithm for Elementary Functions[C].AFIPS Spring Joint Computer Conf.1997,(38):379-385
[15]Numerical Accuracy and Hardware Tradroffs for CORDIC Arithmetic for Special-Purpose Processors.Kishore Lota,Josph R.Cavallaro[J].IEEE TRANSACTIONS ON COMPUTERS,1993,6(42):7
[16]Xiaobo Ronald Hu,Harber G,Steven Bass C.Expanding the range of Convergence of the CORDIC of the CORDIC Algorithm[J].IEEE Transactions on Computer,1991,(40):13-20
[17]MITOLA J,GERALDQ.Cognitive radio:making software radios more personal[J].IEEE Personal Communications,1999,(8):20-36
[18]刘奕,曾文海.CORDIC算法在数字下变频中的应用[J].电视技术,2006年第4/286期,117-121
[19]李滔,韩月秋.基于流水线CORDIC算法的二角函数发生器[J].系统工程与电子技术,2000,Vol.22,No.4:85-87
[20]李素芝,万建伟.时域离散信号处理[M].长沙:国防科技大学出版社,1994:18-114
[21]竞锦辉.DVB-C接收芯片中数据同步的设计及实现.[工学硕士学位论文].杭州:浙江大学,2003,2:11-21
[22]李鸿翔.可编程数字下变频器的关键技术[J].遥控遥测,2003,24(2):19-22
[23]杨小牛,邹少压,楼才义.软件无线电技术与实现[M].北京:电子工业出版社,2004:112-154
[24]Qiu Xiao-yong,Yang Zi-jie,Wang Shu-rong.The Realization of the Programmable Synchro Controller of HF Ground Wave Radar on FPGA[J].Wuhan Univ(Nat Sci Ed),2005,48(3):375-378
[25]杨力生,韩庆文,杨士中.数字下变频及其频谱分析[J].信息与电子下程,2005:3(2):90-92
[26]宋飞.基于FPGA的数字中频处理技术研究.[硕士学位论文].西安:西安电子科杖大学,2007,1:7-13
[27]刘力.基于FPGA的数字下变频器的设计与应用.[硕士学位论文].成都:电子科技大学,2006,10:6-8
[28]周盛荣.DVB-T接收芯片的设计与开发.[工学硕士学位论文].上海:同济大学,2007.3
[29]湛伟.射频接收芯片结构选择的几个要点[J].质量工程,2007年07期,38-39
[30]李鲁燕.有线电视邻频系统的干扰[J].中国有线电视,2004年11期,58-59
[31]MA Zhi-gang,WEN Bi-yang.CIC Filter Theory in DDC and Implementation by Using FPGA[J].Wuhan University Journal of Natural Sciences,2004,(06):118-123
[32]涂志文.谈谈抑制邻频干扰[J].电视技术,1995年第6期,68-69
[33]程水英,陈鹏举,武传华.带通信号的正交调制与数字下变频器的结构设计[J].无线通信技术,2002,4:17-19
[34]WU Cheng-shing.Modified vector rotational CORDIC(MVR-CORDIC)algorithm and its application to FFT[J].IEEE Transactionson Circuits and Systems.2001,48:548-561
[35]孙丹丹,杨萃元,赵大勇.数字下变频器在软件无线电接收机中的应用[J].信息技术,2002,7:24
[36]李林.基于FPGA的数字下变频电路的设计与实现.[硕士学位论文].成都:电子科技大学,2006:10-50
[37]刘玉良,李玲远.数字下变频器中数控振荡器的设计与硬件实现[J].电子技术,2003,No1:44-45
[38]Hao-Yung Lo,Hsui-Feng Lin,Kuen-Shiuh Yang.A New Method of Implementation of VLSI CORDIC for Sine and Cosine Computation[J].IEEE,1995:1984-1987.
[39]韦逸嘉.数字化中频接收机及其算法研究.[工学硕士学位论文].电子科技大学,成都:2005.06.18-30
[40]郭晓宇,潘登,杨同中.基于FPGA实现FIR滤波器的研究,www.21cn.com.2004,7
[41]徐以涛,王呈贵,王金龙.基于DA算法的FIR滤波器硬件实现[J].解放军理工大学学报(自然科学版),2003,4(3):22-25
[42]黄仰博.基于FPGA的数字滤波器实现技术研究.[工学硕士学位论文].湖南:国防科学技术大学,2004.11(3):11-23
[43]FRANRZESKAKISE,LIUKJR.Class of square mot and division free algorithms and architectures for QRD based adaptive signal processing[C].IEEE Trans Signal Processing,1994,42(9):2455-2469
[44]CS Burrus.Digital filter structures described by distributed arithmetic[J].IEEE Transaction on Circuits and System,1977,3(12):102-107
[45]王诚,薛小刚,钟信潮.FPGA/CPLD设计工具—Xilinx ISE使用详解.人民邮电出版社[M],2004:40-115
[46]Zehavi E.8-Psk trellis codes for a Rayleigh channel[J].IEEE Trans.Commun,1992,40(5):873-884
[47]Yu Hen Hu,Zhenyang Wu.Transactions on Siganl Processing[J].IEEE 1995,(43):331-336
[48]王金明.Verilog HDL程序设计教程[M].北京:人民邮电出版社,2004:13-98
[49]简弘伦.精通Verilog HDL:IC设计核心技术实例详解[M].北京:电子工业出版社,2005:1-88
[50]侯伯亨,顾新编著.VHDL硬件描述语言与数字逻辑电路设计[M].西安:西安电子科技大学出版社,1999:1-119