H.264和AVS多模视频解码器运动矢量预测模块设计与实现
|
摘要
在当今社会,视频信息已经成为人类生产和生活中不可或缺的重要元素,对于视频编解码芯片的巨大需求造成了近年来半导体市场的空前繁荣。在市场推动力的作用下,对视频编解码标准及其有效实现方法的研究成为工业界和学术界不断探索的一个重要课题。
本文对目前代表世界先进水平的H.264和AVS两种视频编解码标准的帧间预测解码方法进行了探索和研究,致力于提出一种能够适应多标准共存市场现状的多模视频解码SoC的帧间预测解码及其运动矢量预测器的硬件设计与实现。
本文首先分析了视频领域半导体市场的现状和前景,说明了目前视频解码芯片设计中面临的多标准共存、设计周期紧张、开发成本低廉等突出矛盾,和进行本课题研究的意义。
之后,本文总结了各种帧间预测编码及其解码方法,对H.264和AVS两种标准运动矢量预测方法进行了详细分析,研究了两标准解码过程中运动矢量预测过程在硬件实现中的可复用性,针对两标准对存储空间的需求,提出了一套统一而有效的存储管理机制;同时,本文还提出了一套完整的多模运动矢量预测模块的硬件设计方案;详细介绍了所设计的预测器的工作机制、接口和时序,并分模块详细介绍了各子模块的设计方案,说明了其功能和特点;此外,本文详细分析了设计中的关键点和创新点,其中包括仲裁控制模块内部的控制状态机,空域预测模块的流水线结构,伸缩模块中的流水线阵列除法器以及存储控制模块的实现方案。
最后,在介绍了模块设计中采用的设计流程、开发环境及测试方案后,详细给出了包括RTL仿真、Netlist综合、形式验证和门级仿真在内的各个实验步骤的结果和报告,对实验结果进行了分析和对比。并对全文进行了总结和展望。
In modern society, video information has become an indispensable element of human life, and the tremendous consumption needs of video decoding chip have led to unprecedented thriving of semiconductor market. Driven by the needs of market, research of video coding standards and corresponding hardware realizing method has become an important subject of both industrial and academic community.
This paper has studied the inter prediction method of prevailing video coding standards H.264 and AVS, which stand for the leading video coding technology of the world, and tried to propose a hardware realizing scheme for a motion vector predictor, which can meet the needs of concurrent situation of multiple video coding standards and be flexibly used in multi-mode video decoding SoC design.
First, the paper analyzed the present situation and bright future of video decoding semiconductor industry and also pointed out some conspicurity contradictions faced by this industry today, including the coexistence of multiple video coding standards, the high tension of design period and shotage of development cost. Then it brought out the meaning of our study.
After that, this paper summarized the common inter prediction coding and decoding method. A detailed explanation of motion vector prediction process of H.264 and AVS was made and based on this explanation we analyzed the possibility of hardware sharing during motion vector prediction between these two standards, and also proposed an effective memory control method for the multi-mode motion vector predictor according to the circumscribing of these two standards; meanwhile,the paper proposed a complete scheme of hardware design for multi-mode motion vector predictor; introduced the detail operating mechanisim, interface and timing of the design;and described the design scheme module by module. Besides, the important and creative parts of the design, including the state machine of control module, the pipeline architecture of spatial prediction module, array divider with pipeline in scale module, and the scheme of memory controller, were declared in the paper with emphases.
Finally , after introducing the design flow , environment of exploitation, and the simulation and verification method been used,the paper showed the detail results and reports of each stage of the design, including RTL simulation, synthesis, formal verification and Gate-level simulation. According to the compare and analysis of the experimental results, the paper drew a conclusion and forecast the future.
本文对目前代表世界先进水平的H.264和AVS两种视频编解码标准的帧间预测解码方法进行了探索和研究,致力于提出一种能够适应多标准共存市场现状的多模视频解码SoC的帧间预测解码及其运动矢量预测器的硬件设计与实现。
本文首先分析了视频领域半导体市场的现状和前景,说明了目前视频解码芯片设计中面临的多标准共存、设计周期紧张、开发成本低廉等突出矛盾,和进行本课题研究的意义。
之后,本文总结了各种帧间预测编码及其解码方法,对H.264和AVS两种标准运动矢量预测方法进行了详细分析,研究了两标准解码过程中运动矢量预测过程在硬件实现中的可复用性,针对两标准对存储空间的需求,提出了一套统一而有效的存储管理机制;同时,本文还提出了一套完整的多模运动矢量预测模块的硬件设计方案;详细介绍了所设计的预测器的工作机制、接口和时序,并分模块详细介绍了各子模块的设计方案,说明了其功能和特点;此外,本文详细分析了设计中的关键点和创新点,其中包括仲裁控制模块内部的控制状态机,空域预测模块的流水线结构,伸缩模块中的流水线阵列除法器以及存储控制模块的实现方案。
最后,在介绍了模块设计中采用的设计流程、开发环境及测试方案后,详细给出了包括RTL仿真、Netlist综合、形式验证和门级仿真在内的各个实验步骤的结果和报告,对实验结果进行了分析和对比。并对全文进行了总结和展望。
In modern society, video information has become an indispensable element of human life, and the tremendous consumption needs of video decoding chip have led to unprecedented thriving of semiconductor market. Driven by the needs of market, research of video coding standards and corresponding hardware realizing method has become an important subject of both industrial and academic community.
This paper has studied the inter prediction method of prevailing video coding standards H.264 and AVS, which stand for the leading video coding technology of the world, and tried to propose a hardware realizing scheme for a motion vector predictor, which can meet the needs of concurrent situation of multiple video coding standards and be flexibly used in multi-mode video decoding SoC design.
First, the paper analyzed the present situation and bright future of video decoding semiconductor industry and also pointed out some conspicurity contradictions faced by this industry today, including the coexistence of multiple video coding standards, the high tension of design period and shotage of development cost. Then it brought out the meaning of our study.
After that, this paper summarized the common inter prediction coding and decoding method. A detailed explanation of motion vector prediction process of H.264 and AVS was made and based on this explanation we analyzed the possibility of hardware sharing during motion vector prediction between these two standards, and also proposed an effective memory control method for the multi-mode motion vector predictor according to the circumscribing of these two standards; meanwhile,the paper proposed a complete scheme of hardware design for multi-mode motion vector predictor; introduced the detail operating mechanisim, interface and timing of the design;and described the design scheme module by module. Besides, the important and creative parts of the design, including the state machine of control module, the pipeline architecture of spatial prediction module, array divider with pipeline in scale module, and the scheme of memory controller, were declared in the paper with emphases.
Finally , after introducing the design flow , environment of exploitation, and the simulation and verification method been used,the paper showed the detail results and reports of each stage of the design, including RTL simulation, synthesis, formal verification and Gate-level simulation. According to the compare and analysis of the experimental results, the paper drew a conclusion and forecast the future.
引文
[1] 毕厚杰,新一代视频压缩编码标准——H.264/AVC,北京:人民邮电出版社, 2005.5.
[2] Bin S., Wen G., Don Xi, “Algorithmic and architectural co-design for integer motion estimation of AVS”, Consumer Electronics, IEEE Transactions on Volume 52, Issue 3, Aug. 2006.
[3] 马光胜、冯刚,SoC设计与IP核重用技术,北京:国防工业出版社,2006.8.
[4] Lain E. G. Richardson, “H.264 and MPEG-4 Video Compression”, John Wiley& Sons Ltd, 2003
[5] “Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec。 H.264/ISO/IEC 14 496-10 AVC,” in Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVTG050, 2003.
[6] 信息技术 先进音视频编码 第二部分:视频, 国家质量监督检验检疫总局, 2003.12
[7] Junhao, Z., Di, W., Lei, D., Don, X., Wen, G., “A motion vector predictor architecture for AVS and MPEG-2 HDTV decoder”, Lecture Notes in Computer Science 4261 LNCS, pp. 424-431, 2006.
[8] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay Luthra,“ Overview of The H.264/AVC Video Coding Standard”, IEEE Transactions on circuits and systems for Video Technology, July 2003.
[9] Lain E. G. Richardson , “H.264/MPEG-4 Part 10 White Paper” , http://www.vcodex.com, October 2002.
[10] “Generic Coding of Moving Pictures and Associated Audio Information- Part 2: Video,” ITU-T and ISO/IEC JTC 1, ITU-T Recommendation H.262 and ISO/IEC 13 818-2 (MPEG-2), 1994.
[11] R .Schafer, T. Wiegand, H. Schwarz, “The Emerging H.264/AVC Standard”, EBU Technical review, January 2003.
[12] Ji, X., Zhao, D., Gao, W., Huang, Q., Ma, S., Lu, Y., “New bi-prediction techniques for b pictures coding”, 2004 IEEE International Conference on Multimedia and Expo (ICME) 1, pp. 101-104, 2004.
[13] Lange, R., B?aszak, ?., Domański, M., “Simple AVC-based codecs with spatial scalability”, Proceedings - International Conference on Image Processing, ICIP 4, pp. 2299-2302, 2004.
[14] Chen, M.-J., Chiang, Y.-Y., Li, H.-J., Chi, M.-C., “Efficient multi-frame motion estimation algorithms for MPEG-4 AVC/JVT/H.264”, Proceedings - IEEE International Symposium on Circuits and Systems 3, pp. III737-III740, 2004.
[15] Zheng, J., Ji, X., Ni, G., Gao, W., Wu, F., “Extended direct mode for hierarchical B picture coding”, Proceedings - International Conference on Image Processing, ICIP 2, art. no. 1530042, pp. 265-268, 2005.
[16] Kurozumi, M., Nishida, Y., Nakasu, E., “MPEG-2 - High-compression technologies for HDTV”, EBU Technical Review, 2005.
[17] Shoham, A., “H.264: The video codec to watch”, Electronic Engineering Times (1361), pp. 12-15, 2005.
[18] Ji, S.-H., Park, J.-W., Kim, S.-D., “Optimization of memory management for H.264/AVC decoder”, 8th International Conference Advanced Communication Technology, ICACT 2006 - Proceedings 1, art. no. 1625525, pp. 65-68, 2006.
[19] 钟玉琢,MPEG-2 运动图像压缩编码国际标准及 MPEG 的新进展,北京:清华大学出版社, 2002.3
[20] 王诚,薛小刚,钟信潮,FPGA/CPLD 设计工具-Xilinx ISE5.x 使用详解,北京:人民邮电出版社,2003
[21] 许国辉,视频编解码芯片中的可重用性设计研究,浙江大学硕士论文,2005
[22] 朱松超,H.264 编码算法研究和基于 FPGA 的设计,西北工业大学硕士论文,2006
[23] 李兴,视频编解码芯片中的专用结构与通用结构设计研究,浙江大学硕士论文,2006
[24] 于保成,低码流 H.264 视频编码算法研究及 FPGA 实现探讨,中国海洋大学硕士论文,2005
[25] 李萌,HDTV 视频解码芯片的设计与优化,北京工业大学硕士论文,2005
[26] 常周林,基于 H264AVC 的 HDTV 视频解码芯片研究与初步设计,暨南大学硕士论文,2005
[2] Bin S., Wen G., Don Xi, “Algorithmic and architectural co-design for integer motion estimation of AVS”, Consumer Electronics, IEEE Transactions on Volume 52, Issue 3, Aug. 2006.
[3] 马光胜、冯刚,SoC设计与IP核重用技术,北京:国防工业出版社,2006.8.
[4] Lain E. G. Richardson, “H.264 and MPEG-4 Video Compression”, John Wiley& Sons Ltd, 2003
[5] “Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec。 H.264/ISO/IEC 14 496-10 AVC,” in Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVTG050, 2003.
[6] 信息技术 先进音视频编码 第二部分:视频, 国家质量监督检验检疫总局, 2003.12
[7] Junhao, Z., Di, W., Lei, D., Don, X., Wen, G., “A motion vector predictor architecture for AVS and MPEG-2 HDTV decoder”, Lecture Notes in Computer Science 4261 LNCS, pp. 424-431, 2006.
[8] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay Luthra,“ Overview of The H.264/AVC Video Coding Standard”, IEEE Transactions on circuits and systems for Video Technology, July 2003.
[9] Lain E. G. Richardson , “H.264/MPEG-4 Part 10 White Paper” , http://www.vcodex.com, October 2002.
[10] “Generic Coding of Moving Pictures and Associated Audio Information- Part 2: Video,” ITU-T and ISO/IEC JTC 1, ITU-T Recommendation H.262 and ISO/IEC 13 818-2 (MPEG-2), 1994.
[11] R .Schafer, T. Wiegand, H. Schwarz, “The Emerging H.264/AVC Standard”, EBU Technical review, January 2003.
[12] Ji, X., Zhao, D., Gao, W., Huang, Q., Ma, S., Lu, Y., “New bi-prediction techniques for b pictures coding”, 2004 IEEE International Conference on Multimedia and Expo (ICME) 1, pp. 101-104, 2004.
[13] Lange, R., B?aszak, ?., Domański, M., “Simple AVC-based codecs with spatial scalability”, Proceedings - International Conference on Image Processing, ICIP 4, pp. 2299-2302, 2004.
[14] Chen, M.-J., Chiang, Y.-Y., Li, H.-J., Chi, M.-C., “Efficient multi-frame motion estimation algorithms for MPEG-4 AVC/JVT/H.264”, Proceedings - IEEE International Symposium on Circuits and Systems 3, pp. III737-III740, 2004.
[15] Zheng, J., Ji, X., Ni, G., Gao, W., Wu, F., “Extended direct mode for hierarchical B picture coding”, Proceedings - International Conference on Image Processing, ICIP 2, art. no. 1530042, pp. 265-268, 2005.
[16] Kurozumi, M., Nishida, Y., Nakasu, E., “MPEG-2 - High-compression technologies for HDTV”, EBU Technical Review, 2005.
[17] Shoham, A., “H.264: The video codec to watch”, Electronic Engineering Times (1361), pp. 12-15, 2005.
[18] Ji, S.-H., Park, J.-W., Kim, S.-D., “Optimization of memory management for H.264/AVC decoder”, 8th International Conference Advanced Communication Technology, ICACT 2006 - Proceedings 1, art. no. 1625525, pp. 65-68, 2006.
[19] 钟玉琢,MPEG-2 运动图像压缩编码国际标准及 MPEG 的新进展,北京:清华大学出版社, 2002.3
[20] 王诚,薛小刚,钟信潮,FPGA/CPLD 设计工具-Xilinx ISE5.x 使用详解,北京:人民邮电出版社,2003
[21] 许国辉,视频编解码芯片中的可重用性设计研究,浙江大学硕士论文,2005
[22] 朱松超,H.264 编码算法研究和基于 FPGA 的设计,西北工业大学硕士论文,2006
[23] 李兴,视频编解码芯片中的专用结构与通用结构设计研究,浙江大学硕士论文,2006
[24] 于保成,低码流 H.264 视频编码算法研究及 FPGA 实现探讨,中国海洋大学硕士论文,2005
[25] 李萌,HDTV 视频解码芯片的设计与优化,北京工业大学硕士论文,2005
[26] 常周林,基于 H264AVC 的 HDTV 视频解码芯片研究与初步设计,暨南大学硕士论文,2005