硅基应变与弛豫材料的缺陷机理与表征研究
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摘要
应变SiGe和应变Si以其相对于体Si的诸多优点,成为遵循摩尔定律发展的新材料技术。由于SiGe与衬底之间存在较大的晶格失配,所以异质外延得到的薄膜往往具有很高的位错密度,这些位错极大地限制了器件的性能和可靠性。为了更好的降低和控制穿透位错密度,对硅基应变与弛豫材料缺陷机理及表征方法的研究显得尤为重要。
论文深入研究了硅基应变与弛豫材料中各种缺陷机理,重点对其中位错缺陷的类型、形成机理、特征、行为、成核及增殖机制进行了研究,同时还对缺陷的观察及位错密度的表征方法进行了重点研究。
本文中硅基应变与弛豫材料由RPCVD设备生长,使用透射电子显微镜对材料内部的缺陷及行为进行研究分析,通过腐蚀法对位错密度进行表征研究。实验结果表明,Ge组分梯度渐变缓冲层工艺和低温Si缓冲层工艺能大大降低穿透位错的密度。
通过改变腐蚀液配方及腐蚀时间等实验对表征方法进行了研究,提出了使用梯度腐蚀法测量位错密度。通过使用梯度腐蚀法,可以在同一个样片上进行多个时间的腐蚀实验,对比不同腐蚀时间样片的腐蚀效果,方便确定不同层结构样品的腐蚀时间,提高腐蚀后样片的观测效果。
Strained SiGe and strained Si is a better kind of material and technology than Si CMOS to keep on with the Moore's Law. Due to the large lattice mismatch between the layer and the substrate, the epitaxial film often receives a high dislocation density, which greatly degrades the device performance. For Reducing and controlling the threading dislocation density, it is necessary to have a research on defect mechanism and characterization for Si based strained and relaxed materials.
We researched into the shape, formation mechanism, character, behavior, nucleation and multiplication mechanism of dislocation in Si based strained and relaxed materials, we also have a good research on the observation of the defect and the characterization of dislocation density.
In this work we used the RPCVD device to epitaxial the Si based strained and relaxed materials, the behavior of defect are analyzed by TEM and the density dislocation was characterized by etching. According to the results of research, Ge component gradual changing buffer layer technology and low temperature Si buffer layer technology can both greatly reduce the threading dislocation density.
To get a better etch result, we did a lot of experiments by changing etching solution and etching time. We proposed the ideal of gradient etching .By this method ,we can do many experiments in one sample, determine the etching time with different layer structure easily,and it can improve the observe result of etching.
论文深入研究了硅基应变与弛豫材料中各种缺陷机理,重点对其中位错缺陷的类型、形成机理、特征、行为、成核及增殖机制进行了研究,同时还对缺陷的观察及位错密度的表征方法进行了重点研究。
本文中硅基应变与弛豫材料由RPCVD设备生长,使用透射电子显微镜对材料内部的缺陷及行为进行研究分析,通过腐蚀法对位错密度进行表征研究。实验结果表明,Ge组分梯度渐变缓冲层工艺和低温Si缓冲层工艺能大大降低穿透位错的密度。
通过改变腐蚀液配方及腐蚀时间等实验对表征方法进行了研究,提出了使用梯度腐蚀法测量位错密度。通过使用梯度腐蚀法,可以在同一个样片上进行多个时间的腐蚀实验,对比不同腐蚀时间样片的腐蚀效果,方便确定不同层结构样品的腐蚀时间,提高腐蚀后样片的观测效果。
Strained SiGe and strained Si is a better kind of material and technology than Si CMOS to keep on with the Moore's Law. Due to the large lattice mismatch between the layer and the substrate, the epitaxial film often receives a high dislocation density, which greatly degrades the device performance. For Reducing and controlling the threading dislocation density, it is necessary to have a research on defect mechanism and characterization for Si based strained and relaxed materials.
We researched into the shape, formation mechanism, character, behavior, nucleation and multiplication mechanism of dislocation in Si based strained and relaxed materials, we also have a good research on the observation of the defect and the characterization of dislocation density.
In this work we used the RPCVD device to epitaxial the Si based strained and relaxed materials, the behavior of defect are analyzed by TEM and the density dislocation was characterized by etching. According to the results of research, Ge component gradual changing buffer layer technology and low temperature Si buffer layer technology can both greatly reduce the threading dislocation density.
To get a better etch result, we did a lot of experiments by changing etching solution and etching time. We proposed the ideal of gradient etching .By this method ,we can do many experiments in one sample, determine the etching time with different layer structure easily,and it can improve the observe result of etching.
引文
[1] http:// www.intel.com/research/silicon/mooreslaw.htm
[2] www.intel.com
[3]曹培栋,晶体管原理与设计,电子工业出版社,2001.
[4]罗晋生,范永平,朱秉升,半导体导论第7版,西安电子科技大学出版社,1990:126.
[5]柯导明,陈军宁,高温CMOS集成电路原理与实现.第一版.中国科学技术大学出版社,2000:35.
[6]张凤言.电子电路基础:高性能模拟电路和电流模技术.第二版.高等教育出版社,1995:181.
[7]徐世六等,SiGe微电子技术,北京:国防工业出版社,2007.
[8]任冬玲等,延续摩尔定律的新材料应变硅,半导体技术,2005第32卷第8期, P650-652.
[9] Nobuyuki Sugii, Kiyokazu Nakagawa,Shinya Yamaguchi,et a1. Role of Sil-xGex buffer layer on mobility enhancement in a strained-Si n-channel metal-oxide semiconductor field effect transistor. Appl Phys Lett,1999,75(19):2948～2950.
[10] D. K. Nayak, J. C. S. Woo, J. S. Park, et a1. High-mobility p-channeI metal oxide-semiconductor field-effect transistor on strained Si. Appl Phys Lett,1993, 62(22):2853～2855.
[11] Sung Bae Park, Young Wug Kim, Young Gun Ko, Kwang Il Kim, Il Kwon Kim, Hee-Sung Kang, Jin Oh Yu, and Kwang Pyuk Suh. A 0.25-m, 600-MHz, 1.5-V, Fully depleted SOI CMOS 64-bit microprocessor. IEEE Journal of Solid State Circuits. 34(11): 1436-1445, 1999.
[12]于凌宇,21世纪高可靠性集成电路新技术应用展望,电子质量,2003,05期,P97.
[13] Calarco R, Fiordelisi M, Lagomarsino S, Scarinci F, Near-infrared metal-semiconductor-metal hotodetector integrated on silicon. Thin Solid Films, 2001, 391(1):138~142.
[14] T. Tczuka, N. Sugiyama, S. Takagi. Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction. Appl. Phys. Lett., 2001, 79(12):1798～1800.
[15] H. S. Yang,R. Malik,S. Narasimha,et a1. Dual stress liner for high performance sub-45 nm gate length SOI CMOS Manufacturing.International. Electron Devices Meeting Technical Digest,San Francisco,USA,2004:1075～1078.
[16] Nidhi Mohta,Scott E. Thompson. Mobility enhancement.IEEE circuits and Devices Magazine,2005,2l(5):18～23.
[17] B. M. Haugerud, L. A. Bosworth,and R. E. Belford. Mechanically induced strain enhancement of metal-oxide-semiconductor field effect transistors. Journal of Applied Physics,2003,94(6),4102～4107.
[18] B S Meyerson. Low temperature silicon epitaxy by ultrahigh vacuum-chemical vapordeposition, Appl. Phys. Lett., 1986, 48(12):797-799.
[19]唐伟忠,薄膜教材料制备原理、技术及应用第二版,2003.1.
[20] J.C.Bean and R.Hull. Misfit dislocations in strained layer epitaxy.II. Kinetics. Scripta Metallurgica et Materialia, 1992, 27(6): 663 ~ 715
[21] M T Currie, I B Samavedam, T A Langdo, et al. Controlling threading disloeation densities in Ge on Si using graded SiGe layers and ehemical-mechanical Polishing. Appl. Phys. Lett., 1998, 72:1718-1720.
[22] Luan Hsin-Chiao, R L Desmond, Kevin K.Lee, et al. High-quality Ge epilayers on Si with low threading-dislocation densities. Appl. Phys. Lett., 1999, 75:2909-2911.
[23] KRISHNA SARASWAT. How far can we push Si CMOS? What lies beyond? J. IEEE/SEMI Internation Semiconductor Manufacturing Science Symposium, 1993. 19-20: 1-5.
[24] S.E.Thompson.Key differences for process-induced uniaxial vs. substrate -induced biaxial stressed Si and Ge channel MOSFETs.In:IEDM Technical Digest. 2004.221
[25] J.Berntgen,A.Schueppen,P.Maier et all.SiGe Technology Bears Fruits, Materials Science and Engineering,2002, B89:1320.
[26] K.Goto, SSatoh, H.Ohta, Technology Booster using Strain-Enhancing Laminated SiN (SELS) for 65nm Node HP MPUs. IEDM 04,2004. IEDM 04-209- IEDM 04-212.
[27] C.W.Liu,S.Maikap,and Y.Yu.Mobility-Enhancement Technologies: Recent Progress using new materials,process-induced strain,and package strain.IEEE Circuits&Devices Magazine, 2005,21~36
[28] T.Ghani,M.Armstrong,et al.A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,In:IEDM Technical Digest.2003.978~980
[29] K.H.Vineyard,K.A.Gschneldner, Departures from Vegard’s Law.J ournal of applied Physics,1962,33(12)
[30]陈长春,余本海,刘江峰等,提升亚微米Si基CMOS器件性能的新技术应变Si技术、纳米器件与技术,p14-15,2005.
[31]周永溶,半导体材料,北京理工大学出版社,1992年
[32] [33]严群,冯庆芬.材料科学基础.国防工业出版社.第一版.2009:160-162.
[33]王亚男陈树江董希淳冶金工业出版社2007年3月
[34] J.W.Matthews. Accommodation of misfit across the interface betweensingle-crystal films of various face-centred cubic metals. Phil.Mag. 1966,13:1207~1221
[35] J.W.Matthews, S.Mader, T.B.Light. Accommodation of Misfit Across theInterface Between Crystals of Semiconducting Elements or Compounds. J. Appl. Phys. 1970, 41:3800~3804
[36]D.D.Perovic,G.C.Wealtherly,J.M.Baribeau,D.C.Houghton. Heterogeneousnucleation sourcesin molecular beam epitaxy-grown GexSi1-x/Si strainedlayer superlattices. Thin Solid Films. 1989, 183:141~156
[37] Legoues F K, Meyerson B S, Morar J F,et al. Mechanism and conditions for anomalous strain relaxation in graded thin films and super lattices. J Appl Phys, 1992,71:4230.
[38]金智、杨树人、安海岩、王本忠、赵方海、刘式墉,固体电子学研究与进展位错间的相互作用对应变外延层应变释放的影响。
[39]刘文西黄孝瑛陈玉如材料结构电子显微分析天津大学出版社1989年
[40]洛雷托,斯莫尔曼分析晶体缺陷的电子显微术上海科学技术出版社1979年
[2] www.intel.com
[3]曹培栋,晶体管原理与设计,电子工业出版社,2001.
[4]罗晋生,范永平,朱秉升,半导体导论第7版,西安电子科技大学出版社,1990:126.
[5]柯导明,陈军宁,高温CMOS集成电路原理与实现.第一版.中国科学技术大学出版社,2000:35.
[6]张凤言.电子电路基础:高性能模拟电路和电流模技术.第二版.高等教育出版社,1995:181.
[7]徐世六等,SiGe微电子技术,北京:国防工业出版社,2007.
[8]任冬玲等,延续摩尔定律的新材料应变硅,半导体技术,2005第32卷第8期, P650-652.
[9] Nobuyuki Sugii, Kiyokazu Nakagawa,Shinya Yamaguchi,et a1. Role of Sil-xGex buffer layer on mobility enhancement in a strained-Si n-channel metal-oxide semiconductor field effect transistor. Appl Phys Lett,1999,75(19):2948～2950.
[10] D. K. Nayak, J. C. S. Woo, J. S. Park, et a1. High-mobility p-channeI metal oxide-semiconductor field-effect transistor on strained Si. Appl Phys Lett,1993, 62(22):2853～2855.
[11] Sung Bae Park, Young Wug Kim, Young Gun Ko, Kwang Il Kim, Il Kwon Kim, Hee-Sung Kang, Jin Oh Yu, and Kwang Pyuk Suh. A 0.25-m, 600-MHz, 1.5-V, Fully depleted SOI CMOS 64-bit microprocessor. IEEE Journal of Solid State Circuits. 34(11): 1436-1445, 1999.
[12]于凌宇,21世纪高可靠性集成电路新技术应用展望,电子质量,2003,05期,P97.
[13] Calarco R, Fiordelisi M, Lagomarsino S, Scarinci F, Near-infrared metal-semiconductor-metal hotodetector integrated on silicon. Thin Solid Films, 2001, 391(1):138~142.
[14] T. Tczuka, N. Sugiyama, S. Takagi. Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction. Appl. Phys. Lett., 2001, 79(12):1798～1800.
[15] H. S. Yang,R. Malik,S. Narasimha,et a1. Dual stress liner for high performance sub-45 nm gate length SOI CMOS Manufacturing.International. Electron Devices Meeting Technical Digest,San Francisco,USA,2004:1075～1078.
[16] Nidhi Mohta,Scott E. Thompson. Mobility enhancement.IEEE circuits and Devices Magazine,2005,2l(5):18～23.
[17] B. M. Haugerud, L. A. Bosworth,and R. E. Belford. Mechanically induced strain enhancement of metal-oxide-semiconductor field effect transistors. Journal of Applied Physics,2003,94(6),4102～4107.
[18] B S Meyerson. Low temperature silicon epitaxy by ultrahigh vacuum-chemical vapordeposition, Appl. Phys. Lett., 1986, 48(12):797-799.
[19]唐伟忠,薄膜教材料制备原理、技术及应用第二版,2003.1.
[20] J.C.Bean and R.Hull. Misfit dislocations in strained layer epitaxy.II. Kinetics. Scripta Metallurgica et Materialia, 1992, 27(6): 663 ~ 715
[21] M T Currie, I B Samavedam, T A Langdo, et al. Controlling threading disloeation densities in Ge on Si using graded SiGe layers and ehemical-mechanical Polishing. Appl. Phys. Lett., 1998, 72:1718-1720.
[22] Luan Hsin-Chiao, R L Desmond, Kevin K.Lee, et al. High-quality Ge epilayers on Si with low threading-dislocation densities. Appl. Phys. Lett., 1999, 75:2909-2911.
[23] KRISHNA SARASWAT. How far can we push Si CMOS? What lies beyond? J. IEEE/SEMI Internation Semiconductor Manufacturing Science Symposium, 1993. 19-20: 1-5.
[24] S.E.Thompson.Key differences for process-induced uniaxial vs. substrate -induced biaxial stressed Si and Ge channel MOSFETs.In:IEDM Technical Digest. 2004.221
[25] J.Berntgen,A.Schueppen,P.Maier et all.SiGe Technology Bears Fruits, Materials Science and Engineering,2002, B89:1320.
[26] K.Goto, SSatoh, H.Ohta, Technology Booster using Strain-Enhancing Laminated SiN (SELS) for 65nm Node HP MPUs. IEDM 04,2004. IEDM 04-209- IEDM 04-212.
[27] C.W.Liu,S.Maikap,and Y.Yu.Mobility-Enhancement Technologies: Recent Progress using new materials,process-induced strain,and package strain.IEEE Circuits&Devices Magazine, 2005,21~36
[28] T.Ghani,M.Armstrong,et al.A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,In:IEDM Technical Digest.2003.978~980
[29] K.H.Vineyard,K.A.Gschneldner, Departures from Vegard’s Law.J ournal of applied Physics,1962,33(12)
[30]陈长春,余本海,刘江峰等,提升亚微米Si基CMOS器件性能的新技术应变Si技术、纳米器件与技术,p14-15,2005.
[31]周永溶,半导体材料,北京理工大学出版社,1992年
[32] [33]严群,冯庆芬.材料科学基础.国防工业出版社.第一版.2009:160-162.
[33]王亚男陈树江董希淳冶金工业出版社2007年3月
[34] J.W.Matthews. Accommodation of misfit across the interface betweensingle-crystal films of various face-centred cubic metals. Phil.Mag. 1966,13:1207~1221
[35] J.W.Matthews, S.Mader, T.B.Light. Accommodation of Misfit Across theInterface Between Crystals of Semiconducting Elements or Compounds. J. Appl. Phys. 1970, 41:3800~3804
[36]D.D.Perovic,G.C.Wealtherly,J.M.Baribeau,D.C.Houghton. Heterogeneousnucleation sourcesin molecular beam epitaxy-grown GexSi1-x/Si strainedlayer superlattices. Thin Solid Films. 1989, 183:141~156
[37] Legoues F K, Meyerson B S, Morar J F,et al. Mechanism and conditions for anomalous strain relaxation in graded thin films and super lattices. J Appl Phys, 1992,71:4230.
[38]金智、杨树人、安海岩、王本忠、赵方海、刘式墉,固体电子学研究与进展位错间的相互作用对应变外延层应变释放的影响。
[39]刘文西黄孝瑛陈玉如材料结构电子显微分析天津大学出版社1989年
[40]洛雷托,斯莫尔曼分析晶体缺陷的电子显微术上海科学技术出版社1979年