2Gbps高速通信解调技术及其实现研究
|
摘要
近年来,随着信息技术的发展,各领域对信息传输速率的要求从数百Mbps增长到了数Gbps甚至数十Gbps。研究表明,未来十年内需要的无线传输速率将达到5-15Gbps。然而目前的通信系统并不能提供足够高的数据传输速率以满足日益增长的高速数据传输需求。因此,本论文主要针对高码率调制信号的全并行解调技术及其硬件实现进行研究,以期突破高速解调中的全并行解调构架设计、并行定时同步、并行载波同步和并行自适应均衡等关键技术。
首先,完善了APRX构架为一种通用的完整全并行高速通信解调构架,该构架基于频域匹配滤波及定时相位误差旋转,复杂度较低,利于硬件实现,能以较低的时钟速率对高达数Gbps的通信信号进行解调。对作为构架核心的并行频域匹配滤波器进行了设计及并行实现简化。理论分析及仿真验证了算法的有效性。
其次,提出了基于相位滑动的频偏校正和频域相偏校正组成的并行定时同步算法。该算法通过索引变换及乘法即可实现并行定时同步,避免了反馈调节ADC采样时钟及复杂的插值操作。仿真表明该并行定时同步算法能以小于0.5dB的信噪比损失实现定时同步。
接着,在基于驰豫超前变换的并行自适应滤波算法基础上,利用延时近似技术,提出了自适应CMA盲均衡算法的基于短卷积的流水线高效并行实现构架,并进行了FPGA实现,最后对该并行均衡算法进行了仿真验证。
然后,将鉴频鉴相算法中的矩形窗改进为环形窗,并与全相位域数字锁相环结合,提出了一种基于环形窗的全相位域判决反馈锁相环载波同步算法。针对该算法的并行实现,设计了一种简单有效的基于平均等量补偿的结构并完成了FPGA实现。对整个并行解调系统进行的定点仿真表明本并行解调构架的定点解调性能损失小于1dB。
最后,基于提出的解调构架及算法研制了高速解调原理样机,并对整个并行解调构架及算法进行了FPGA实现。对样机的性能测试表明,在无信道编译码情况下,样机的整体解调信噪比损失小于2dB,验证了提出的解调构架及算法的高效性。本文还利用该解调样机进行了140GHz上的35m、500m、1.5km的无线传输实验,得到的无线传输误码率分别达到了10-10量级、10-9量级、10-7量级。
As the development of communication technology in decades, demand for very highdata rate wireless communication in all areas is growing rapidly, from several hundredMegabits per second (Mbps) to multi-Gigabits per second (Gbps). Research shows thatdata rates of around5-15Gbps will be required in next ten years. However, existing com-munication systems cannot provide data rates that are high enough to meet the increasingrequirement in high-speed data transmission. This thesis conducts a research on highdata rate parallel demodulation and its FPGA implementation, looking forward to makebreakthrough in the critical issue of high data rate demodulation, such as parallel demod-ulation architecture, parallel timing synchronization, parallel carrier synchronization andparallel adaptive equalization.
First, this thesis improves APRX parallel demodulation architecture to a universalcomplete high-speed fully parallel demodulation architecture. Based on frequency do-main matched fltering and timing phase error rotation, this architecture can easily im-plemented to demodulate modulated signal as high as multi-Gbps with very low clockfrequency and low hardware cost. In the thesis, we design the kernel of the architec-ture, a parallel frequency domain matched flter, and simplifes its parallel process. Boththeoretic analyzing and simulation demonstrate the efectiveness of the architecture.
Second, this thesis proposes parallel timing synchronization algorithm, which con-sists of phase shift based approach to timing frequency ofset correction and frequencydomain timing phase ofset correction. The algorithm can avoid feedback regulation forADC clock and complicated interpolation, since it can be realized simply through in-dex transformation and multiplication. Simulations show that the algorithm can achievetiming synchronization with less than0.5dB SNR loss.
Third, by introducing delay relaxation into relaxed look-ahead adaptive flter, thethesis develops a short convolution based, efective pipelined parallel implementationstructure of adaptive CMA blind equalization algorithm. FPGA implementation and sim-ulations of the algorithm are also conducted.
Moreover, this thesis improves Phase and Frequency Detector (PFD) based on ringwindow instead of rectangle window in previous work. Combining PFD and phase do-main digital PLL, the thesis presents a ring window-based all-phase domain Decision- Directed PLL for carrier synchronization. On account of its parallel realization, the thesisdesigns a simple but efective mean-equivalent-compensation-based structure, and furtheraccomplishes its FPGA implementation. The fxed-point simulation on the whole systemshows that the demodulation performance loss of the parallel demodulation architectureis just less than1dB.
Finally, based on the proposed demodulation architecture and algorithms, the thesisdevelops a high data rate demodulator prototype, the parallel demodulation architectureand algorithms are implemented on the prototype. The performance test of the prototypeindicates that, without channel code/decode, the overall SNR loss of the prototype is lessthan2dB, which validates the efciency of the proposed demodulation architecture andalgorithms. Wireless communication experiments of the prototype on140GHz, at thedistance of35m,500m and1.5km are also conducted. The achieved BER is down to theorder of1010,109and107separately.
首先,完善了APRX构架为一种通用的完整全并行高速通信解调构架,该构架基于频域匹配滤波及定时相位误差旋转,复杂度较低,利于硬件实现,能以较低的时钟速率对高达数Gbps的通信信号进行解调。对作为构架核心的并行频域匹配滤波器进行了设计及并行实现简化。理论分析及仿真验证了算法的有效性。
其次,提出了基于相位滑动的频偏校正和频域相偏校正组成的并行定时同步算法。该算法通过索引变换及乘法即可实现并行定时同步,避免了反馈调节ADC采样时钟及复杂的插值操作。仿真表明该并行定时同步算法能以小于0.5dB的信噪比损失实现定时同步。
接着,在基于驰豫超前变换的并行自适应滤波算法基础上,利用延时近似技术,提出了自适应CMA盲均衡算法的基于短卷积的流水线高效并行实现构架,并进行了FPGA实现,最后对该并行均衡算法进行了仿真验证。
然后,将鉴频鉴相算法中的矩形窗改进为环形窗,并与全相位域数字锁相环结合,提出了一种基于环形窗的全相位域判决反馈锁相环载波同步算法。针对该算法的并行实现,设计了一种简单有效的基于平均等量补偿的结构并完成了FPGA实现。对整个并行解调系统进行的定点仿真表明本并行解调构架的定点解调性能损失小于1dB。
最后,基于提出的解调构架及算法研制了高速解调原理样机,并对整个并行解调构架及算法进行了FPGA实现。对样机的性能测试表明,在无信道编译码情况下,样机的整体解调信噪比损失小于2dB,验证了提出的解调构架及算法的高效性。本文还利用该解调样机进行了140GHz上的35m、500m、1.5km的无线传输实验,得到的无线传输误码率分别达到了10-10量级、10-9量级、10-7量级。
As the development of communication technology in decades, demand for very highdata rate wireless communication in all areas is growing rapidly, from several hundredMegabits per second (Mbps) to multi-Gigabits per second (Gbps). Research shows thatdata rates of around5-15Gbps will be required in next ten years. However, existing com-munication systems cannot provide data rates that are high enough to meet the increasingrequirement in high-speed data transmission. This thesis conducts a research on highdata rate parallel demodulation and its FPGA implementation, looking forward to makebreakthrough in the critical issue of high data rate demodulation, such as parallel demod-ulation architecture, parallel timing synchronization, parallel carrier synchronization andparallel adaptive equalization.
First, this thesis improves APRX parallel demodulation architecture to a universalcomplete high-speed fully parallel demodulation architecture. Based on frequency do-main matched fltering and timing phase error rotation, this architecture can easily im-plemented to demodulate modulated signal as high as multi-Gbps with very low clockfrequency and low hardware cost. In the thesis, we design the kernel of the architec-ture, a parallel frequency domain matched flter, and simplifes its parallel process. Boththeoretic analyzing and simulation demonstrate the efectiveness of the architecture.
Second, this thesis proposes parallel timing synchronization algorithm, which con-sists of phase shift based approach to timing frequency ofset correction and frequencydomain timing phase ofset correction. The algorithm can avoid feedback regulation forADC clock and complicated interpolation, since it can be realized simply through in-dex transformation and multiplication. Simulations show that the algorithm can achievetiming synchronization with less than0.5dB SNR loss.
Third, by introducing delay relaxation into relaxed look-ahead adaptive flter, thethesis develops a short convolution based, efective pipelined parallel implementationstructure of adaptive CMA blind equalization algorithm. FPGA implementation and sim-ulations of the algorithm are also conducted.
Moreover, this thesis improves Phase and Frequency Detector (PFD) based on ringwindow instead of rectangle window in previous work. Combining PFD and phase do-main digital PLL, the thesis presents a ring window-based all-phase domain Decision- Directed PLL for carrier synchronization. On account of its parallel realization, the thesisdesigns a simple but efective mean-equivalent-compensation-based structure, and furtheraccomplishes its FPGA implementation. The fxed-point simulation on the whole systemshows that the demodulation performance loss of the parallel demodulation architectureis just less than1dB.
Finally, based on the proposed demodulation architecture and algorithms, the thesisdevelops a high data rate demodulator prototype, the parallel demodulation architectureand algorithms are implemented on the prototype. The performance test of the prototypeindicates that, without channel code/decode, the overall SNR loss of the prototype is lessthan2dB, which validates the efciency of the proposed demodulation architecture andalgorithms. Wireless communication experiments of the prototype on140GHz, at thedistance of35m,500m and1.5km are also conducted. The achieved BER is down to theorder of1010,109and107separately.
引文
[1] Lansing F, Lemmerman L, Walton A, et al. Needs for Communications and Onboard Process-ing in the Vision Era. Proceedings of2002IEEE International Geoscience and Remote SensingSymposium,2002.375–377.
[2] Cherry S. Edholm’s law of bandwidth. IEEE Spectrum,2004,41(7):58–60.
[3] Hirata A, Kosugi T, Takahashi H, et al.120-GHz-Band Millimeter-Wave Photonic WirelessLink for10-Gb/s Data Transmission. IEEE Transactions on Microwave Theory and Tech-niques,2006,54(5):1937–1944.
[4] Hirata A, Nagatsuma T, Kosugi T, et al.10-Gbit/s Wireless Communications TechnologyUsing Sub-terahertz Waves. Proceedings of Proc. of SPIE on Terahertz Physics, Devices, andSystems II,2007.67720B.
[5] Kosugi T, Shibata T, Enoki T, et al. A120-GHz millimeter-wave MMIC chipset for futurebroadband wireless access applications. Proceedings of Microwave Symposium Digest,2003IEEE MTT-S International,2003.129–132.
[6] Kosugi T, Tokumitsu M, Enoki T, et al.120-GHz Tx/Rx chipset for10-Gbit/s wireless appli-cations using0.1-um-gate InP HEMTs. Proceedings of2004IEEE compound semiconductorIntegrated Circuit Symposium,2004.171–174.
[7] Kosugi T, Tokumitsu M, Murata K, et al.120-GHz Tx/Rx Waveguide Modules for10-Gbit/sWireless Link System. Proceedings of2006IEEE Compound Semiconductor Integrated Cir-cuit Symposium,2006.25–28.
[8] Yamaguchi R, Hirata A, Kosugi T, et al.10-Gbit/s MMIC Wireless Link Exceeding800meters.Proceedings of2008IEEE Radio and Wireless Symposium,2008.695–698.
[9] Takahashi H, Kosugi T, Hirata A, et al.120-GHz-band BPSK modulator and demodulator for10-Gbit/s data transmission. Proceedings of2009IEEE International Microwave Symposium,2009.557–560.
[10] DigitalGlobe. QuickBird Spacecraft Data Sheet,2009. http://www.digitalglobe.com/index.php/85/QuickBird.
[11] DigitalGlobe. WorldView-2Spacecraft Data Sheet,2009. http://www.digitalglobe.com/index.php/88/WorldView-2.
[12] GeoEye. GeoEye-1Fact Sheet,2010. http://launch.geoeye.com/LaunchSite/about/fact sheet.aspx.
[13] NASA. New Series of Tracking and Data Relay Satellites Replenishing The Original Fleet.Technical report, NASA Goddard Space Flight Center, November27,2002. http://www.gsfc.nasa.gov/topstory/20021127tdrs j.html.
[14] Kumar R, Taggart D, Monzingo R, et al. Wideband Gapfller Satellite (WGS) System. Pro-ceedings of Proceedings of the2005IEEE Aerospace Conference, Big Sky, Montana,2005.
[15] Benedetto S, Garello R, Montorsi G, et al. MHOMS: high-speed ACM modem for satelliteapplications. IEEE Wireless Communications,2005,12(2):66–77.
[16] Ogawa Y, Hashimoto Y, Yoshimura N, et al.622Mbps High-speed satellite communicationsystem for WINDS. Acta Astronautica,2006,59(1-5):96–99.
[17] Kifle M, Bizon T P, Nguyen N T, et al. Implementation of a622Mbps OFDM digital modem.Proceedings of20th AIAA International Communication Satellite Systems Conference andExhibit, Montreal, Quebec, Canada,2002.
[18] Krstic M, Piz M, Ehrig M, et al. OFDM Datapath Baseband Processor for1Gbps Datarate.Proceedings of Proc. IFIP/IEEE VLSI-SoC Conference, Rhodes Island, Greece,2008.156–159.
[19] Piz M, Krstic M, Ehrig M, et al. An OFDM baseband receiver for short-range communicationat60GHz. Proceedings of2009IEEE International Symposium on Circuits and Systems,ISCAS2009, Proceedings, Taipei, Taiwan,2009.409–412.
[20] Choi C S, Grass E, Piz M, et al.60-Ghz OFDM Systems for Multi-Gigabit Wireless LANApplications. Proceedings of20107th IEEE Consumer Communications and NetworkingConference, CCNC2010, Las Vegas, NV, United states,2010.
[21] Thompson M, Jones W. An all Digital650-Mbps Demonstration Receiver for NASA’s HighData Rate Satellite Applications. Proceedings of IEEE Military Communications Conference,1992.194–198.
[22] Sadr R, Vaidyanathan P P, Raphaeli D, et al. Parallel Digital Modem Using Multirate DigitalFilter Banks. JPL Publication94-20, Jet Propulsion Laboratory, NASA, August15,1994.
[23] Srinivasan M, Chen C C, Grebowsky G, et al. An All-Digital, High Data-Rate Parallel Receiver.TDA Progress Report42-131, Jet Propulsion Laboratory, NASA, November15,1997. http://ipnpr.jpl.nasa.gov/progress report/42-131/title.htm.
[24] Gray A A. Parallel Sub-Convolution Filter Bank Architectures. Proceedings of IEEE Interna-tional Symposium on Circuits and Systems, Bangkok, Thailand,2003.
[25] Gray A A, Hoy S D. Parallel Adaptive Equalizer Employing Sub-Convolution: VLSI Archi-tecture Realized in a Field Programmable Gate Array. Proceedings of MAPLD InternationalConference,2003.
[26] Gray A A, Hoy S D, Ghuman P. Adaptive LMS processing architectures employing frequencydomain sub-convolution. Proceedings of Proceedings of the2004International Symposium onCircuits and Systems,2004. III617–620.
[27] Ghuman P, Sheikh S, Koubek S, et al. High Rate Digital Demodulator ASIC. Technical report,Goddard Space Flight Center, NASA,1998. http://ntrs.larc.nasa.gov.
[28] Grebowsky G J, Gray A A, Srinivasan M. Method and Apparatus for High Data Rate Demod-ulation. US Patent6,177,835,2001.
[29] Gray A, Srinivasan M, Simon M, et al. Flexible All-Digital Receiver for Bandwidth EfcientModulations. Technical report, Jet Propulsion Laboratory, NASA,2000. http://ntrs.larc.nasa.gov.
[30]Springett J C. Achieving Future Space Very Long Baseline Interferometry Gigabits-per-Second Data Rates. IPN Progress Report42-149, Jet Propulsion Laboratory, NASA, May15,2002. http://ipnpr.jpl.nasa.gov.
[31]Oncu A, Fujishima M.19.2mW2Gbps CMOS pulse receiver for60GHz band wireless com-munication. Proceedings of2008IEEE Symposium on VLSI Circuits,2008.158-159.
[32]Juntunen E, Leung M C H, Barale F, et al. A60-GHz38-pJ/bit3.5-Gb/s90-nm CMOS OOK Digital Radio. IEEE Transactions on Microwave Theory and Techniques,2010,58(2):348-355.
[33]Lee J, Chen Y, Huang Y. A Low-Power Low-Cost Fully-Integrated60-GHz Transceiver Sys-tem With OOK Modulation and On-Board Antenna Assembly. IEEE Journal of Solid-State Circuits,2010,45(2):264-275.
[34]Maruhashi K, Tanomura M, Hamada Y, et al.60-GHz-Band CMOS MMIC Technology for High-Speed Wireless Personal Area Networks. Proceedings of IEEE Compound Semiconduc-tor Integrated Circuits Symposium, CSIC'08.,2008.1-4.
[35]Pinel S, Sen P, Sarkar S, et al.60GHz single-chip CMOS digital radios and phased array solutions for gaming and connectivity. IEEE Journal on Selected Areas in Communications,2009,27(8):1347-1357.
[36]Sarkas I, Nicolson S T, Tomkins A, et al. A12-Gb/s, Direct QPSK Modulation SiGe BiC-MOS Transceiver for Last Mile Links in the70-80GHz Band. Proceedings of Annual IEEE Compound Semiconductor Integrated Circuit Symposium, CISC2009,2009.1-4.
[37]Dyadyuk V, Bunton J D, Pathikulangara J, et al. A Multigigabit Millimeter-Wave Communi-cation System With Improved Spectral Efficiency. IEEE Transactions on Microwave Theory and Techniques,2007,55(12):2813-2821.
[38]Dyadyuk V, Sevimli O, Bunton J, et al. A6Gbps Millimetre Wave Wireless Link with2.4bit/Hz Spectral Efficiency. Proceedings of Proceedings of the2007IEEE/MTT-S International Microwave Symposium, Honolulu, Hawaii,2007.471-474.
[39]Zodiac Data Systems. High Data Rate Receiver Cortex Series HDR-XXL User's Manual. La Teste:Zodiac Aerospace,2009.
[40]RT Logic. TELEMETRIX1200HIGH DATA RATE. Denver:Real Time Logic Inc.,2009.
[41]梁侠800Mbps高速数传接收机匹配滤波及定时恢复的研究和实现[硕士学位论文].长沙：国防科学技术大学,2007.
[42]杨军.高速数据传输中的TCM技术研究及其应用[博士学位论文].长沙：国防科学技术大学,2005.
[43]姜波.中继卫星数据传输系统的载波同步与信道均衡技术研究[博士学位论文].长沙：国防科学技术大学,2008.
[44]童长海,郑雪峰,郑戈,等.600Mb/s高速数传接收机的设计与实现.遥测遥控,2007,28(增刊)：30-34.
[45]陈大海.中频数字收发信机的研究与系统实现[博士学位论文].成都：电子科技大学,2008.
[46]翟海涛.高速数传系统中匹配滤波及定时同步算法改进及实现研究[硕士学位论文].长沙：国防科学技术大学,2009.
[47]陈晖,易克初,李文铎.高速数字解调中的并行处理算法.电子科技大学学报,2010,39(3)：340-345.
[48]Chen Z, Zhan Y, Lu J. A High Data-Rate Software Defined Radio Receiver Suited for FPGA Platforms. China Communications,2009,(1):73-77.
[49]郭晓峰,郑雪峰,卢满宏,等.高速数传QAM解调器设计及应用.遥测遥控,2011,32(3)：21-25.
[50]邓贤进,王成,林长星,等.0.14THz超高速无线通信系统实验研究.强激光与粒子束,2011,23(6)：1430-1432.
[51]Shannon C E. A Mathematical Theory of Communication. The Bell System Technical Journal,1948,27:379-423,623-656.
[52]Ungerboeck G. Trellis-coded modulation with redundant signal sets Part Ⅰ:introduction. IEEE Communications Magazine,1987,25(2):5-11.
[53]Berrou C, Glavieux A, Thitimajshima P. Near Shannon limit error-correcting coding and de-coding:Turbo-codes.1. Proceedings of Communications,1993. ICC93. Geneva. Technical Program, Conference Record, IEEE International Conference on, volume2, Geneva, Switzer-land,1993.1064-1070.
[54]Gallager R G. Low Density Parity Check Codes. Monograph:M.I.T. Press,1963.
[55]MacKay D, Neal R. Near Shannon Limit Performance of Low Density Parity Check Codes. Electronics Letters,1996,32:1645-1646.
[56]Vaughan R G, Scott N L, White D R. The Theory of Bandpass Sampling. IEEE Transactions on Signal Processing,1991,39(9):1973-1984.
[57]Mengali U, D'Andrea A N. Synchronization Techniques for Digital Receivers. New York: Plenum Press,1997.
[58]Proakis J G. Digital Communications. Fourth ed., McGraw-Hill Science/Engineering/Math,2000.
[59]吕洪生,杨新德.实用卫星通信工程.成都：电子科技大学出版社,1994.
[60]Xilinx. Virtex-6FPGA SelectIO Resources User Guide,2010. UG361(v1.3).
[61]曹志刚,钱亚生.现代通信原理.北京：清华大学出版社,2007.
[62]应启珩,冯一云,窦维蓓.离散时间信号分析和处理.北京：清华大学出版社,2001.
[63]Xilinx. Virtex-6FPGA DSP48E1Slice User Guide, September,2009. UG369(v1.2).
[64]Sklar B. Digital Communications:Fundamentals and Applications. Second ed., Prentice Hall PTR,2001.
[65]Gardner F M. Interpolation in Digital Modems—Part Ⅰ:Fundamentals. IEEE Transactions on Communications,1993,41(3):501-507.
[66]Erup L, Gardner F M, Harris R A. Interpolation in Digital Modems—Part Ⅱ:Implementation and Performance. IEEE Transactions on Communications,1993,41(6):998-1008.
[67]Gardner F M. A BPSK/QPSK Timing-Error Detector for Sampled Receivers. IEEE Transac-tions on Communications,1986, COM-34(5):423-429.
[68]Oerder M, Meyr H. Digital Filter and Square Timing Recovery. IEEE Transactions on Com-munications,1988,36(5):605-612.
[69]郑大春,项海格.一种全数字QAM接收机符号定时和载波相位恢复方案.通信学报,1998,19(7)：83-88.
[70]郑君里,应启珩,杨为理.信号与系统.北京：高等教育出版社,2000.
[71]Xilinx. CORDIC v4.0Product Specification, April,2009. DS249.
[72]Yang J, Werner J J, Dumont G A. The Multimodulus Blind Equalization and Its Generalized Algorithms. IEEE Journal on Selected Areas in Communications,2002,20(5):997-1015.
[73]He L, Amin M G, Reed C, et al. A hybrid adaptive blind equalization algorithm for QAM sig-nals in wireless communications. IEEE Transactions on Signal Processing,2004,52(7):2058-2069.
[74]Banovic K, Abdel-Raheem E, Khalid M A S. Hybrid methods for blind adaptive equalization: New results and comparisons. Proceedings of Proceedings of the10th IEEE Symposium on Computers and Communications,2005.
[75]Banovic K, Abdel-Raheem E, Khalid M A S. A novel radius-adjusted approach for blind adaptive equalization. IEEE Signal Processing Letters,2006,13(1):37-40.
[76]Banovic K, Khalid M A S, Abdel-Raheem E. A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators. Digital Signal Processing,2007,17:1071-1088.
[77]Parhi K K. VLSI Digital Signal Processing Systems:Design and Implementation. New York: Wiley,1999.
[78]Shanbhag N R, Parhi K K. Relaxed look-ahead pipelined LMS adaptive filters and their appli-cation to ADPCM coder. IEEE Transactions on Circuits and Systems—Ⅱ: Analog and Digital Signal Processing,1993,40(12):753-766.
[79]Granata J, Conner M, Tolimieri R. A Tensor Product Factorization of the Linear Convolution. IEEE Transactions on Circuits and Systems,1991,38(11):1364-1366.
[80]Granata J, Conner M, Tolimieri R. The Tensor Product:A Mathematical Programming Lan-guage for FFTs and other Fast DSP Operations. IEEE Signal Processing Magazine,1992,9(1):40-48.
[81]Cheng C, Parhi K K. Hardware efficient fast parallel FIR filter structures based on iterated short convolution. Proceedings of Circuits and Systems,2004. ISC AS'04. Proceedings of the2004International Symposium on,2004.
[82]Cheng C, Parhi K K. Hardware efficient fast parallel FIR filter structures based on iterat-ed short convolution. IEEE Transactions on Circuits and Systems—Ⅰ: Regular Papers,2004,51(8):1492-1500.
[83]Cheng C, Parhi K K. Low Cost Parallel Adaptive Filter Structures. Proceedings of Conference Record of the39th Asilomar Conference on Signals, Systems and Computers,2005.354-358.
[84]http://spib.rice.edu/.
[85]季仲梅,杨洪生,王大鸣,等.通信中的同步技术及应用.北京：清华大学出版社,2008.
[86]Shayan Y, Le-Ngoc T. All digital phase-locked loop:concepts, design and applications. IEE Proceedings F on Radar and Signal Processing,1989,136(1):53-56.
[87]Jablon N K. Joint Blind Equalization, Carrier Recovery and Timing Recovery for High-Order QAM Signal Constellations. IEEE Transactions on Signal Processing,1992,40(6):1383-1398.
[88]Kim K Y, Choi H J. Design of Carrier Recovery Algorithm for High-Order QAM with Large Frequence Acquisition Range. Proceedings of IEEE International Conference on Communica-tions,2001.1016-1020.
[89]Sari H, Moridi S. New Phase and Frequency Detectors for Carrier Recovery in PSK and QAM Systems. IEEE Transactions on Communications,1988,36(9):1035-1043.
[90]中华人民共和国广播电影电视行业标准GY/T170-2001.有线数字电视广播信道编码与调制规范.国家广播电影电视总局,2001.
[91]National Semiconductor. ADC10D1000/ADC10D1500Low Power,10-Bit, Dual1.0/1.5GSP-S or Single2.0/3.0GSPS ADC,2011.
[92]National Semiconductor. LMX2531High Performance Frequency Synthesizer System with Integrated VCO, September,2010.
[2] Cherry S. Edholm’s law of bandwidth. IEEE Spectrum,2004,41(7):58–60.
[3] Hirata A, Kosugi T, Takahashi H, et al.120-GHz-Band Millimeter-Wave Photonic WirelessLink for10-Gb/s Data Transmission. IEEE Transactions on Microwave Theory and Tech-niques,2006,54(5):1937–1944.
[4] Hirata A, Nagatsuma T, Kosugi T, et al.10-Gbit/s Wireless Communications TechnologyUsing Sub-terahertz Waves. Proceedings of Proc. of SPIE on Terahertz Physics, Devices, andSystems II,2007.67720B.
[5] Kosugi T, Shibata T, Enoki T, et al. A120-GHz millimeter-wave MMIC chipset for futurebroadband wireless access applications. Proceedings of Microwave Symposium Digest,2003IEEE MTT-S International,2003.129–132.
[6] Kosugi T, Tokumitsu M, Enoki T, et al.120-GHz Tx/Rx chipset for10-Gbit/s wireless appli-cations using0.1-um-gate InP HEMTs. Proceedings of2004IEEE compound semiconductorIntegrated Circuit Symposium,2004.171–174.
[7] Kosugi T, Tokumitsu M, Murata K, et al.120-GHz Tx/Rx Waveguide Modules for10-Gbit/sWireless Link System. Proceedings of2006IEEE Compound Semiconductor Integrated Cir-cuit Symposium,2006.25–28.
[8] Yamaguchi R, Hirata A, Kosugi T, et al.10-Gbit/s MMIC Wireless Link Exceeding800meters.Proceedings of2008IEEE Radio and Wireless Symposium,2008.695–698.
[9] Takahashi H, Kosugi T, Hirata A, et al.120-GHz-band BPSK modulator and demodulator for10-Gbit/s data transmission. Proceedings of2009IEEE International Microwave Symposium,2009.557–560.
[10] DigitalGlobe. QuickBird Spacecraft Data Sheet,2009. http://www.digitalglobe.com/index.php/85/QuickBird.
[11] DigitalGlobe. WorldView-2Spacecraft Data Sheet,2009. http://www.digitalglobe.com/index.php/88/WorldView-2.
[12] GeoEye. GeoEye-1Fact Sheet,2010. http://launch.geoeye.com/LaunchSite/about/fact sheet.aspx.
[13] NASA. New Series of Tracking and Data Relay Satellites Replenishing The Original Fleet.Technical report, NASA Goddard Space Flight Center, November27,2002. http://www.gsfc.nasa.gov/topstory/20021127tdrs j.html.
[14] Kumar R, Taggart D, Monzingo R, et al. Wideband Gapfller Satellite (WGS) System. Pro-ceedings of Proceedings of the2005IEEE Aerospace Conference, Big Sky, Montana,2005.
[15] Benedetto S, Garello R, Montorsi G, et al. MHOMS: high-speed ACM modem for satelliteapplications. IEEE Wireless Communications,2005,12(2):66–77.
[16] Ogawa Y, Hashimoto Y, Yoshimura N, et al.622Mbps High-speed satellite communicationsystem for WINDS. Acta Astronautica,2006,59(1-5):96–99.
[17] Kifle M, Bizon T P, Nguyen N T, et al. Implementation of a622Mbps OFDM digital modem.Proceedings of20th AIAA International Communication Satellite Systems Conference andExhibit, Montreal, Quebec, Canada,2002.
[18] Krstic M, Piz M, Ehrig M, et al. OFDM Datapath Baseband Processor for1Gbps Datarate.Proceedings of Proc. IFIP/IEEE VLSI-SoC Conference, Rhodes Island, Greece,2008.156–159.
[19] Piz M, Krstic M, Ehrig M, et al. An OFDM baseband receiver for short-range communicationat60GHz. Proceedings of2009IEEE International Symposium on Circuits and Systems,ISCAS2009, Proceedings, Taipei, Taiwan,2009.409–412.
[20] Choi C S, Grass E, Piz M, et al.60-Ghz OFDM Systems for Multi-Gigabit Wireless LANApplications. Proceedings of20107th IEEE Consumer Communications and NetworkingConference, CCNC2010, Las Vegas, NV, United states,2010.
[21] Thompson M, Jones W. An all Digital650-Mbps Demonstration Receiver for NASA’s HighData Rate Satellite Applications. Proceedings of IEEE Military Communications Conference,1992.194–198.
[22] Sadr R, Vaidyanathan P P, Raphaeli D, et al. Parallel Digital Modem Using Multirate DigitalFilter Banks. JPL Publication94-20, Jet Propulsion Laboratory, NASA, August15,1994.
[23] Srinivasan M, Chen C C, Grebowsky G, et al. An All-Digital, High Data-Rate Parallel Receiver.TDA Progress Report42-131, Jet Propulsion Laboratory, NASA, November15,1997. http://ipnpr.jpl.nasa.gov/progress report/42-131/title.htm.
[24] Gray A A. Parallel Sub-Convolution Filter Bank Architectures. Proceedings of IEEE Interna-tional Symposium on Circuits and Systems, Bangkok, Thailand,2003.
[25] Gray A A, Hoy S D. Parallel Adaptive Equalizer Employing Sub-Convolution: VLSI Archi-tecture Realized in a Field Programmable Gate Array. Proceedings of MAPLD InternationalConference,2003.
[26] Gray A A, Hoy S D, Ghuman P. Adaptive LMS processing architectures employing frequencydomain sub-convolution. Proceedings of Proceedings of the2004International Symposium onCircuits and Systems,2004. III617–620.
[27] Ghuman P, Sheikh S, Koubek S, et al. High Rate Digital Demodulator ASIC. Technical report,Goddard Space Flight Center, NASA,1998. http://ntrs.larc.nasa.gov.
[28] Grebowsky G J, Gray A A, Srinivasan M. Method and Apparatus for High Data Rate Demod-ulation. US Patent6,177,835,2001.
[29] Gray A, Srinivasan M, Simon M, et al. Flexible All-Digital Receiver for Bandwidth EfcientModulations. Technical report, Jet Propulsion Laboratory, NASA,2000. http://ntrs.larc.nasa.gov.
[30]Springett J C. Achieving Future Space Very Long Baseline Interferometry Gigabits-per-Second Data Rates. IPN Progress Report42-149, Jet Propulsion Laboratory, NASA, May15,2002. http://ipnpr.jpl.nasa.gov.
[31]Oncu A, Fujishima M.19.2mW2Gbps CMOS pulse receiver for60GHz band wireless com-munication. Proceedings of2008IEEE Symposium on VLSI Circuits,2008.158-159.
[32]Juntunen E, Leung M C H, Barale F, et al. A60-GHz38-pJ/bit3.5-Gb/s90-nm CMOS OOK Digital Radio. IEEE Transactions on Microwave Theory and Techniques,2010,58(2):348-355.
[33]Lee J, Chen Y, Huang Y. A Low-Power Low-Cost Fully-Integrated60-GHz Transceiver Sys-tem With OOK Modulation and On-Board Antenna Assembly. IEEE Journal of Solid-State Circuits,2010,45(2):264-275.
[34]Maruhashi K, Tanomura M, Hamada Y, et al.60-GHz-Band CMOS MMIC Technology for High-Speed Wireless Personal Area Networks. Proceedings of IEEE Compound Semiconduc-tor Integrated Circuits Symposium, CSIC'08.,2008.1-4.
[35]Pinel S, Sen P, Sarkar S, et al.60GHz single-chip CMOS digital radios and phased array solutions for gaming and connectivity. IEEE Journal on Selected Areas in Communications,2009,27(8):1347-1357.
[36]Sarkas I, Nicolson S T, Tomkins A, et al. A12-Gb/s, Direct QPSK Modulation SiGe BiC-MOS Transceiver for Last Mile Links in the70-80GHz Band. Proceedings of Annual IEEE Compound Semiconductor Integrated Circuit Symposium, CISC2009,2009.1-4.
[37]Dyadyuk V, Bunton J D, Pathikulangara J, et al. A Multigigabit Millimeter-Wave Communi-cation System With Improved Spectral Efficiency. IEEE Transactions on Microwave Theory and Techniques,2007,55(12):2813-2821.
[38]Dyadyuk V, Sevimli O, Bunton J, et al. A6Gbps Millimetre Wave Wireless Link with2.4bit/Hz Spectral Efficiency. Proceedings of Proceedings of the2007IEEE/MTT-S International Microwave Symposium, Honolulu, Hawaii,2007.471-474.
[39]Zodiac Data Systems. High Data Rate Receiver Cortex Series HDR-XXL User's Manual. La Teste:Zodiac Aerospace,2009.
[40]RT Logic. TELEMETRIX1200HIGH DATA RATE. Denver:Real Time Logic Inc.,2009.
[41]梁侠800Mbps高速数传接收机匹配滤波及定时恢复的研究和实现[硕士学位论文].长沙：国防科学技术大学,2007.
[42]杨军.高速数据传输中的TCM技术研究及其应用[博士学位论文].长沙：国防科学技术大学,2005.
[43]姜波.中继卫星数据传输系统的载波同步与信道均衡技术研究[博士学位论文].长沙：国防科学技术大学,2008.
[44]童长海,郑雪峰,郑戈,等.600Mb/s高速数传接收机的设计与实现.遥测遥控,2007,28(增刊)：30-34.
[45]陈大海.中频数字收发信机的研究与系统实现[博士学位论文].成都：电子科技大学,2008.
[46]翟海涛.高速数传系统中匹配滤波及定时同步算法改进及实现研究[硕士学位论文].长沙：国防科学技术大学,2009.
[47]陈晖,易克初,李文铎.高速数字解调中的并行处理算法.电子科技大学学报,2010,39(3)：340-345.
[48]Chen Z, Zhan Y, Lu J. A High Data-Rate Software Defined Radio Receiver Suited for FPGA Platforms. China Communications,2009,(1):73-77.
[49]郭晓峰,郑雪峰,卢满宏,等.高速数传QAM解调器设计及应用.遥测遥控,2011,32(3)：21-25.
[50]邓贤进,王成,林长星,等.0.14THz超高速无线通信系统实验研究.强激光与粒子束,2011,23(6)：1430-1432.
[51]Shannon C E. A Mathematical Theory of Communication. The Bell System Technical Journal,1948,27:379-423,623-656.
[52]Ungerboeck G. Trellis-coded modulation with redundant signal sets Part Ⅰ:introduction. IEEE Communications Magazine,1987,25(2):5-11.
[53]Berrou C, Glavieux A, Thitimajshima P. Near Shannon limit error-correcting coding and de-coding:Turbo-codes.1. Proceedings of Communications,1993. ICC93. Geneva. Technical Program, Conference Record, IEEE International Conference on, volume2, Geneva, Switzer-land,1993.1064-1070.
[54]Gallager R G. Low Density Parity Check Codes. Monograph:M.I.T. Press,1963.
[55]MacKay D, Neal R. Near Shannon Limit Performance of Low Density Parity Check Codes. Electronics Letters,1996,32:1645-1646.
[56]Vaughan R G, Scott N L, White D R. The Theory of Bandpass Sampling. IEEE Transactions on Signal Processing,1991,39(9):1973-1984.
[57]Mengali U, D'Andrea A N. Synchronization Techniques for Digital Receivers. New York: Plenum Press,1997.
[58]Proakis J G. Digital Communications. Fourth ed., McGraw-Hill Science/Engineering/Math,2000.
[59]吕洪生,杨新德.实用卫星通信工程.成都：电子科技大学出版社,1994.
[60]Xilinx. Virtex-6FPGA SelectIO Resources User Guide,2010. UG361(v1.3).
[61]曹志刚,钱亚生.现代通信原理.北京：清华大学出版社,2007.
[62]应启珩,冯一云,窦维蓓.离散时间信号分析和处理.北京：清华大学出版社,2001.
[63]Xilinx. Virtex-6FPGA DSP48E1Slice User Guide, September,2009. UG369(v1.2).
[64]Sklar B. Digital Communications:Fundamentals and Applications. Second ed., Prentice Hall PTR,2001.
[65]Gardner F M. Interpolation in Digital Modems—Part Ⅰ:Fundamentals. IEEE Transactions on Communications,1993,41(3):501-507.
[66]Erup L, Gardner F M, Harris R A. Interpolation in Digital Modems—Part Ⅱ:Implementation and Performance. IEEE Transactions on Communications,1993,41(6):998-1008.
[67]Gardner F M. A BPSK/QPSK Timing-Error Detector for Sampled Receivers. IEEE Transac-tions on Communications,1986, COM-34(5):423-429.
[68]Oerder M, Meyr H. Digital Filter and Square Timing Recovery. IEEE Transactions on Com-munications,1988,36(5):605-612.
[69]郑大春,项海格.一种全数字QAM接收机符号定时和载波相位恢复方案.通信学报,1998,19(7)：83-88.
[70]郑君里,应启珩,杨为理.信号与系统.北京：高等教育出版社,2000.
[71]Xilinx. CORDIC v4.0Product Specification, April,2009. DS249.
[72]Yang J, Werner J J, Dumont G A. The Multimodulus Blind Equalization and Its Generalized Algorithms. IEEE Journal on Selected Areas in Communications,2002,20(5):997-1015.
[73]He L, Amin M G, Reed C, et al. A hybrid adaptive blind equalization algorithm for QAM sig-nals in wireless communications. IEEE Transactions on Signal Processing,2004,52(7):2058-2069.
[74]Banovic K, Abdel-Raheem E, Khalid M A S. Hybrid methods for blind adaptive equalization: New results and comparisons. Proceedings of Proceedings of the10th IEEE Symposium on Computers and Communications,2005.
[75]Banovic K, Abdel-Raheem E, Khalid M A S. A novel radius-adjusted approach for blind adaptive equalization. IEEE Signal Processing Letters,2006,13(1):37-40.
[76]Banovic K, Khalid M A S, Abdel-Raheem E. A configurable fractionally-spaced blind adaptive equalizer for QAM demodulators. Digital Signal Processing,2007,17:1071-1088.
[77]Parhi K K. VLSI Digital Signal Processing Systems:Design and Implementation. New York: Wiley,1999.
[78]Shanbhag N R, Parhi K K. Relaxed look-ahead pipelined LMS adaptive filters and their appli-cation to ADPCM coder. IEEE Transactions on Circuits and Systems—Ⅱ: Analog and Digital Signal Processing,1993,40(12):753-766.
[79]Granata J, Conner M, Tolimieri R. A Tensor Product Factorization of the Linear Convolution. IEEE Transactions on Circuits and Systems,1991,38(11):1364-1366.
[80]Granata J, Conner M, Tolimieri R. The Tensor Product:A Mathematical Programming Lan-guage for FFTs and other Fast DSP Operations. IEEE Signal Processing Magazine,1992,9(1):40-48.
[81]Cheng C, Parhi K K. Hardware efficient fast parallel FIR filter structures based on iterated short convolution. Proceedings of Circuits and Systems,2004. ISC AS'04. Proceedings of the2004International Symposium on,2004.
[82]Cheng C, Parhi K K. Hardware efficient fast parallel FIR filter structures based on iterat-ed short convolution. IEEE Transactions on Circuits and Systems—Ⅰ: Regular Papers,2004,51(8):1492-1500.
[83]Cheng C, Parhi K K. Low Cost Parallel Adaptive Filter Structures. Proceedings of Conference Record of the39th Asilomar Conference on Signals, Systems and Computers,2005.354-358.
[84]http://spib.rice.edu/.
[85]季仲梅,杨洪生,王大鸣,等.通信中的同步技术及应用.北京：清华大学出版社,2008.
[86]Shayan Y, Le-Ngoc T. All digital phase-locked loop:concepts, design and applications. IEE Proceedings F on Radar and Signal Processing,1989,136(1):53-56.
[87]Jablon N K. Joint Blind Equalization, Carrier Recovery and Timing Recovery for High-Order QAM Signal Constellations. IEEE Transactions on Signal Processing,1992,40(6):1383-1398.
[88]Kim K Y, Choi H J. Design of Carrier Recovery Algorithm for High-Order QAM with Large Frequence Acquisition Range. Proceedings of IEEE International Conference on Communica-tions,2001.1016-1020.
[89]Sari H, Moridi S. New Phase and Frequency Detectors for Carrier Recovery in PSK and QAM Systems. IEEE Transactions on Communications,1988,36(9):1035-1043.
[90]中华人民共和国广播电影电视行业标准GY/T170-2001.有线数字电视广播信道编码与调制规范.国家广播电影电视总局,2001.
[91]National Semiconductor. ADC10D1000/ADC10D1500Low Power,10-Bit, Dual1.0/1.5GSP-S or Single2.0/3.0GSPS ADC,2011.
[92]National Semiconductor. LMX2531High Performance Frequency Synthesizer System with Integrated VCO, September,2010.