数字系统时延故障的低成本高质量测试方法研究
摘要
随着集成电路高度集成化及深亚微米技术的迅速发展，为了确保数字电路的正确性，不仅需要验证其逻辑功能是否正确，更需要验证其时序特性。在这种环境下，测试功耗、测试数据量和覆盖率的问题变得更加严重。针对这三个方面的问题，本文提出了有效的解决方案，降低时延故障测试的成本，提高测试质量。
论文工作包括：
(1)在功耗方面，主要有基于DFT的方法和基于X位填充的方法。基于DFT的方法主要有多周期测试和分块测试两种方法。在时延故障测试中，这些方法因其固有的限制，无法在既不影响测试成本又能保住测试质量的前提下降低功耗。多周期测试方法可以降低电路的测试功耗，但是它可能引起捕获冲突，造成一部分故障不可测，从而需要更多的测试向量来保证覆盖率。本文提出基于整数线性规划的优化方法来实现多周期捕获冲突最小化，保证在几乎不增加数据量的前提下降低功耗。分块测试方法通过在一个周期内只测试一部分电路实现低功耗，其弊端是不能覆盖所有故障，需要额外测试耦合部分以保证覆盖率。本文提出最小化耦合部分的方法，实现了无覆盖率损失的低功耗测试方案。相对于DFT方法，基于X位填充的方法成本低，但是它不能直接应用在线性数据压缩的测试环境中，因为X位填充不仅要实现低功耗，而且要满足向量可以被压缩。本文通过分析线性解码器的结构和原理，将向量可压缩的约束条件转换为虚拟电路，成为电路的一部分，将问题转换为传统X位填充问题，从而可以利用以往的低功耗方法来降低测试功耗。
(2)在测试数据方面，时延故障测试比功能测试需要更多的测试数据量。测试数据量不仅包括测试激励还包括测试响应，很多方法只关注两个问题中的一个。本文分析电路的拓扑结构和时延故障的特征，提出了基于广播的测试激励压缩方法和基于异或门网络的测试响应压缩器，极大程度地降低了测试数据量。
(3)在覆盖率方面，时延故障的测试方法中，宽边延迟测试应用最为广泛，但是它的覆盖率最低。本文对宽边测试的ATPG过程进行分析，找到了覆盖率低的本质原因，提出了新的冲突度量标准用来解决触发器的选择和分配问题，打破了宽边测试的功能依赖，覆盖率可以提高到增强扫描测试方法的水平。
With the increasing density of very large scale integrated (VLSI) circuits and thedevelopment of deep sub-micron technology, VLSI testing becomes more and more dif-ficult. Functional testing methods are not sufcient to guarantee the correctness of thecircuits; therefore, delay fault testing is an essential step for modern VLSI circuits. Testpower, volume, and time are the major test cost parameters that must be minimized whileachieving the desired level of fault coverage. For delay testing, these problems becomemore and more complex, therefore, we propose new methods to solve these problems.
We make the following contributions:
Previous low-power methods mainly include design-for-testability (DFT)-basedmethods and X-filling methods. These methods are very efcient in reducing test powerfor stuck-at fault testing. However, most of them cannot apply to delay testing directly.We want to propose new approaches to reduce test power without loss of test quality:
(1) The use of only a subset of scan cells to capture responses in a cycle may causecapture violations, thereby leading to fault coverage loss. In order to restore the originalfault coverage, new test patterns must be generated, leading to higher test-data volume.In this paper, we propose a scan-cell clustering method that can support multiple capturecycles in delay testing without increasing test-data volume.
(2) Partition the circuits into many parts and test each part independently can re-duce test power, however, it may make some testable faults in standard broadside testinguntestable. A new test application scheme called partial launch-on-capture (PLOC) isproposed to solve the problem. It allows only a part of scan flip-flops to be active in thelaunch cycle and capture cycle. In order to guarantee that all testable faults in the stan-dard broadside testing can be detected in the new test scheme, extra eforts are requiredto check the overlapping part. Therefore, a new scan flip-flop partitioning algorithm isproposed to minimize the overlapping part.
(3) DFT-based methods can reduce test power efciently, but they need hardwareoverhead. X-filling methods can efciently reduce test power with low overhead. How-ever, traditional X-filling methods cannot be reused in the linear decompressor basedcompression (LDC) environment. In this paper, we propose a virtual circuit model to make the linear decompressor transparent to the external testing. As a result, existingX-filling methods can be reused to reduce test power. Sufcient experimental results arepresented to demonstrate the efciency of the proposed method.
Test data compression is a much more difcult problem for launch-on-capture (LOC,for short) delay testing because test data for LOC delay testing is much more than thatof stuck-at fault testing, since LOC delay fault test generation in the two-frame circuitmodel can specify much more care bits which is hard to do compaction and compres-sion. A new scan architecture is proposed to compress test stimulus data, compact testresponses and reduce test application time for LOC delay fault testing. Sufcient con-ditions are presented for including any pair of scan flip-flops into the same group forLOC transition, non-robust path delay and robust path delay fault testing. Test data forLOC delay testing based on the new scan architecture can be compressed significantly.Sufcient experimental results are presented to show the efectiveness of the method.
Among the methods for delay testing, broadside testing is widely used for its easilyimplementation, but the fault coverage is low. This paper presents a new method forimproving transition fault coverage in hybrid scan testing. These techniques are based ona novel test application scheme, in order to break the functional dependency of broadsidetesting. Experimental results show that fault coverage based on the proposed method iscomparable to enhanced scan.
论文工作包括：
(1)在功耗方面，主要有基于DFT的方法和基于X位填充的方法。基于DFT的方法主要有多周期测试和分块测试两种方法。在时延故障测试中，这些方法因其固有的限制，无法在既不影响测试成本又能保住测试质量的前提下降低功耗。多周期测试方法可以降低电路的测试功耗，但是它可能引起捕获冲突，造成一部分故障不可测，从而需要更多的测试向量来保证覆盖率。本文提出基于整数线性规划的优化方法来实现多周期捕获冲突最小化，保证在几乎不增加数据量的前提下降低功耗。分块测试方法通过在一个周期内只测试一部分电路实现低功耗，其弊端是不能覆盖所有故障，需要额外测试耦合部分以保证覆盖率。本文提出最小化耦合部分的方法，实现了无覆盖率损失的低功耗测试方案。相对于DFT方法，基于X位填充的方法成本低，但是它不能直接应用在线性数据压缩的测试环境中，因为X位填充不仅要实现低功耗，而且要满足向量可以被压缩。本文通过分析线性解码器的结构和原理，将向量可压缩的约束条件转换为虚拟电路，成为电路的一部分，将问题转换为传统X位填充问题，从而可以利用以往的低功耗方法来降低测试功耗。
(2)在测试数据方面，时延故障测试比功能测试需要更多的测试数据量。测试数据量不仅包括测试激励还包括测试响应，很多方法只关注两个问题中的一个。本文分析电路的拓扑结构和时延故障的特征，提出了基于广播的测试激励压缩方法和基于异或门网络的测试响应压缩器，极大程度地降低了测试数据量。
(3)在覆盖率方面，时延故障的测试方法中，宽边延迟测试应用最为广泛，但是它的覆盖率最低。本文对宽边测试的ATPG过程进行分析，找到了覆盖率低的本质原因，提出了新的冲突度量标准用来解决触发器的选择和分配问题，打破了宽边测试的功能依赖，覆盖率可以提高到增强扫描测试方法的水平。
With the increasing density of very large scale integrated (VLSI) circuits and thedevelopment of deep sub-micron technology, VLSI testing becomes more and more dif-ficult. Functional testing methods are not sufcient to guarantee the correctness of thecircuits; therefore, delay fault testing is an essential step for modern VLSI circuits. Testpower, volume, and time are the major test cost parameters that must be minimized whileachieving the desired level of fault coverage. For delay testing, these problems becomemore and more complex, therefore, we propose new methods to solve these problems.
We make the following contributions:
Previous low-power methods mainly include design-for-testability (DFT)-basedmethods and X-filling methods. These methods are very efcient in reducing test powerfor stuck-at fault testing. However, most of them cannot apply to delay testing directly.We want to propose new approaches to reduce test power without loss of test quality:
(1) The use of only a subset of scan cells to capture responses in a cycle may causecapture violations, thereby leading to fault coverage loss. In order to restore the originalfault coverage, new test patterns must be generated, leading to higher test-data volume.In this paper, we propose a scan-cell clustering method that can support multiple capturecycles in delay testing without increasing test-data volume.
(2) Partition the circuits into many parts and test each part independently can re-duce test power, however, it may make some testable faults in standard broadside testinguntestable. A new test application scheme called partial launch-on-capture (PLOC) isproposed to solve the problem. It allows only a part of scan flip-flops to be active in thelaunch cycle and capture cycle. In order to guarantee that all testable faults in the stan-dard broadside testing can be detected in the new test scheme, extra eforts are requiredto check the overlapping part. Therefore, a new scan flip-flop partitioning algorithm isproposed to minimize the overlapping part.
(3) DFT-based methods can reduce test power efciently, but they need hardwareoverhead. X-filling methods can efciently reduce test power with low overhead. How-ever, traditional X-filling methods cannot be reused in the linear decompressor basedcompression (LDC) environment. In this paper, we propose a virtual circuit model to make the linear decompressor transparent to the external testing. As a result, existingX-filling methods can be reused to reduce test power. Sufcient experimental results arepresented to demonstrate the efciency of the proposed method.
Test data compression is a much more difcult problem for launch-on-capture (LOC,for short) delay testing because test data for LOC delay testing is much more than thatof stuck-at fault testing, since LOC delay fault test generation in the two-frame circuitmodel can specify much more care bits which is hard to do compaction and compres-sion. A new scan architecture is proposed to compress test stimulus data, compact testresponses and reduce test application time for LOC delay fault testing. Sufcient con-ditions are presented for including any pair of scan flip-flops into the same group forLOC transition, non-robust path delay and robust path delay fault testing. Test data forLOC delay testing based on the new scan architecture can be compressed significantly.Sufcient experimental results are presented to show the efectiveness of the method.
Among the methods for delay testing, broadside testing is widely used for its easilyimplementation, but the fault coverage is low. This paper presents a new method forimproving transition fault coverage in hybrid scan testing. These techniques are based ona novel test application scheme, in order to break the functional dependency of broadsidetesting. Experimental results show that fault coverage based on the proposed method iscomparable to enhanced scan.
引文
[1] Bryant R E, Cheng K T, Kahng A B, et al. Limitations and Challenges of Computer-AidedDesign Technology for CMOS VLSI. Proceedings of the IEEE,2001,89(3):341–365.
[2] Needham W M. Nanometer Technology Challenges for Test and Test Equipment. Computer,1999,32(11):52–57.
[3] Cheng K T, Dey S, Rodgers M, et al. Test Challenges for Deep Sub-Micron Technologies.Proceedings of ACM/IEEE Design Automation Conference (DAC),2000.142–149.
[4] International SEMATECH. The International Technology Roadmap for Semiconductors(ITRS):2001Edition. http://public.itrs.net/Files/2001ITRS/Home.htm,2001.
[5] Krstic A, Cheng K T. Delay Fault Testing for VLSI Circuits. Kluwer Academic Publishers,1998.
[6] Chalsani P R, Bhawmik S, Acharya A, et al. Design of Testable VLSI Circuits with MinimumArea Overhead. IEEE Transactions on Computers,1989,38(9):1460–1462.
[7] McCluskey E J. Built-In Self-Test Techniques. IEEE Design&Test of Computers,1985.21–28.
[8] McCluskey E J. Built-In Self-Test Structures. IEEE Design&Test of Computers,1985.29–36.
[9] Nag P, Gattiker A, SWei, et al. Modeling the Economics of Testing: A DFT Perspective. IEEEDesign&Test of Computers,2002,19:29–41.
[10] Roth J P, Bouricius W G, Schneider P R. Programmed Algorithms to Compute Tests to Detectand Distinguish Between Failures in Logic Circuits. IEEE Trans. On Electronic Computers,1967, EC-16:567–579.
[11] Goel P. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Cir-cuits. IEEE Trans. Comput.,1981,30:215–222.
[12] Fujiwara H, Shimono T. On the Acceleration of Test Generation Algorithms. IEEE Trans.Comput.,1983,32:1137–1144.
[13] L-TWang, C-WWu, XWen. VLSI Test Principle and Architectures: Design for Testability.Morgan Kaufmann,2006.
[14] Abramovici M, Breuer M A, Friedman A D. Digital Systems Testing and Testable Design.IEEE Press,1994.
[15] Kunz W, Pradhan D K. Accelerated dynamic learning for test pattern generation in combina-tional circuits. IEEE Trans. on Computer-Aided Design,1993,12(5):684–694.
[16] Niermann T, Patel J H. HITEC: A Test Generation package for sequential circuits. Proceedingsof European Design Automation Conf. IEEE,1991.214–218.
[17] Schulz M H, Trischler E, Sarfert T M. SOCRATES: A highly efcient automatic test patterngeneration system. IEEE Trans. Computer-Aided Design,1988,7(1):126–137.
[18] Cheng K T. Gate Level Test Generation for Sequential Circuits. ACM Transactions on DesignAutomation of Electronic Systems,1996,1(4):405–442.
[19] Kim Y C, Saluja K K. Sequential Test Generators: Past, Present and Future. Integration, theVLSI journal,1998,26(1-2):41–54.
[20] Tsai K H, Tompson R, Rajski J, et al. STARATPG: A High Speed Test Pattern Generation forLarge Scan Designs. Proceedings of IEEE International Test Conference (ITC),1999.1021–1030.
[21] Pomeranz I, Reddy S M. Delay Fault Models for VLSI Circuits. Integration, the VLSI journal,1998,26(1-2):21–40.
[22] Lin Y C, Lu F, Cheng K T. Pseudofunctional testing. IEEE Trans. on Computer-Aided Design,2006,25(8):1535–1546.
[23] Lin X, Press R, Rajski J, et al. High-Frequency, At-Speed Scan Testing. IEEE Des. Test,2003,20(5):17–25.
[24] Savir J, Patil S. On broad-side delay test. IEEE Trans. Very Large Scale Integr. Syst.,1994,2:368–372.
[25] Savir J, Patil S. Scan-based transition test. IEEE Trans. on Computer-Aided Design,1993,12:1232–1241.
[26] DasGupta S, Walther R, Williams T, et al. An Enhancement to LSSD and Some Applications ofLSSD in Reliability, Availability, and Serviceability. Proceedings of11th IEEE Fault-TolerantComputing Symp.,1981.32–34.
[27] Rosinger P M, Gonciari P T, Al-Hashimi B M, et al. Analyzing Trade-ofs in Scan Powerand Test Data Compression for Systems-on-a-Chip. IEE Proceedings, Computers and DigitalTechniques,2002,149(5).
[28] Saxena J, Butler K M, Jayaram V B, et al. A Case Study of IR-Drop in Structured At-SpeedTesting. Proceedings of In Int. Test Conf,2003.1098–1104.
[29] Girard P. Survey of Low-Power Testing of VLSI Circuits. IEEE Design&Test of Computers,2002,19(3):80–90.
[30] Najm F N. A Survey of Power Estimation Techniques in VLSI Circuits. IEEE Transactions onVLSI Systems,1994,2(4):446–455.
[31] Pedram M. Power Minimization in IC Design: Principles and Applications. ACM Transactionson Design Automation of Electronic Systems,1996,1(1):3–56.
[32] Chandrakasan A, Brodersen R. Low Power Digital CMOS Design. Kluwer Academic Pub-lishers,1995.
[33] Chakravarty S, Dabholkar V. Two Techniques for Minimizing Power Dissipation in Scan Cir-cuits During Test Application. Proceedings of IEEE Asian Test Symposium (ATS),1994.324–329.
[34] Chakravarty S, Monzel J, Agrawal V D, et al. Power Dissipation During Testing: Should WeWorry About it? Proceedings of IEEE VLSI Test Symposium (VTS),1997.456.
[35] Girard P. Low Power Testing of VLSI Circuits: Problems and Solutions. Proceedings ofInternational Symposium on Quality of Electronic Design (ISQED),2000.173–180.
[36] Wang J, Walker D M H, Majhi A, et al. Power Supply Noise in Delay Testing. Proceedings ofIEEE International Test Conference (ITC),2006.17.3.
[37] Kajihara S, Ishida K, Miyase K. Test Vector Modification for Power Reduction During ScanTesting. Proceedings of IEEE VLSI Test Symposium (VTS),2002.160–165.
[38] Gerstendo¨rfer S, Wunderlich H J. Minimized Power Consumption For Scan-Based Bist. Pro-ceedings of the1999IEEE International Test Conference,1999.77–84.
[39] Girard P, Landrault C, Pravossoudovitch S, et al. Reduction of power consumption during testapplication by test vector ordering. IEE Electronics Letters,1997,33(21):1752–1754.
[40] Girard P, Landrault C, Pravossoudovitch S, et al. Reducing power consumption during testapplication by test vector ordering. Proceedings of International Symposium on Circuits andSystems (ISCAS),1998.296–299.
[41] Girard P, Guiller L, Landrault C, et al. A test vector ordering technique for switching activityreduction during test operation. Proceedings of Proc. IEEE Great Lakes Symposium on VLSI,1999.24–27.
[42] Butler K M, Saxena J, Fryars T, et al. Minimizing power consumption in scan testing: patterngeneration and DFT techniques. Proceedings of IEEE International Test Conference,2004.355–364.
[43] Czysz D, Kassab M, Lin X, et al. Low-power scan operation in test compression environment.Trans. Comp.-Aided Des. Integ. Cir. Sys.,2009,28(11):1742–1755.
[44] Chen Z, Feng J, Xiang D, et al. Scan chain configuration based X-filling for low power andhigh quality testing. IET Computers&Digital Techniques,2010,4(1):1–13.
[45] Wen X, Miyase K, Suzuki T, et al. A Highly-Guided X-Filling Method for Efective Low-Capture-Power Scan Test Generation. Proceedings of International Conference on ComputerDesign (ICCD),2006.251–258.
[46] Remersaro S, Lin X, Zhang Z, et al. Preferred Fill: A Scalable Method to Reduce CapturePower for Scan Based Designs. Proceedings of IEEE International Test Conference (ITC,2006.
[47] Wen X, Yamashita Y, Morishima S, et al. On Low-Capture-Power Test Generation for ScanTesting. Proceedings of IEEE VLSI Test Symposium (VTS),2005.
[48] Remersaro S, Lin X, Reddy S M, et al. Low Shift and Capture Power Scan Tests. Proceed-ings of the20th International Conference on VLSI Design held jointly with6th InternationalConference: Embedded Systems,2007.793–798.
[49] Li J, Xu Q, Hu Y, et al. iFill: An Impact-Oriented X-Filling Method for Shift-and Capture-Power Reduction in At-Speed Scan-Based Testing. Proceedings of Design, Automation, andTest in Europe (DATE),2008.1184–1189.
[50] Wen X, Yamashita Y, Morishima S, et al. Low-capture-power test generation for scan-basedat-speed testing. Proceedings of IEEE International Test Conference (ITC),2005.
[51] Nourani M, Tehranipoor M, Ahmed N. Low-Transition Test Pattern Generation for BIST-BasedApplications. IEEE Trans. Comput.,2008,57(3):303–315.
[52] Lee H, Pomeranz I, Reddy S M. On Complete Functional Broadside Tests for Transition Faults.IEEE Trans. on CAD of Integrated Circuits and Systems,2008.583–587.
[53] Wang S, Gupta S K. An Automatic Test Pattern Generator for Minimizing Switching ActivityDuring Scan Testing. IEEE Transactions on Computer-Aided Design of Integrated Circuits,2002,21(8).
[54] Corno F, Prinetto P, Rebaudengo M, et al. A Test Pattern Generation methodology for lowpower consumption. Proceedings of IEEE VLSI Test Symposium (VTS),1998.453–460.
[55] Li W, Reddy S M, Pomeranz I. On Test Generation for Transition Faults with Minimized PeakPower Dissipation. Proceedings of ACM/IEEE Design Automation Conference (DAC),2004.504–509.
[56] Li J, Liu X, Zhang Y, et al. On capture power-aware test data compression for scan-based test-ing. Proceedings of IEEE/ACM International Conference on Computer-Aided Design,2008.67–72.
[57] Liu X, Xu Q. On Simultaneous Shift-and Capture-Power Reduction in Linear Decompressor-Based Test Compression Environment. Proceedings of IEEE International Test Conference,2009.
[58] Wu M F, Huang J L, Wen X, et al. Power supply noise reduction for at-speed scan testingin linear-decompression environment. IEEE Trans. Comp.-Aided Des. Integ. Cir. Sys.,2009,28:1767–1776.
[59] Miyase K, Yamato Y, Noda K, et al. A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. Proceedings of In-ternational Conference on Computer-Aided Design,2009.97–104.
[60] Girard P, Guiller L, Landrault C, et al. Circuit partitioning for low power BIST design withminimized peak power consumption. Proceedings of IEEE Asian Test Symposium (ATS),1999.89–94.
[61] Bonhom Y, Girard P, Guiller L, et al. A Gated Clock Scheme for Low Power Scan Testingof Logic ICs or Embedded Cores. Proceedings of the10th Asian Test Symposium,2001.253–258.
[62] Sankaralingam R, Pouya B, Touba N A. Reducing Power Dissipation During Test Using ScanChain Disable. Proceedings of VLSI Test Symposium,2001.319–324.
[63] Saha I, Bhattacharya B B, Zhang S, et al. Planar Straight-Line Embedding of Double-TreeScan Architecture on a Rectangular Grid. Fundam. Inf.,2008,89(2-3):331–344.
[64] Girard P, Guiller L, Landrault C, et al. A Modified Clock Scheme for a Low Power BIST TestPattern Generator. Proceedings of IEEE VLSI Test Symposium (VTS),2001.306–311.
[65] Chen J J, Yang C K, Lee K J. Test pattern generation and clock disabling for simultaneoustest time and power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems,2003.363–370.
[66] Bhunia S, Mahmoodi H, Ghosh D, et al. Low-Power Scan Design Using First-Level SupplyGating. IEEE Transactions on VLSI Systems,2005,13(3):384–395.
[67] Huang T C, Lee K J. Reduction of Power Consumption in Scan-Based Circuits during TestApplication by an Input Control Technique. IEEE Transactions on Computer-Aided Design,2001,20(7):911–917.
[68] Monteiro J, Devadas S, Ghosh A. Sequential Logic Optimization for Low Power Using In-put Disabling Precomputation Architectures. IEEE Transactions on Computer-Aided Design,1998,17(3):279–284.
[69] Nicolici N, Al-Hashimi B M, Williams A C. Minimisation of Power Dissipation During TestApplication in Full Scan Sequential Circuits Using Primary Input Freezing. IEE Proceedings,Computers and Digital Techniques,2000,147(5):313–322.
[70] Huang T C, Lee K J. An Input Control Technique for Power Reduction in Scan Circuits DuringTest Application. Proceedings of IEEE Asian Test Symposium (ATS),1999.315–320.
[71] Whetsel L. Adapting Scan Architectures for Low Power Operation. Proceedings of IEEEInternational Test Conference,2000.863–.
[72] Nicolici N, Al-Hashimi B M. Multiple Scan Chains for Power Minimization during Test Ap-plication in Sequential Circuits. IEEE Trans. Comput.,2002,51:721–734.
[73] Wang S J, Li K S M, Chen S C, et al. Scan-chain partition for high test-data compressibilityand low shift power under routing constraint. Trans. Comp.-Aided Des. Integ. Cir. Sys.,2009,28(5):716–727.
[74] Lin C Y, Lin H C, Chen H M. On reducing test power and test volume by selective patterncompression schemes. IEEE Trans. Very Large Scale Integr. Syst.,2010,18(8):1220–1224.
[75] Chen Z, Xiang D, Yin B. A power-efective scan architecture using scan flip-flops clusteringand post-generation filling. Proceedings of the19th ACM Great Lakes symposium on VLSI,2009.517–522.
[76] MElm, H-JWunderlich, MEImhof, et al. Scan Chain Clustering for Test Power Reduction.Proceedings of ACM/IEEE Design Automation Conference (DAC),2008.828–833.
[77] Xu Q, Hu D, Xiang D. Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction.Proceedings of IEEE International Test Conference (ITC), paper25.2,2007.
[78] Rosinger P M, Al-Hashimi B M, Nicolici N. Scan architecture with mutually exclusive scansegment activation for shift-and capture-power reduction. IEEE Trans. on CAD of IntegratedCircuits and Systems,2004.1142–1153.
[79] Touba N A. Survey of Test Vector Compression Techniques. IEEE Des. Test,2006,23(4):294–303.
[80] Jas A, Touba N A. Test Vector Decompression via Cyclical Scan Chains and Its Application toTesting Core-Based Designs. Proceedings of Int. Test Conf,1998.458–464.
[81] Chandra A, Chakrabarty K. Test Data Compression for System-on-a-Chip Using GolombCodes. Proceedings of the18th IEEE VLSI Test Symposium,2000.113–118.
[82] Chandra A, Chakrabarty K. System-on-a-chip test-data compression and decompression ar-chitectures based on Golomb codes. IEEE Transactions on Computer-Aided Design,2001,20(3):355–368.
[83] Reddy S M, Miyase K, Kajihara S, et al. On test data volume reduction for multiple scan chaindesigns. ACM Trans. Des. Autom. Electron. Syst.,2003,8:460–469.
[84] Li L, Chakrabarty K, Touba N A. Test data compression using dictionaries with selectiveentries and fixed-length indices. ACM Trans. Des. Autom. Electron. Syst.,2003,8:470–490.
[85] Jas A, Ghosh-dastidar J, Ng M, et al. An Efcient Test Vector Compression Scheme UsingSelective Hufman Coding. IEEE Trans. Computer-Aided Design Integr. Circuits Syst,2003,22:797–806.
[86] Wang Z, Chakrabarty K. Test data compression using selective encoding of scan slices. IEEETrans. Very Large Scale Integr. Syst.,2008,16(11):1429–1440.
[87] Chandra A, Chakrabarty K. Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes. IEEE Trans. Comput.,2003,52:1076–1088.
[88] Gonciari P T, Gonciari P T, Al-hashimi B M, et al. Variable-length Input Hufman Coding forSystem-on-a-Chip Test. IEEE Trans. on Computer-Aided Design,2003,22:783–796.
[89] Konemann B. LFSR-coded test patterns for scan designs,. Proceedings of European TestConference,1991.
[90] Bayraktaroglu I, Orailoglu A. Concurrent Application of Compaction and Compression forTest Time and Data Volume Reduction in Scan Designs. IEEE Trans. Comput.,2003,52:1480–1489.
[91] Mitra S, Kim K S. XPAND: An Efcient Test Stimulus Compression Technique. IEEE Trans.Comput.,2006,55:163–173.
[92] Rajski J, Tyszer J, Kassab M, et al. Embedded Deterministic Test for Low Cost ManufacturingTest. Proceedings of Int. Test Conf,2002.301–310.
[93] Krishna C V, Touba N A. Reducing Test Dat Volume Using LFSR Reseeding with Seed Com-pression. Proceedings of the2002IEEE International Test Conference,2002.321–330.
[94] Volkerink E H, Mitra S. Efcient Seed Utilization for Reseeding based Compression. Proceed-ings of the21st IEEE VLSI Test Symposium,2003.232–237.
[95] Hamzaoglu I, Patel J H. Reducing Test Application Time for Full Scan Embedded Cores.Proceedings of International Symposium on Fault-Tolerant Computing (FTCS),1999.260–267.
[96] Xiang D, Li K, Sun J, et al. Reconfigured Scan Forest for Test Application Cost, Test DataVolume, and Test Power Reduction. IEEE Trans. Comput.,2007,56(4):557–562.
[97] Miyase K, Kajihara S. Optimal Scan Tree Construction with Test Vector Modification for TestCompression. Asian Test Symposium,2003,0:136–141.
[98] Miyase K, Kajihara S, Reddy S M. Multiple Scan Tree Design with Test Vector Modification.Proceedings of the13th Asian Test Symposium,2004.76–81.
[99] Lee K J, Chen J J, Huang C H. Using a single input to support multiple scan chains. Pro-ceedings of the1998IEEE/ACM international conference on Computer-aided design,1998.74–78.
[100] Chen Z, Seth S, Xiang D, et al. A Unified Solution to Scan Test Volume, Time, and PowerMinimization. Proceedings of the23rd International Conference on VLSI Design,2010.9–14.
[101] Pandey A R, Patel T H. Reconfiguration Technique for Reducing Test Time and Test DataVolume in Illinois Scan Architecture Based Designs. Proceedings of the20th IEEE VLSI TestSymposium,2002.9–15.
[102] Samaranayake S, Gizdarski E, Sitchinava N, et al. A Reconfigurable Shared Scan-in Architec-ture. Proceedings of the21st IEEE VLSI Test Symposium,2003.9–15.
[103] Narayanan S, Breuer M A. Reconfiguration Techniques for a Single Scan Chain. IEEE Trans-actions on Computer-Aided Design,1995,14(6):750–765.
[104] Devtaprasanna N, Gunda A, Krishnamurthy P, et al. Methods for improving transition delayfault coverage using broadside tests. IEEE International Test Conference (ITC),2005,0:265–.
[105] Pomeranz I, Reddy S M. On Achieving Complete Coverage of Delay Faults in Full ScanCircuits using Locally Available Lines. Proceedings of IEEE International Test Conference,1999.923–931.
[106] Mao W, Ciletti M D. Reducing correlation to improve coverage of delay faults in scan-pathdesign. IEEE Trans. Computer-Aided Design,1994,13(5):638–646.
[107] Ahmed N, Tehranipoor M. Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. Proceedings of the20th IEEE International Symposium on Defect and FaultTolerance in VLSI Systems,2005.187–198.
[108] Amhed N, Tehranipoor M. Improving transition delay test using a hybrid method. IEEE,2006.402–412.
[109] Wang S. Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Techniquefor High Fault Coverage and Compact Test Sets. Proceedings of Design, Automation and Testin Europe (DATE),2004.1296–1301.
[110] Chen Z, Chakrabarty K, Xiang D. MVP: Capture-power reduction with minimum-violationspartitioning for delay testing. Proceedings of IEEE/ACM International Conference onComputer-Aided Design,2010.149–154.
[111] Chen Z, Chakrabarty K, Xiang D. MVP: Minimum-Violations Partitioning for Reducing Cap-ture Power in At-Speed Delay-Fault Testing. IEEE Trans. Computer-Aided Design,2011,30(11):1762–1767.
[112] Chen Z, Xiang D. Low-capture-power at-speed testing using partial launch-on-capture testscheme. Proceedings of IEEE VLSI Test Symposium,2010.141–146.
[113] Chen Z, Li J, Xiang D, et al. Virtual Circuit Model for Low Power Scan Testing in LinearDecompressor-Based Compression Environment. Proceedings of the13th Asian Test Sympo-sium,2011.96–101.
[114] Chen Z, Xiang D, Wang L T. Scan flip-flop grouping to compress test data and compact testresponses for broadside delay testing. accepted to appear in ACM Trans. on Design Automationof Electronic Systems..
[115] Chen Z, Yin B, Xiang D. Conflict driven scan chain configuration for high transition faultcoverage and low test power. Proceedings of Asia and South Pacific Design Automation Con-ference,2009.666–671.
[116] Chen Z, Xiang D, Yin B. The ATPG Conflict-Driven Scheme for High Transition Fault Cov-erage and Low Test Cost. Proceedings of27th IEEE VLSI Test Symposium,2009.146–151.
[117] Chen Z, Xiang D. A novel test application scheme for high transition fault coverage and lowtest cost. Trans. Comp.-Aided Des. Integ. Cir. Sys.,2010,29(6):966–976.
[118] Girard P, Guiller L, Landrault C, et al. Low Power BIST Design by Hypergraph Partitioning:Methodology and Architectures. Proceedings of IEEE International Test Conference,2000.652–661.
[119] Ko H F, Nicolici N. A Novel Automated Scan Chain Division Method for Shift and CapturePower Reduction in Broadside At-Speed Test.2008.2092–2097.
[120] Lee K J, Hsu S J, Ho C M. Test Power Reduction with Multiple Capture Orders. Proceedingsof the13th Asian Test Symposium,2004.26–31.
[121] Zhang Z, Reddy S M, Pomeranz I, et al. Enhancing Delay Fault Coverage through Low PowerSegmented Scan. Proceedings of European Test Symposium’06,2006.21–28.
[122] Garey M R, Johnson D S. Computers and Intractability; A Guide to the Theory of NP-Completeness. New York, NY, USA: W. H. Freeman&Co.,1990.
[123] Bertsimas D, Tsitsiklis J N. Introduction to linear optimization. Athena Scientific,1997.
[124] Raghavan P, Tompson C D. Randomized rounding: a technique for provably good algorithmsand algorithmic proofs. Combinatorica,1987,7(4):365–374.
[125] Wu X, Falkenstern P, Chakrabarty K, et al. Scan-chain design and optimization for three-dimensional integrated circuits. J. Emerg. Technol. Comput. Syst.,2009,5:9:1–9:26.
[126] Bonhom Y, Girard P, Guiller L, et al. Design of Routing-Constrained Low Power Scan Chains.Proceedings of the conference on Design, automation and test in Europe-Volume1,2004.62–67.
[127] Berthelot D, Chaudhuri S, Savoj H. An Efcient Linear Time Algorithm for Scan Chain Opti-mization and Repartitioning. Proceedings of IEEE International Test Conference,2002.781–787.
[128] Gupta P, Kahng A B, Mantik S. Routing-aware scan chain ordering. ACM Transactions onDesign Automation of Electronic Systems,2005,10(3):546–560.
[129] Sankaralingam R, Oruganti R R, Touba N A. Static Compaction Techniques to Control ScanVector Power Dissipation. Proceedings of VLSI Test Symposium,2000.35–40.
[130] Karypis G, Aggarwal R, Kumar V, et al. Multilevel hypergraph partitioning: application inVLSI domain. Proceedings of the34th annual Design Automation Conference,1997.526–529.
[131] Hamzaoglu I, Patel J H. Compact two-pattern test set generation for combinational and fullscan circuits. Proceedings of International Test Conference. IEEE,1998.957–963.
[132] Hamzaoglu I, Patel J H. Test set compaction algorithms for combinational circuits. IEEETrans. on Computer-Aided Design,2000,19(8):957–963.
[133] Pomeranz I, Reddy S M. Test compaction for transition faults under transparent scan. Pro-ceedings of IEEE/ACM Design Automation and Test in Europe Conf. ACM,2006.1–6.
[134] Pomeranz I, Reddy S M. Compactest: A method to generate compact test sets for combina-tional circuits. volume12,1993.1040–1049.
[135] Wang Z, Walker D. Dynamic Compaction for High Quality Delay Test. VLSI Test Symposium,IEEE,2008,0:243–248.
[136] Xiang D, Li K, Fujiwara H, et al. Generating compact robust and non-robust tests for completecoverage of path delay faults based on stuck-at tests. Proceedings of24th IEEE Int. Conferenceon Computer Design,2006.446–451.
[137] Ivanov A, Tsuji B K, Zorian Y. Programmable BIST Space Compactors. IEEE Trans. Comput.,1996,45(12):1393–1404.
[138] Chakrabarty K, Murray B T, Hayes J P. Optimal Zero-Aliasing Space Compaction of TestResponses. IEEE Trans. Comput.,1998,47(11):1171–1187.
[139] Mitra S, Kim K S. X-Compact: An Efcient Response Compaction Technique for Test CostReduction. Proceedings of IEEE International Test Conference,2002.311–.
[140] Naruse M, Pomeranz I, Reddy S M, et al. On-chip Compression of Output Responses withUnknown Values Using LFSR Reseeding. IEEE International Test Conference,2003.1060–1068.
[141] Pomeranz I, Kundu S, Reddy S M. On output response compression in the presence of un-known output values. Proceedings of the39th annual Design Automation Conference,2002.255–258.
[142] Patel J H, Lumetta S S, Reddy S M. Application of Saluja-Karpovsky Compactors to TestResponses with Many Unknowns. Proceedings of the21st IEEE VLSI Test Symposium,2003.107–112.
[143] Kinsman A B, Nicolici N. Trade-Ofs in Test Data Compression and Deterministic X-Maskingof Responses. IEEE Trans. Comput.,2011,60(4):498–507.
[144] Rajski J, Tyszer J, Wang C, et al. Finite memory test response compactors for embedded testapplications. IEEE Trans. Comp.-Aided Des. Integ. Cir. Sys.,2005,24:622–634.
[145] Rajski J, Tyszer J, Kassab M, et al. Embedded deterministic test. IEEE Trans. Comput.,2004,23:776–792.
[146] Xiang D, Yin B, Cheng K T. Dynamic Test Compaction for Transition Faults in BroadsideScan Testing Based on an Influence Cone Measure. Proceedings of27th IEEE VLSI TestSymposium,2009.251–256.
[147] Shah M A, Patel J H. Enhancement of the Illinois Scan Architecture for Use with MultipleScan Inputs. VLSI, IEEE Computer Society Annual Symposium on,2004.167–172.
[148] Cheng K T. Transition fault testing for sequential circuits. IEEE Trans. on Computer-AidedDesign,1993,12(12):1971–1983.
[149] Liu X, Hsiao M, Chakravarty S, et al. Efcient techniques for transition fault testing. ACMTrans. on Design Automation of Electronic Systems,2005,10(2):258–278.
[150] Liou J J, Wang L C, Cheng K T, et al. Enhancing test efciency for delay fault testing usingmultiple-clocked schemes. Proceedings of ACM/IEEE Design Automation Conference. ACM,2002.371–374.
[151] Shao Y, Pomeranz I, Reddy S M. On Generating High Quality Tests for Transition Faults.Proceedings of the11th Asian Test Symposium,2002.1–8.
[152] Smith G L. Model for delay faults based upon paths. Proceedings of International Test Con-ference. IEEE,1984.342–349.
[153] Cheng K T, Devadas S, Keutzer K. Robust delay-fault test generation and synthesis for testa-bility under a standard scan design methodology. Proceedings of the28th ACM/IEEE DesignAutomation Conference,1991.80–86.
[154] Chen Z, Seth S, Xiang D. A novel hybrid delay testing scheme with low test power, volume,and time. Proceedings of IEEE VLSI Test Symposium,2010.307–312.
[155] Pomeranz I, Reddy S M. Enhanced Broadside Testing for Improved Transition Fault Coverage.Proceedings of the16th Asian Test Symposium,2007.479–484.
[156] Wang S J, Peng K L, Hsiao K C, et al. Layout-aware scan chain reorder for launch-of-shifttransition test coverage. ACM Trans. Des. Autom. Electron. Syst.,2008,13(4):64:1–64:16.
[157] Xu G, Singh A D. Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. Pro-ceedings of IEEE International conference on VLSI Design,2007.763–768.
[2] Needham W M. Nanometer Technology Challenges for Test and Test Equipment. Computer,1999,32(11):52–57.
[3] Cheng K T, Dey S, Rodgers M, et al. Test Challenges for Deep Sub-Micron Technologies.Proceedings of ACM/IEEE Design Automation Conference (DAC),2000.142–149.
[4] International SEMATECH. The International Technology Roadmap for Semiconductors(ITRS):2001Edition. http://public.itrs.net/Files/2001ITRS/Home.htm,2001.
[5] Krstic A, Cheng K T. Delay Fault Testing for VLSI Circuits. Kluwer Academic Publishers,1998.
[6] Chalsani P R, Bhawmik S, Acharya A, et al. Design of Testable VLSI Circuits with MinimumArea Overhead. IEEE Transactions on Computers,1989,38(9):1460–1462.
[7] McCluskey E J. Built-In Self-Test Techniques. IEEE Design&Test of Computers,1985.21–28.
[8] McCluskey E J. Built-In Self-Test Structures. IEEE Design&Test of Computers,1985.29–36.
[9] Nag P, Gattiker A, SWei, et al. Modeling the Economics of Testing: A DFT Perspective. IEEEDesign&Test of Computers,2002,19:29–41.
[10] Roth J P, Bouricius W G, Schneider P R. Programmed Algorithms to Compute Tests to Detectand Distinguish Between Failures in Logic Circuits. IEEE Trans. On Electronic Computers,1967, EC-16:567–579.
[11] Goel P. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Cir-cuits. IEEE Trans. Comput.,1981,30:215–222.
[12] Fujiwara H, Shimono T. On the Acceleration of Test Generation Algorithms. IEEE Trans.Comput.,1983,32:1137–1144.
[13] L-TWang, C-WWu, XWen. VLSI Test Principle and Architectures: Design for Testability.Morgan Kaufmann,2006.
[14] Abramovici M, Breuer M A, Friedman A D. Digital Systems Testing and Testable Design.IEEE Press,1994.
[15] Kunz W, Pradhan D K. Accelerated dynamic learning for test pattern generation in combina-tional circuits. IEEE Trans. on Computer-Aided Design,1993,12(5):684–694.
[16] Niermann T, Patel J H. HITEC: A Test Generation package for sequential circuits. Proceedingsof European Design Automation Conf. IEEE,1991.214–218.
[17] Schulz M H, Trischler E, Sarfert T M. SOCRATES: A highly efcient automatic test patterngeneration system. IEEE Trans. Computer-Aided Design,1988,7(1):126–137.
[18] Cheng K T. Gate Level Test Generation for Sequential Circuits. ACM Transactions on DesignAutomation of Electronic Systems,1996,1(4):405–442.
[19] Kim Y C, Saluja K K. Sequential Test Generators: Past, Present and Future. Integration, theVLSI journal,1998,26(1-2):41–54.
[20] Tsai K H, Tompson R, Rajski J, et al. STARATPG: A High Speed Test Pattern Generation forLarge Scan Designs. Proceedings of IEEE International Test Conference (ITC),1999.1021–1030.
[21] Pomeranz I, Reddy S M. Delay Fault Models for VLSI Circuits. Integration, the VLSI journal,1998,26(1-2):21–40.
[22] Lin Y C, Lu F, Cheng K T. Pseudofunctional testing. IEEE Trans. on Computer-Aided Design,2006,25(8):1535–1546.
[23] Lin X, Press R, Rajski J, et al. High-Frequency, At-Speed Scan Testing. IEEE Des. Test,2003,20(5):17–25.
[24] Savir J, Patil S. On broad-side delay test. IEEE Trans. Very Large Scale Integr. Syst.,1994,2:368–372.
[25] Savir J, Patil S. Scan-based transition test. IEEE Trans. on Computer-Aided Design,1993,12:1232–1241.
[26] DasGupta S, Walther R, Williams T, et al. An Enhancement to LSSD and Some Applications ofLSSD in Reliability, Availability, and Serviceability. Proceedings of11th IEEE Fault-TolerantComputing Symp.,1981.32–34.
[27] Rosinger P M, Gonciari P T, Al-Hashimi B M, et al. Analyzing Trade-ofs in Scan Powerand Test Data Compression for Systems-on-a-Chip. IEE Proceedings, Computers and DigitalTechniques,2002,149(5).
[28] Saxena J, Butler K M, Jayaram V B, et al. A Case Study of IR-Drop in Structured At-SpeedTesting. Proceedings of In Int. Test Conf,2003.1098–1104.
[29] Girard P. Survey of Low-Power Testing of VLSI Circuits. IEEE Design&Test of Computers,2002,19(3):80–90.
[30] Najm F N. A Survey of Power Estimation Techniques in VLSI Circuits. IEEE Transactions onVLSI Systems,1994,2(4):446–455.
[31] Pedram M. Power Minimization in IC Design: Principles and Applications. ACM Transactionson Design Automation of Electronic Systems,1996,1(1):3–56.
[32] Chandrakasan A, Brodersen R. Low Power Digital CMOS Design. Kluwer Academic Pub-lishers,1995.
[33] Chakravarty S, Dabholkar V. Two Techniques for Minimizing Power Dissipation in Scan Cir-cuits During Test Application. Proceedings of IEEE Asian Test Symposium (ATS),1994.324–329.
[34] Chakravarty S, Monzel J, Agrawal V D, et al. Power Dissipation During Testing: Should WeWorry About it? Proceedings of IEEE VLSI Test Symposium (VTS),1997.456.
[35] Girard P. Low Power Testing of VLSI Circuits: Problems and Solutions. Proceedings ofInternational Symposium on Quality of Electronic Design (ISQED),2000.173–180.
[36] Wang J, Walker D M H, Majhi A, et al. Power Supply Noise in Delay Testing. Proceedings ofIEEE International Test Conference (ITC),2006.17.3.
[37] Kajihara S, Ishida K, Miyase K. Test Vector Modification for Power Reduction During ScanTesting. Proceedings of IEEE VLSI Test Symposium (VTS),2002.160–165.
[38] Gerstendo¨rfer S, Wunderlich H J. Minimized Power Consumption For Scan-Based Bist. Pro-ceedings of the1999IEEE International Test Conference,1999.77–84.
[39] Girard P, Landrault C, Pravossoudovitch S, et al. Reduction of power consumption during testapplication by test vector ordering. IEE Electronics Letters,1997,33(21):1752–1754.
[40] Girard P, Landrault C, Pravossoudovitch S, et al. Reducing power consumption during testapplication by test vector ordering. Proceedings of International Symposium on Circuits andSystems (ISCAS),1998.296–299.
[41] Girard P, Guiller L, Landrault C, et al. A test vector ordering technique for switching activityreduction during test operation. Proceedings of Proc. IEEE Great Lakes Symposium on VLSI,1999.24–27.
[42] Butler K M, Saxena J, Fryars T, et al. Minimizing power consumption in scan testing: patterngeneration and DFT techniques. Proceedings of IEEE International Test Conference,2004.355–364.
[43] Czysz D, Kassab M, Lin X, et al. Low-power scan operation in test compression environment.Trans. Comp.-Aided Des. Integ. Cir. Sys.,2009,28(11):1742–1755.
[44] Chen Z, Feng J, Xiang D, et al. Scan chain configuration based X-filling for low power andhigh quality testing. IET Computers&Digital Techniques,2010,4(1):1–13.
[45] Wen X, Miyase K, Suzuki T, et al. A Highly-Guided X-Filling Method for Efective Low-Capture-Power Scan Test Generation. Proceedings of International Conference on ComputerDesign (ICCD),2006.251–258.
[46] Remersaro S, Lin X, Zhang Z, et al. Preferred Fill: A Scalable Method to Reduce CapturePower for Scan Based Designs. Proceedings of IEEE International Test Conference (ITC,2006.
[47] Wen X, Yamashita Y, Morishima S, et al. On Low-Capture-Power Test Generation for ScanTesting. Proceedings of IEEE VLSI Test Symposium (VTS),2005.
[48] Remersaro S, Lin X, Reddy S M, et al. Low Shift and Capture Power Scan Tests. Proceed-ings of the20th International Conference on VLSI Design held jointly with6th InternationalConference: Embedded Systems,2007.793–798.
[49] Li J, Xu Q, Hu Y, et al. iFill: An Impact-Oriented X-Filling Method for Shift-and Capture-Power Reduction in At-Speed Scan-Based Testing. Proceedings of Design, Automation, andTest in Europe (DATE),2008.1184–1189.
[50] Wen X, Yamashita Y, Morishima S, et al. Low-capture-power test generation for scan-basedat-speed testing. Proceedings of IEEE International Test Conference (ITC),2005.
[51] Nourani M, Tehranipoor M, Ahmed N. Low-Transition Test Pattern Generation for BIST-BasedApplications. IEEE Trans. Comput.,2008,57(3):303–315.
[52] Lee H, Pomeranz I, Reddy S M. On Complete Functional Broadside Tests for Transition Faults.IEEE Trans. on CAD of Integrated Circuits and Systems,2008.583–587.
[53] Wang S, Gupta S K. An Automatic Test Pattern Generator for Minimizing Switching ActivityDuring Scan Testing. IEEE Transactions on Computer-Aided Design of Integrated Circuits,2002,21(8).
[54] Corno F, Prinetto P, Rebaudengo M, et al. A Test Pattern Generation methodology for lowpower consumption. Proceedings of IEEE VLSI Test Symposium (VTS),1998.453–460.
[55] Li W, Reddy S M, Pomeranz I. On Test Generation for Transition Faults with Minimized PeakPower Dissipation. Proceedings of ACM/IEEE Design Automation Conference (DAC),2004.504–509.
[56] Li J, Liu X, Zhang Y, et al. On capture power-aware test data compression for scan-based test-ing. Proceedings of IEEE/ACM International Conference on Computer-Aided Design,2008.67–72.
[57] Liu X, Xu Q. On Simultaneous Shift-and Capture-Power Reduction in Linear Decompressor-Based Test Compression Environment. Proceedings of IEEE International Test Conference,2009.
[58] Wu M F, Huang J L, Wen X, et al. Power supply noise reduction for at-speed scan testingin linear-decompression environment. IEEE Trans. Comp.-Aided Des. Integ. Cir. Sys.,2009,28:1767–1776.
[59] Miyase K, Yamato Y, Noda K, et al. A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment. Proceedings of In-ternational Conference on Computer-Aided Design,2009.97–104.
[60] Girard P, Guiller L, Landrault C, et al. Circuit partitioning for low power BIST design withminimized peak power consumption. Proceedings of IEEE Asian Test Symposium (ATS),1999.89–94.
[61] Bonhom Y, Girard P, Guiller L, et al. A Gated Clock Scheme for Low Power Scan Testingof Logic ICs or Embedded Cores. Proceedings of the10th Asian Test Symposium,2001.253–258.
[62] Sankaralingam R, Pouya B, Touba N A. Reducing Power Dissipation During Test Using ScanChain Disable. Proceedings of VLSI Test Symposium,2001.319–324.
[63] Saha I, Bhattacharya B B, Zhang S, et al. Planar Straight-Line Embedding of Double-TreeScan Architecture on a Rectangular Grid. Fundam. Inf.,2008,89(2-3):331–344.
[64] Girard P, Guiller L, Landrault C, et al. A Modified Clock Scheme for a Low Power BIST TestPattern Generator. Proceedings of IEEE VLSI Test Symposium (VTS),2001.306–311.
[65] Chen J J, Yang C K, Lee K J. Test pattern generation and clock disabling for simultaneoustest time and power reduction. IEEE Trans. on CAD of Integrated Circuits and Systems,2003.363–370.
[66] Bhunia S, Mahmoodi H, Ghosh D, et al. Low-Power Scan Design Using First-Level SupplyGating. IEEE Transactions on VLSI Systems,2005,13(3):384–395.
[67] Huang T C, Lee K J. Reduction of Power Consumption in Scan-Based Circuits during TestApplication by an Input Control Technique. IEEE Transactions on Computer-Aided Design,2001,20(7):911–917.
[68] Monteiro J, Devadas S, Ghosh A. Sequential Logic Optimization for Low Power Using In-put Disabling Precomputation Architectures. IEEE Transactions on Computer-Aided Design,1998,17(3):279–284.
[69] Nicolici N, Al-Hashimi B M, Williams A C. Minimisation of Power Dissipation During TestApplication in Full Scan Sequential Circuits Using Primary Input Freezing. IEE Proceedings,Computers and Digital Techniques,2000,147(5):313–322.
[70] Huang T C, Lee K J. An Input Control Technique for Power Reduction in Scan Circuits DuringTest Application. Proceedings of IEEE Asian Test Symposium (ATS),1999.315–320.
[71] Whetsel L. Adapting Scan Architectures for Low Power Operation. Proceedings of IEEEInternational Test Conference,2000.863–.
[72] Nicolici N, Al-Hashimi B M. Multiple Scan Chains for Power Minimization during Test Ap-plication in Sequential Circuits. IEEE Trans. Comput.,2002,51:721–734.
[73] Wang S J, Li K S M, Chen S C, et al. Scan-chain partition for high test-data compressibilityand low shift power under routing constraint. Trans. Comp.-Aided Des. Integ. Cir. Sys.,2009,28(5):716–727.
[74] Lin C Y, Lin H C, Chen H M. On reducing test power and test volume by selective patterncompression schemes. IEEE Trans. Very Large Scale Integr. Syst.,2010,18(8):1220–1224.
[75] Chen Z, Xiang D, Yin B. A power-efective scan architecture using scan flip-flops clusteringand post-generation filling. Proceedings of the19th ACM Great Lakes symposium on VLSI,2009.517–522.
[76] MElm, H-JWunderlich, MEImhof, et al. Scan Chain Clustering for Test Power Reduction.Proceedings of ACM/IEEE Design Automation Conference (DAC),2008.828–833.
[77] Xu Q, Hu D, Xiang D. Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction.Proceedings of IEEE International Test Conference (ITC), paper25.2,2007.
[78] Rosinger P M, Al-Hashimi B M, Nicolici N. Scan architecture with mutually exclusive scansegment activation for shift-and capture-power reduction. IEEE Trans. on CAD of IntegratedCircuits and Systems,2004.1142–1153.
[79] Touba N A. Survey of Test Vector Compression Techniques. IEEE Des. Test,2006,23(4):294–303.
[80] Jas A, Touba N A. Test Vector Decompression via Cyclical Scan Chains and Its Application toTesting Core-Based Designs. Proceedings of Int. Test Conf,1998.458–464.
[81] Chandra A, Chakrabarty K. Test Data Compression for System-on-a-Chip Using GolombCodes. Proceedings of the18th IEEE VLSI Test Symposium,2000.113–118.
[82] Chandra A, Chakrabarty K. System-on-a-chip test-data compression and decompression ar-chitectures based on Golomb codes. IEEE Transactions on Computer-Aided Design,2001,20(3):355–368.
[83] Reddy S M, Miyase K, Kajihara S, et al. On test data volume reduction for multiple scan chaindesigns. ACM Trans. Des. Autom. Electron. Syst.,2003,8:460–469.
[84] Li L, Chakrabarty K, Touba N A. Test data compression using dictionaries with selectiveentries and fixed-length indices. ACM Trans. Des. Autom. Electron. Syst.,2003,8:470–490.
[85] Jas A, Ghosh-dastidar J, Ng M, et al. An Efcient Test Vector Compression Scheme UsingSelective Hufman Coding. IEEE Trans. Computer-Aided Design Integr. Circuits Syst,2003,22:797–806.
[86] Wang Z, Chakrabarty K. Test data compression using selective encoding of scan slices. IEEETrans. Very Large Scale Integr. Syst.,2008,16(11):1429–1440.
[87] Chandra A, Chakrabarty K. Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes. IEEE Trans. Comput.,2003,52:1076–1088.
[88] Gonciari P T, Gonciari P T, Al-hashimi B M, et al. Variable-length Input Hufman Coding forSystem-on-a-Chip Test. IEEE Trans. on Computer-Aided Design,2003,22:783–796.
[89] Konemann B. LFSR-coded test patterns for scan designs,. Proceedings of European TestConference,1991.
[90] Bayraktaroglu I, Orailoglu A. Concurrent Application of Compaction and Compression forTest Time and Data Volume Reduction in Scan Designs. IEEE Trans. Comput.,2003,52:1480–1489.
[91] Mitra S, Kim K S. XPAND: An Efcient Test Stimulus Compression Technique. IEEE Trans.Comput.,2006,55:163–173.
[92] Rajski J, Tyszer J, Kassab M, et al. Embedded Deterministic Test for Low Cost ManufacturingTest. Proceedings of Int. Test Conf,2002.301–310.
[93] Krishna C V, Touba N A. Reducing Test Dat Volume Using LFSR Reseeding with Seed Com-pression. Proceedings of the2002IEEE International Test Conference,2002.321–330.
[94] Volkerink E H, Mitra S. Efcient Seed Utilization for Reseeding based Compression. Proceed-ings of the21st IEEE VLSI Test Symposium,2003.232–237.
[95] Hamzaoglu I, Patel J H. Reducing Test Application Time for Full Scan Embedded Cores.Proceedings of International Symposium on Fault-Tolerant Computing (FTCS),1999.260–267.
[96] Xiang D, Li K, Sun J, et al. Reconfigured Scan Forest for Test Application Cost, Test DataVolume, and Test Power Reduction. IEEE Trans. Comput.,2007,56(4):557–562.
[97] Miyase K, Kajihara S. Optimal Scan Tree Construction with Test Vector Modification for TestCompression. Asian Test Symposium,2003,0:136–141.
[98] Miyase K, Kajihara S, Reddy S M. Multiple Scan Tree Design with Test Vector Modification.Proceedings of the13th Asian Test Symposium,2004.76–81.
[99] Lee K J, Chen J J, Huang C H. Using a single input to support multiple scan chains. Pro-ceedings of the1998IEEE/ACM international conference on Computer-aided design,1998.74–78.
[100] Chen Z, Seth S, Xiang D, et al. A Unified Solution to Scan Test Volume, Time, and PowerMinimization. Proceedings of the23rd International Conference on VLSI Design,2010.9–14.
[101] Pandey A R, Patel T H. Reconfiguration Technique for Reducing Test Time and Test DataVolume in Illinois Scan Architecture Based Designs. Proceedings of the20th IEEE VLSI TestSymposium,2002.9–15.
[102] Samaranayake S, Gizdarski E, Sitchinava N, et al. A Reconfigurable Shared Scan-in Architec-ture. Proceedings of the21st IEEE VLSI Test Symposium,2003.9–15.
[103] Narayanan S, Breuer M A. Reconfiguration Techniques for a Single Scan Chain. IEEE Trans-actions on Computer-Aided Design,1995,14(6):750–765.
[104] Devtaprasanna N, Gunda A, Krishnamurthy P, et al. Methods for improving transition delayfault coverage using broadside tests. IEEE International Test Conference (ITC),2005,0:265–.
[105] Pomeranz I, Reddy S M. On Achieving Complete Coverage of Delay Faults in Full ScanCircuits using Locally Available Lines. Proceedings of IEEE International Test Conference,1999.923–931.
[106] Mao W, Ciletti M D. Reducing correlation to improve coverage of delay faults in scan-pathdesign. IEEE Trans. Computer-Aided Design,1994,13(5):638–646.
[107] Ahmed N, Tehranipoor M. Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique. Proceedings of the20th IEEE International Symposium on Defect and FaultTolerance in VLSI Systems,2005.187–198.
[108] Amhed N, Tehranipoor M. Improving transition delay test using a hybrid method. IEEE,2006.402–412.
[109] Wang S. Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Techniquefor High Fault Coverage and Compact Test Sets. Proceedings of Design, Automation and Testin Europe (DATE),2004.1296–1301.
[110] Chen Z, Chakrabarty K, Xiang D. MVP: Capture-power reduction with minimum-violationspartitioning for delay testing. Proceedings of IEEE/ACM International Conference onComputer-Aided Design,2010.149–154.
[111] Chen Z, Chakrabarty K, Xiang D. MVP: Minimum-Violations Partitioning for Reducing Cap-ture Power in At-Speed Delay-Fault Testing. IEEE Trans. Computer-Aided Design,2011,30(11):1762–1767.
[112] Chen Z, Xiang D. Low-capture-power at-speed testing using partial launch-on-capture testscheme. Proceedings of IEEE VLSI Test Symposium,2010.141–146.
[113] Chen Z, Li J, Xiang D, et al. Virtual Circuit Model for Low Power Scan Testing in LinearDecompressor-Based Compression Environment. Proceedings of the13th Asian Test Sympo-sium,2011.96–101.
[114] Chen Z, Xiang D, Wang L T. Scan flip-flop grouping to compress test data and compact testresponses for broadside delay testing. accepted to appear in ACM Trans. on Design Automationof Electronic Systems..
[115] Chen Z, Yin B, Xiang D. Conflict driven scan chain configuration for high transition faultcoverage and low test power. Proceedings of Asia and South Pacific Design Automation Con-ference,2009.666–671.
[116] Chen Z, Xiang D, Yin B. The ATPG Conflict-Driven Scheme for High Transition Fault Cov-erage and Low Test Cost. Proceedings of27th IEEE VLSI Test Symposium,2009.146–151.
[117] Chen Z, Xiang D. A novel test application scheme for high transition fault coverage and lowtest cost. Trans. Comp.-Aided Des. Integ. Cir. Sys.,2010,29(6):966–976.
[118] Girard P, Guiller L, Landrault C, et al. Low Power BIST Design by Hypergraph Partitioning:Methodology and Architectures. Proceedings of IEEE International Test Conference,2000.652–661.
[119] Ko H F, Nicolici N. A Novel Automated Scan Chain Division Method for Shift and CapturePower Reduction in Broadside At-Speed Test.2008.2092–2097.
[120] Lee K J, Hsu S J, Ho C M. Test Power Reduction with Multiple Capture Orders. Proceedingsof the13th Asian Test Symposium,2004.26–31.
[121] Zhang Z, Reddy S M, Pomeranz I, et al. Enhancing Delay Fault Coverage through Low PowerSegmented Scan. Proceedings of European Test Symposium’06,2006.21–28.
[122] Garey M R, Johnson D S. Computers and Intractability; A Guide to the Theory of NP-Completeness. New York, NY, USA: W. H. Freeman&Co.,1990.
[123] Bertsimas D, Tsitsiklis J N. Introduction to linear optimization. Athena Scientific,1997.
[124] Raghavan P, Tompson C D. Randomized rounding: a technique for provably good algorithmsand algorithmic proofs. Combinatorica,1987,7(4):365–374.
[125] Wu X, Falkenstern P, Chakrabarty K, et al. Scan-chain design and optimization for three-dimensional integrated circuits. J. Emerg. Technol. Comput. Syst.,2009,5:9:1–9:26.
[126] Bonhom Y, Girard P, Guiller L, et al. Design of Routing-Constrained Low Power Scan Chains.Proceedings of the conference on Design, automation and test in Europe-Volume1,2004.62–67.
[127] Berthelot D, Chaudhuri S, Savoj H. An Efcient Linear Time Algorithm for Scan Chain Opti-mization and Repartitioning. Proceedings of IEEE International Test Conference,2002.781–787.
[128] Gupta P, Kahng A B, Mantik S. Routing-aware scan chain ordering. ACM Transactions onDesign Automation of Electronic Systems,2005,10(3):546–560.
[129] Sankaralingam R, Oruganti R R, Touba N A. Static Compaction Techniques to Control ScanVector Power Dissipation. Proceedings of VLSI Test Symposium,2000.35–40.
[130] Karypis G, Aggarwal R, Kumar V, et al. Multilevel hypergraph partitioning: application inVLSI domain. Proceedings of the34th annual Design Automation Conference,1997.526–529.
[131] Hamzaoglu I, Patel J H. Compact two-pattern test set generation for combinational and fullscan circuits. Proceedings of International Test Conference. IEEE,1998.957–963.
[132] Hamzaoglu I, Patel J H. Test set compaction algorithms for combinational circuits. IEEETrans. on Computer-Aided Design,2000,19(8):957–963.
[133] Pomeranz I, Reddy S M. Test compaction for transition faults under transparent scan. Pro-ceedings of IEEE/ACM Design Automation and Test in Europe Conf. ACM,2006.1–6.
[134] Pomeranz I, Reddy S M. Compactest: A method to generate compact test sets for combina-tional circuits. volume12,1993.1040–1049.
[135] Wang Z, Walker D. Dynamic Compaction for High Quality Delay Test. VLSI Test Symposium,IEEE,2008,0:243–248.
[136] Xiang D, Li K, Fujiwara H, et al. Generating compact robust and non-robust tests for completecoverage of path delay faults based on stuck-at tests. Proceedings of24th IEEE Int. Conferenceon Computer Design,2006.446–451.
[137] Ivanov A, Tsuji B K, Zorian Y. Programmable BIST Space Compactors. IEEE Trans. Comput.,1996,45(12):1393–1404.
[138] Chakrabarty K, Murray B T, Hayes J P. Optimal Zero-Aliasing Space Compaction of TestResponses. IEEE Trans. Comput.,1998,47(11):1171–1187.
[139] Mitra S, Kim K S. X-Compact: An Efcient Response Compaction Technique for Test CostReduction. Proceedings of IEEE International Test Conference,2002.311–.
[140] Naruse M, Pomeranz I, Reddy S M, et al. On-chip Compression of Output Responses withUnknown Values Using LFSR Reseeding. IEEE International Test Conference,2003.1060–1068.
[141] Pomeranz I, Kundu S, Reddy S M. On output response compression in the presence of un-known output values. Proceedings of the39th annual Design Automation Conference,2002.255–258.
[142] Patel J H, Lumetta S S, Reddy S M. Application of Saluja-Karpovsky Compactors to TestResponses with Many Unknowns. Proceedings of the21st IEEE VLSI Test Symposium,2003.107–112.
[143] Kinsman A B, Nicolici N. Trade-Ofs in Test Data Compression and Deterministic X-Maskingof Responses. IEEE Trans. Comput.,2011,60(4):498–507.
[144] Rajski J, Tyszer J, Wang C, et al. Finite memory test response compactors for embedded testapplications. IEEE Trans. Comp.-Aided Des. Integ. Cir. Sys.,2005,24:622–634.
[145] Rajski J, Tyszer J, Kassab M, et al. Embedded deterministic test. IEEE Trans. Comput.,2004,23:776–792.
[146] Xiang D, Yin B, Cheng K T. Dynamic Test Compaction for Transition Faults in BroadsideScan Testing Based on an Influence Cone Measure. Proceedings of27th IEEE VLSI TestSymposium,2009.251–256.
[147] Shah M A, Patel J H. Enhancement of the Illinois Scan Architecture for Use with MultipleScan Inputs. VLSI, IEEE Computer Society Annual Symposium on,2004.167–172.
[148] Cheng K T. Transition fault testing for sequential circuits. IEEE Trans. on Computer-AidedDesign,1993,12(12):1971–1983.
[149] Liu X, Hsiao M, Chakravarty S, et al. Efcient techniques for transition fault testing. ACMTrans. on Design Automation of Electronic Systems,2005,10(2):258–278.
[150] Liou J J, Wang L C, Cheng K T, et al. Enhancing test efciency for delay fault testing usingmultiple-clocked schemes. Proceedings of ACM/IEEE Design Automation Conference. ACM,2002.371–374.
[151] Shao Y, Pomeranz I, Reddy S M. On Generating High Quality Tests for Transition Faults.Proceedings of the11th Asian Test Symposium,2002.1–8.
[152] Smith G L. Model for delay faults based upon paths. Proceedings of International Test Con-ference. IEEE,1984.342–349.
[153] Cheng K T, Devadas S, Keutzer K. Robust delay-fault test generation and synthesis for testa-bility under a standard scan design methodology. Proceedings of the28th ACM/IEEE DesignAutomation Conference,1991.80–86.
[154] Chen Z, Seth S, Xiang D. A novel hybrid delay testing scheme with low test power, volume,and time. Proceedings of IEEE VLSI Test Symposium,2010.307–312.
[155] Pomeranz I, Reddy S M. Enhanced Broadside Testing for Improved Transition Fault Coverage.Proceedings of the16th Asian Test Symposium,2007.479–484.
[156] Wang S J, Peng K L, Hsiao K C, et al. Layout-aware scan chain reorder for launch-of-shifttransition test coverage. ACM Trans. Des. Autom. Electron. Syst.,2008,13(4):64:1–64:16.
[157] Xu G, Singh A D. Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. Pro-ceedings of IEEE International conference on VLSI Design,2007.763–768.